Software APIs
dif_pattgen_autogen.c
1 // Copyright lowRISC contributors (OpenTitan project).
2 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3 // SPDX-License-Identifier: Apache-2.0
4 
5 // THIS FILE HAS BEEN GENERATED, DO NOT EDIT MANUALLY. COMMAND:
6 // util/make_new_dif.py --mode=regen --only=autogen
7 
8 #include "sw/device/lib/dif/autogen/dif_pattgen_autogen.h"
9 
10 #include <stdint.h>
11 
12 #include "sw/device/lib/dif/dif_base.h"
13 
14 #include "pattgen_regs.h" // Generated.
15 
16 OT_WARN_UNUSED_RESULT
17 dif_result_t dif_pattgen_init(mmio_region_t base_addr, dif_pattgen_t *pattgen) {
18  if (pattgen == NULL) {
19  return kDifBadArg;
20  }
21 
22  pattgen->base_addr = base_addr;
23 
24  return kDifOk;
25 }
26 
27 dif_result_t dif_pattgen_alert_force(const dif_pattgen_t *pattgen,
28  dif_pattgen_alert_t alert) {
29  if (pattgen == NULL) {
30  return kDifBadArg;
31  }
32 
33  bitfield_bit32_index_t alert_idx;
34  switch (alert) {
35  case kDifPattgenAlertFatalFault:
36  alert_idx = PATTGEN_ALERT_TEST_FATAL_FAULT_BIT;
37  break;
38  default:
39  return kDifBadArg;
40  }
41 
42  uint32_t alert_test_reg = bitfield_bit32_write(0, alert_idx, true);
43  mmio_region_write32(pattgen->base_addr,
44  (ptrdiff_t)PATTGEN_ALERT_TEST_REG_OFFSET, alert_test_reg);
45 
46  return kDifOk;
47 }
48 
49 /**
50  * Get the corresponding interrupt register bit offset of the IRQ.
51  */
52 static bool pattgen_get_irq_bit_index(dif_pattgen_irq_t irq,
53  bitfield_bit32_index_t *index_out) {
54  switch (irq) {
55  case kDifPattgenIrqDoneCh0:
56  *index_out = PATTGEN_INTR_COMMON_DONE_CH0_BIT;
57  break;
58  case kDifPattgenIrqDoneCh1:
59  *index_out = PATTGEN_INTR_COMMON_DONE_CH1_BIT;
60  break;
61  default:
62  return false;
63  }
64 
65  return true;
66 }
67 
68 static dif_irq_type_t irq_types[] = {
69  kDifIrqTypeEvent,
70  kDifIrqTypeEvent,
71 };
72 
73 OT_WARN_UNUSED_RESULT
74 dif_result_t dif_pattgen_irq_get_type(const dif_pattgen_t *pattgen,
75  dif_pattgen_irq_t irq,
76  dif_irq_type_t *type) {
77  if (pattgen == NULL || type == NULL || irq == kDifPattgenIrqDoneCh1 + 1) {
78  return kDifBadArg;
79  }
80 
81  *type = irq_types[irq];
82 
83  return kDifOk;
84 }
85 
86 OT_WARN_UNUSED_RESULT
87 dif_result_t dif_pattgen_irq_get_state(
88  const dif_pattgen_t *pattgen, dif_pattgen_irq_state_snapshot_t *snapshot) {
89  if (pattgen == NULL || snapshot == NULL) {
90  return kDifBadArg;
91  }
92 
93  *snapshot = mmio_region_read32(pattgen->base_addr,
94  (ptrdiff_t)PATTGEN_INTR_STATE_REG_OFFSET);
95 
96  return kDifOk;
97 }
98 
99 OT_WARN_UNUSED_RESULT
100 dif_result_t dif_pattgen_irq_acknowledge_state(
101  const dif_pattgen_t *pattgen, dif_pattgen_irq_state_snapshot_t snapshot) {
102  if (pattgen == NULL) {
103  return kDifBadArg;
104  }
105 
106  mmio_region_write32(pattgen->base_addr,
107  (ptrdiff_t)PATTGEN_INTR_STATE_REG_OFFSET, snapshot);
108 
109  return kDifOk;
110 }
111 
112 OT_WARN_UNUSED_RESULT
113 dif_result_t dif_pattgen_irq_is_pending(const dif_pattgen_t *pattgen,
114  dif_pattgen_irq_t irq,
115  bool *is_pending) {
116  if (pattgen == NULL || is_pending == NULL) {
117  return kDifBadArg;
118  }
119 
120  bitfield_bit32_index_t index;
121  if (!pattgen_get_irq_bit_index(irq, &index)) {
122  return kDifBadArg;
123  }
124 
125  uint32_t intr_state_reg = mmio_region_read32(
126  pattgen->base_addr, (ptrdiff_t)PATTGEN_INTR_STATE_REG_OFFSET);
127 
128  *is_pending = bitfield_bit32_read(intr_state_reg, index);
129 
130  return kDifOk;
131 }
132 
133 OT_WARN_UNUSED_RESULT
134 dif_result_t dif_pattgen_irq_acknowledge_all(const dif_pattgen_t *pattgen) {
135  if (pattgen == NULL) {
136  return kDifBadArg;
137  }
138 
139  // Writing to the register clears the corresponding bits (Write-one clear).
140  mmio_region_write32(pattgen->base_addr,
141  (ptrdiff_t)PATTGEN_INTR_STATE_REG_OFFSET, UINT32_MAX);
142 
143  return kDifOk;
144 }
145 
146 OT_WARN_UNUSED_RESULT
147 dif_result_t dif_pattgen_irq_acknowledge(const dif_pattgen_t *pattgen,
148  dif_pattgen_irq_t irq) {
149  if (pattgen == NULL) {
150  return kDifBadArg;
151  }
152 
153  bitfield_bit32_index_t index;
154  if (!pattgen_get_irq_bit_index(irq, &index)) {
155  return kDifBadArg;
156  }
157 
158  // Writing to the register clears the corresponding bits (Write-one clear).
159  uint32_t intr_state_reg = bitfield_bit32_write(0, index, true);
160  mmio_region_write32(pattgen->base_addr,
161  (ptrdiff_t)PATTGEN_INTR_STATE_REG_OFFSET, intr_state_reg);
162 
163  return kDifOk;
164 }
165 
166 OT_WARN_UNUSED_RESULT
167 dif_result_t dif_pattgen_irq_force(const dif_pattgen_t *pattgen,
168  dif_pattgen_irq_t irq, const bool val) {
169  if (pattgen == NULL) {
170  return kDifBadArg;
171  }
172 
173  bitfield_bit32_index_t index;
174  if (!pattgen_get_irq_bit_index(irq, &index)) {
175  return kDifBadArg;
176  }
177 
178  uint32_t intr_test_reg = bitfield_bit32_write(0, index, val);
179  mmio_region_write32(pattgen->base_addr,
180  (ptrdiff_t)PATTGEN_INTR_TEST_REG_OFFSET, intr_test_reg);
181 
182  return kDifOk;
183 }
184 
185 OT_WARN_UNUSED_RESULT
186 dif_result_t dif_pattgen_irq_get_enabled(const dif_pattgen_t *pattgen,
187  dif_pattgen_irq_t irq,
188  dif_toggle_t *state) {
189  if (pattgen == NULL || state == NULL) {
190  return kDifBadArg;
191  }
192 
193  bitfield_bit32_index_t index;
194  if (!pattgen_get_irq_bit_index(irq, &index)) {
195  return kDifBadArg;
196  }
197 
198  uint32_t intr_enable_reg = mmio_region_read32(
199  pattgen->base_addr, (ptrdiff_t)PATTGEN_INTR_ENABLE_REG_OFFSET);
200 
201  bool is_enabled = bitfield_bit32_read(intr_enable_reg, index);
202  *state = is_enabled ? kDifToggleEnabled : kDifToggleDisabled;
203 
204  return kDifOk;
205 }
206 
207 OT_WARN_UNUSED_RESULT
208 dif_result_t dif_pattgen_irq_set_enabled(const dif_pattgen_t *pattgen,
209  dif_pattgen_irq_t irq,
210  dif_toggle_t state) {
211  if (pattgen == NULL) {
212  return kDifBadArg;
213  }
214 
215  bitfield_bit32_index_t index;
216  if (!pattgen_get_irq_bit_index(irq, &index)) {
217  return kDifBadArg;
218  }
219 
220  uint32_t intr_enable_reg = mmio_region_read32(
221  pattgen->base_addr, (ptrdiff_t)PATTGEN_INTR_ENABLE_REG_OFFSET);
222 
223  bool enable_bit = (state == kDifToggleEnabled) ? true : false;
224  intr_enable_reg = bitfield_bit32_write(intr_enable_reg, index, enable_bit);
225  mmio_region_write32(pattgen->base_addr,
226  (ptrdiff_t)PATTGEN_INTR_ENABLE_REG_OFFSET,
227  intr_enable_reg);
228 
229  return kDifOk;
230 }
231 
232 OT_WARN_UNUSED_RESULT
233 dif_result_t dif_pattgen_irq_disable_all(
234  const dif_pattgen_t *pattgen, dif_pattgen_irq_enable_snapshot_t *snapshot) {
235  if (pattgen == NULL) {
236  return kDifBadArg;
237  }
238 
239  // Pass the current interrupt state to the caller, if requested.
240  if (snapshot != NULL) {
241  *snapshot = mmio_region_read32(pattgen->base_addr,
242  (ptrdiff_t)PATTGEN_INTR_ENABLE_REG_OFFSET);
243  }
244 
245  // Disable all interrupts.
246  mmio_region_write32(pattgen->base_addr,
247  (ptrdiff_t)PATTGEN_INTR_ENABLE_REG_OFFSET, 0u);
248 
249  return kDifOk;
250 }
251 
252 OT_WARN_UNUSED_RESULT
253 dif_result_t dif_pattgen_irq_restore_all(
254  const dif_pattgen_t *pattgen,
255  const dif_pattgen_irq_enable_snapshot_t *snapshot) {
256  if (pattgen == NULL || snapshot == NULL) {
257  return kDifBadArg;
258  }
259 
260  mmio_region_write32(pattgen->base_addr,
261  (ptrdiff_t)PATTGEN_INTR_ENABLE_REG_OFFSET, *snapshot);
262 
263  return kDifOk;
264 }
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