Software APIs
dif_pattgen_autogen.c
1 // Copyright lowRISC contributors (OpenTitan project).
2 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3 // SPDX-License-Identifier: Apache-2.0
4 
5 // THIS FILE HAS BEEN GENERATED, DO NOT EDIT MANUALLY. COMMAND:
6 // util/make_new_dif.py --mode=regen --only=autogen
7 
8 #include "sw/device/lib/dif/autogen/dif_pattgen_autogen.h"
9 
10 #include <stdint.h>
11 
12 #include "sw/device/lib/dif/dif_base.h"
13 
14 #include "pattgen_regs.h" // Generated.
15 
16 OT_WARN_UNUSED_RESULT
17 dif_result_t dif_pattgen_init(mmio_region_t base_addr, dif_pattgen_t *pattgen) {
18  if (pattgen == NULL) {
19  return kDifBadArg;
20  }
21 
22  pattgen->base_addr = base_addr;
23 
24  return kDifOk;
25 }
26 
27 dif_result_t dif_pattgen_alert_force(const dif_pattgen_t *pattgen,
28  dif_pattgen_alert_t alert) {
29  if (pattgen == NULL) {
30  return kDifBadArg;
31  }
32 
33  bitfield_bit32_index_t alert_idx;
34  switch (alert) {
35  case kDifPattgenAlertFatalFault:
36  alert_idx = PATTGEN_ALERT_TEST_FATAL_FAULT_BIT;
37  break;
38  default:
39  return kDifBadArg;
40  }
41 
42  uint32_t alert_test_reg = bitfield_bit32_write(0, alert_idx, true);
43  mmio_region_write32(pattgen->base_addr,
44  (ptrdiff_t)PATTGEN_ALERT_TEST_REG_OFFSET, alert_test_reg);
45 
46  return kDifOk;
47 }
48 
49 /**
50  * Get the corresponding interrupt register bit offset of the IRQ.
51  */
52 static bool pattgen_get_irq_bit_index(dif_pattgen_irq_t irq,
53  bitfield_bit32_index_t *index_out) {
54  switch (irq) {
55  case kDifPattgenIrqDoneCh0:
56  *index_out = PATTGEN_INTR_COMMON_DONE_CH0_BIT;
57  break;
58  case kDifPattgenIrqDoneCh1:
59  *index_out = PATTGEN_INTR_COMMON_DONE_CH1_BIT;
60  break;
61  default:
62  return false;
63  }
64 
65  return true;
66 }
67 
68 static dif_irq_type_t irq_types[] = {
69  kDifIrqTypeEvent,
70  kDifIrqTypeEvent,
71 };
72 
73 OT_WARN_UNUSED_RESULT
74 dif_result_t dif_pattgen_irq_get_type(const dif_pattgen_t *pattgen,
75  dif_pattgen_irq_t irq,
76  dif_irq_type_t *type) {
77  if (pattgen == NULL || type == NULL || irq < 0 ||
78  irq > kDifPattgenIrqDoneCh1) {
79  return kDifBadArg;
80  }
81 
82  *type = irq_types[irq];
83 
84  return kDifOk;
85 }
86 
87 OT_WARN_UNUSED_RESULT
88 dif_result_t dif_pattgen_irq_get_state(
89  const dif_pattgen_t *pattgen, dif_pattgen_irq_state_snapshot_t *snapshot) {
90  if (pattgen == NULL || snapshot == NULL) {
91  return kDifBadArg;
92  }
93 
94  *snapshot = mmio_region_read32(pattgen->base_addr,
95  (ptrdiff_t)PATTGEN_INTR_STATE_REG_OFFSET);
96 
97  return kDifOk;
98 }
99 
100 OT_WARN_UNUSED_RESULT
101 dif_result_t dif_pattgen_irq_acknowledge_state(
102  const dif_pattgen_t *pattgen, dif_pattgen_irq_state_snapshot_t snapshot) {
103  if (pattgen == NULL) {
104  return kDifBadArg;
105  }
106 
107  mmio_region_write32(pattgen->base_addr,
108  (ptrdiff_t)PATTGEN_INTR_STATE_REG_OFFSET, snapshot);
109 
110  return kDifOk;
111 }
112 
113 OT_WARN_UNUSED_RESULT
114 dif_result_t dif_pattgen_irq_is_pending(const dif_pattgen_t *pattgen,
115  dif_pattgen_irq_t irq,
116  bool *is_pending) {
117  if (pattgen == NULL || is_pending == NULL) {
118  return kDifBadArg;
119  }
120 
121  bitfield_bit32_index_t index;
122  if (!pattgen_get_irq_bit_index(irq, &index)) {
123  return kDifBadArg;
124  }
125 
126  uint32_t intr_state_reg = mmio_region_read32(
127  pattgen->base_addr, (ptrdiff_t)PATTGEN_INTR_STATE_REG_OFFSET);
128 
129  *is_pending = bitfield_bit32_read(intr_state_reg, index);
130 
131  return kDifOk;
132 }
133 
134 OT_WARN_UNUSED_RESULT
135 dif_result_t dif_pattgen_irq_acknowledge_all(const dif_pattgen_t *pattgen) {
136  if (pattgen == NULL) {
137  return kDifBadArg;
138  }
139 
140  // Writing to the register clears the corresponding bits (Write-one clear).
141  mmio_region_write32(pattgen->base_addr,
142  (ptrdiff_t)PATTGEN_INTR_STATE_REG_OFFSET, UINT32_MAX);
143 
144  return kDifOk;
145 }
146 
147 OT_WARN_UNUSED_RESULT
148 dif_result_t dif_pattgen_irq_acknowledge(const dif_pattgen_t *pattgen,
149  dif_pattgen_irq_t irq) {
150  if (pattgen == NULL) {
151  return kDifBadArg;
152  }
153 
154  bitfield_bit32_index_t index;
155  if (!pattgen_get_irq_bit_index(irq, &index)) {
156  return kDifBadArg;
157  }
158 
159  // Writing to the register clears the corresponding bits (Write-one clear).
160  uint32_t intr_state_reg = bitfield_bit32_write(0, index, true);
161  mmio_region_write32(pattgen->base_addr,
162  (ptrdiff_t)PATTGEN_INTR_STATE_REG_OFFSET, intr_state_reg);
163 
164  return kDifOk;
165 }
166 
167 OT_WARN_UNUSED_RESULT
168 dif_result_t dif_pattgen_irq_force(const dif_pattgen_t *pattgen,
169  dif_pattgen_irq_t irq, const bool val) {
170  if (pattgen == NULL) {
171  return kDifBadArg;
172  }
173 
174  bitfield_bit32_index_t index;
175  if (!pattgen_get_irq_bit_index(irq, &index)) {
176  return kDifBadArg;
177  }
178 
179  uint32_t intr_test_reg = bitfield_bit32_write(0, index, val);
180  mmio_region_write32(pattgen->base_addr,
181  (ptrdiff_t)PATTGEN_INTR_TEST_REG_OFFSET, intr_test_reg);
182 
183  return kDifOk;
184 }
185 
186 OT_WARN_UNUSED_RESULT
187 dif_result_t dif_pattgen_irq_get_enabled(const dif_pattgen_t *pattgen,
188  dif_pattgen_irq_t irq,
189  dif_toggle_t *state) {
190  if (pattgen == NULL || state == NULL) {
191  return kDifBadArg;
192  }
193 
194  bitfield_bit32_index_t index;
195  if (!pattgen_get_irq_bit_index(irq, &index)) {
196  return kDifBadArg;
197  }
198 
199  uint32_t intr_enable_reg = mmio_region_read32(
200  pattgen->base_addr, (ptrdiff_t)PATTGEN_INTR_ENABLE_REG_OFFSET);
201 
202  bool is_enabled = bitfield_bit32_read(intr_enable_reg, index);
203  *state = is_enabled ? kDifToggleEnabled : kDifToggleDisabled;
204 
205  return kDifOk;
206 }
207 
208 OT_WARN_UNUSED_RESULT
209 dif_result_t dif_pattgen_irq_set_enabled(const dif_pattgen_t *pattgen,
210  dif_pattgen_irq_t irq,
211  dif_toggle_t state) {
212  if (pattgen == NULL) {
213  return kDifBadArg;
214  }
215 
216  bitfield_bit32_index_t index;
217  if (!pattgen_get_irq_bit_index(irq, &index)) {
218  return kDifBadArg;
219  }
220 
221  uint32_t intr_enable_reg = mmio_region_read32(
222  pattgen->base_addr, (ptrdiff_t)PATTGEN_INTR_ENABLE_REG_OFFSET);
223 
224  bool enable_bit = (state == kDifToggleEnabled) ? true : false;
225  intr_enable_reg = bitfield_bit32_write(intr_enable_reg, index, enable_bit);
226  mmio_region_write32(pattgen->base_addr,
227  (ptrdiff_t)PATTGEN_INTR_ENABLE_REG_OFFSET,
228  intr_enable_reg);
229 
230  return kDifOk;
231 }
232 
233 OT_WARN_UNUSED_RESULT
234 dif_result_t dif_pattgen_irq_disable_all(
235  const dif_pattgen_t *pattgen, dif_pattgen_irq_enable_snapshot_t *snapshot) {
236  if (pattgen == NULL) {
237  return kDifBadArg;
238  }
239 
240  // Pass the current interrupt state to the caller, if requested.
241  if (snapshot != NULL) {
242  *snapshot = mmio_region_read32(pattgen->base_addr,
243  (ptrdiff_t)PATTGEN_INTR_ENABLE_REG_OFFSET);
244  }
245 
246  // Disable all interrupts.
247  mmio_region_write32(pattgen->base_addr,
248  (ptrdiff_t)PATTGEN_INTR_ENABLE_REG_OFFSET, 0u);
249 
250  return kDifOk;
251 }
252 
253 OT_WARN_UNUSED_RESULT
254 dif_result_t dif_pattgen_irq_restore_all(
255  const dif_pattgen_t *pattgen,
256  const dif_pattgen_irq_enable_snapshot_t *snapshot) {
257  if (pattgen == NULL || snapshot == NULL) {
258  return kDifBadArg;
259  }
260 
261  mmio_region_write32(pattgen->base_addr,
262  (ptrdiff_t)PATTGEN_INTR_ENABLE_REG_OFFSET, *snapshot);
263 
264  return kDifOk;
265 }
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