10 #include "pattgen_regs.h"
24 ptrdiff_t clock_divisor_reg_offset;
25 ptrdiff_t seed_lower_reg_offset;
26 ptrdiff_t seed_upper_reg_offset;
30 #define DIF_PATTGEN_CHANNEL_CONFIG_CASE_(channel_) \
31 case kDifPattgenChannel##channel_: \
32 enable_bit_idx = PATTGEN_CTRL_ENABLE_CH##channel_##_BIT; \
33 polarity_bit_idx = PATTGEN_CTRL_POLARITY_CH##channel_##_BIT; \
34 clock_divisor_reg_offset = PATTGEN_PREDIV_CH##channel_##_REG_OFFSET; \
35 seed_lower_reg_offset = PATTGEN_DATA_CH##channel_##_0_REG_OFFSET; \
36 seed_upper_reg_offset = PATTGEN_DATA_CH##channel_##_1_REG_OFFSET; \
37 seed_pattern_length_field = PATTGEN_SIZE_LEN_CH##channel_##_FIELD; \
38 num_pattern_repetitions_field = PATTGEN_SIZE_REPS_CH##channel_##_FIELD; \
46 #undef DIF_PATTGEN_CHANNEL_CONFIG_CASE_
49 mmio_region_read32(pattgen->
base_addr, PATTGEN_CTRL_REG_OFFSET);
58 mmio_region_write32(pattgen->
base_addr, PATTGEN_CTRL_REG_OFFSET, ctrl_reg);
61 mmio_region_write32(pattgen->
base_addr, clock_divisor_reg_offset,
65 mmio_region_write32(pattgen->
base_addr, seed_lower_reg_offset,
68 mmio_region_write32(pattgen->
base_addr, seed_upper_reg_offset,
74 mmio_region_read32(pattgen->
base_addr, PATTGEN_SIZE_REG_OFFSET);
79 mmio_region_write32(pattgen->
base_addr, PATTGEN_SIZE_REG_OFFSET, size_reg);
93 #define DIF_PATTGEN_CHANNEL_SET_ENABLED_CASE_(channel_) \
94 case kDifPattgenChannel##channel_: \
95 enable_bit_idx = PATTGEN_CTRL_ENABLE_CH##channel_##_BIT; \
103 #undef DIF_PATTGEN_CHANNEL_SET_ENABLED_CASE_
106 mmio_region_read32(pattgen->
base_addr, PATTGEN_CTRL_REG_OFFSET);
109 mmio_region_write32(pattgen->
base_addr, PATTGEN_CTRL_REG_OFFSET, ctrl_reg);
117 if (pattgen == NULL || is_enabled == NULL) {
123 #define DIF_PATTGEN_CHANNEL_SET_ENABLED_CASE_(channel_) \
124 case kDifPattgenChannel##channel_: \
125 enable_bit_idx = PATTGEN_CTRL_ENABLE_CH##channel_##_BIT; \
133 #undef DIF_PATTGEN_CHANNEL_SET_ENABLED_CASE_
136 mmio_region_read32(pattgen->
base_addr, PATTGEN_CTRL_REG_OFFSET);