Software APIs
dif_otp_ctrl_autogen.c
1 // Copyright lowRISC contributors (OpenTitan project).
2 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3 // SPDX-License-Identifier: Apache-2.0
4 
5 // THIS FILE HAS BEEN GENERATED, DO NOT EDIT MANUALLY. COMMAND:
6 // util/make_new_dif.py --mode=regen --only=autogen
7 
8 #include "sw/device/lib/dif/autogen/dif_otp_ctrl_autogen.h"
9 
10 #include <stdint.h>
11 
12 #include "sw/device/lib/dif/dif_base.h"
13 
14 #include "otp_ctrl_regs.h" // Generated.
15 
16 OT_WARN_UNUSED_RESULT
17 dif_result_t dif_otp_ctrl_init(mmio_region_t base_addr,
18  dif_otp_ctrl_t *otp_ctrl) {
19  if (otp_ctrl == NULL) {
20  return kDifBadArg;
21  }
22 
23  otp_ctrl->base_addr = base_addr;
24 
25  return kDifOk;
26 }
27 
28 dif_result_t dif_otp_ctrl_alert_force(const dif_otp_ctrl_t *otp_ctrl,
29  dif_otp_ctrl_alert_t alert) {
30  if (otp_ctrl == NULL) {
31  return kDifBadArg;
32  }
33 
34  bitfield_bit32_index_t alert_idx;
35  switch (alert) {
36  case kDifOtpCtrlAlertFatalMacroError:
37  alert_idx = OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_BIT;
38  break;
39  case kDifOtpCtrlAlertFatalCheckError:
40  alert_idx = OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_BIT;
41  break;
42  case kDifOtpCtrlAlertFatalBusIntegError:
43  alert_idx = OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_BIT;
44  break;
45  case kDifOtpCtrlAlertFatalPrimOtpAlert:
46  alert_idx = OTP_CTRL_ALERT_TEST_FATAL_PRIM_OTP_ALERT_BIT;
47  break;
48  case kDifOtpCtrlAlertRecovPrimOtpAlert:
49  alert_idx = OTP_CTRL_ALERT_TEST_RECOV_PRIM_OTP_ALERT_BIT;
50  break;
51  default:
52  return kDifBadArg;
53  }
54 
55  uint32_t alert_test_reg = bitfield_bit32_write(0, alert_idx, true);
56  mmio_region_write32(otp_ctrl->base_addr,
57  (ptrdiff_t)OTP_CTRL_ALERT_TEST_REG_OFFSET,
58  alert_test_reg);
59 
60  return kDifOk;
61 }
62 
63 /**
64  * Get the corresponding interrupt register bit offset of the IRQ.
65  */
66 static bool otp_ctrl_get_irq_bit_index(dif_otp_ctrl_irq_t irq,
67  bitfield_bit32_index_t *index_out) {
68  switch (irq) {
69  case kDifOtpCtrlIrqOtpOperationDone:
70  *index_out = OTP_CTRL_INTR_COMMON_OTP_OPERATION_DONE_BIT;
71  break;
72  case kDifOtpCtrlIrqOtpError:
73  *index_out = OTP_CTRL_INTR_COMMON_OTP_ERROR_BIT;
74  break;
75  default:
76  return false;
77  }
78 
79  return true;
80 }
81 
82 static dif_irq_type_t irq_types[] = {
83  kDifIrqTypeEvent,
84  kDifIrqTypeEvent,
85 };
86 
87 OT_WARN_UNUSED_RESULT
88 dif_result_t dif_otp_ctrl_irq_get_type(const dif_otp_ctrl_t *otp_ctrl,
89  dif_otp_ctrl_irq_t irq,
90  dif_irq_type_t *type) {
91  if (otp_ctrl == NULL || type == NULL || irq < 0 ||
92  irq > kDifOtpCtrlIrqOtpError) {
93  return kDifBadArg;
94  }
95 
96  *type = irq_types[irq];
97 
98  return kDifOk;
99 }
100 
101 OT_WARN_UNUSED_RESULT
102 dif_result_t dif_otp_ctrl_irq_get_state(
103  const dif_otp_ctrl_t *otp_ctrl,
104  dif_otp_ctrl_irq_state_snapshot_t *snapshot) {
105  if (otp_ctrl == NULL || snapshot == NULL) {
106  return kDifBadArg;
107  }
108 
109  *snapshot = mmio_region_read32(otp_ctrl->base_addr,
110  (ptrdiff_t)OTP_CTRL_INTR_STATE_REG_OFFSET);
111 
112  return kDifOk;
113 }
114 
115 OT_WARN_UNUSED_RESULT
116 dif_result_t dif_otp_ctrl_irq_acknowledge_state(
117  const dif_otp_ctrl_t *otp_ctrl,
118  dif_otp_ctrl_irq_state_snapshot_t snapshot) {
119  if (otp_ctrl == NULL) {
120  return kDifBadArg;
121  }
122 
123  mmio_region_write32(otp_ctrl->base_addr,
124  (ptrdiff_t)OTP_CTRL_INTR_STATE_REG_OFFSET, snapshot);
125 
126  return kDifOk;
127 }
128 
129 OT_WARN_UNUSED_RESULT
130 dif_result_t dif_otp_ctrl_irq_is_pending(const dif_otp_ctrl_t *otp_ctrl,
131  dif_otp_ctrl_irq_t irq,
132  bool *is_pending) {
133  if (otp_ctrl == NULL || is_pending == NULL) {
134  return kDifBadArg;
135  }
136 
137  bitfield_bit32_index_t index;
138  if (!otp_ctrl_get_irq_bit_index(irq, &index)) {
139  return kDifBadArg;
140  }
141 
142  uint32_t intr_state_reg = mmio_region_read32(
143  otp_ctrl->base_addr, (ptrdiff_t)OTP_CTRL_INTR_STATE_REG_OFFSET);
144 
145  *is_pending = bitfield_bit32_read(intr_state_reg, index);
146 
147  return kDifOk;
148 }
149 
150 OT_WARN_UNUSED_RESULT
151 dif_result_t dif_otp_ctrl_irq_acknowledge_all(const dif_otp_ctrl_t *otp_ctrl) {
152  if (otp_ctrl == NULL) {
153  return kDifBadArg;
154  }
155 
156  // Writing to the register clears the corresponding bits (Write-one clear).
157  mmio_region_write32(otp_ctrl->base_addr,
158  (ptrdiff_t)OTP_CTRL_INTR_STATE_REG_OFFSET, UINT32_MAX);
159 
160  return kDifOk;
161 }
162 
163 OT_WARN_UNUSED_RESULT
164 dif_result_t dif_otp_ctrl_irq_acknowledge(const dif_otp_ctrl_t *otp_ctrl,
165  dif_otp_ctrl_irq_t irq) {
166  if (otp_ctrl == NULL) {
167  return kDifBadArg;
168  }
169 
170  bitfield_bit32_index_t index;
171  if (!otp_ctrl_get_irq_bit_index(irq, &index)) {
172  return kDifBadArg;
173  }
174 
175  // Writing to the register clears the corresponding bits (Write-one clear).
176  uint32_t intr_state_reg = bitfield_bit32_write(0, index, true);
177  mmio_region_write32(otp_ctrl->base_addr,
178  (ptrdiff_t)OTP_CTRL_INTR_STATE_REG_OFFSET,
179  intr_state_reg);
180 
181  return kDifOk;
182 }
183 
184 OT_WARN_UNUSED_RESULT
185 dif_result_t dif_otp_ctrl_irq_force(const dif_otp_ctrl_t *otp_ctrl,
186  dif_otp_ctrl_irq_t irq, const bool val) {
187  if (otp_ctrl == NULL) {
188  return kDifBadArg;
189  }
190 
191  bitfield_bit32_index_t index;
192  if (!otp_ctrl_get_irq_bit_index(irq, &index)) {
193  return kDifBadArg;
194  }
195 
196  uint32_t intr_test_reg = bitfield_bit32_write(0, index, val);
197  mmio_region_write32(otp_ctrl->base_addr,
198  (ptrdiff_t)OTP_CTRL_INTR_TEST_REG_OFFSET, intr_test_reg);
199 
200  return kDifOk;
201 }
202 
203 OT_WARN_UNUSED_RESULT
204 dif_result_t dif_otp_ctrl_irq_get_enabled(const dif_otp_ctrl_t *otp_ctrl,
205  dif_otp_ctrl_irq_t irq,
206  dif_toggle_t *state) {
207  if (otp_ctrl == NULL || state == NULL) {
208  return kDifBadArg;
209  }
210 
211  bitfield_bit32_index_t index;
212  if (!otp_ctrl_get_irq_bit_index(irq, &index)) {
213  return kDifBadArg;
214  }
215 
216  uint32_t intr_enable_reg = mmio_region_read32(
217  otp_ctrl->base_addr, (ptrdiff_t)OTP_CTRL_INTR_ENABLE_REG_OFFSET);
218 
219  bool is_enabled = bitfield_bit32_read(intr_enable_reg, index);
220  *state = is_enabled ? kDifToggleEnabled : kDifToggleDisabled;
221 
222  return kDifOk;
223 }
224 
225 OT_WARN_UNUSED_RESULT
226 dif_result_t dif_otp_ctrl_irq_set_enabled(const dif_otp_ctrl_t *otp_ctrl,
227  dif_otp_ctrl_irq_t irq,
228  dif_toggle_t state) {
229  if (otp_ctrl == NULL) {
230  return kDifBadArg;
231  }
232 
233  bitfield_bit32_index_t index;
234  if (!otp_ctrl_get_irq_bit_index(irq, &index)) {
235  return kDifBadArg;
236  }
237 
238  uint32_t intr_enable_reg = mmio_region_read32(
239  otp_ctrl->base_addr, (ptrdiff_t)OTP_CTRL_INTR_ENABLE_REG_OFFSET);
240 
241  bool enable_bit = (state == kDifToggleEnabled) ? true : false;
242  intr_enable_reg = bitfield_bit32_write(intr_enable_reg, index, enable_bit);
243  mmio_region_write32(otp_ctrl->base_addr,
244  (ptrdiff_t)OTP_CTRL_INTR_ENABLE_REG_OFFSET,
245  intr_enable_reg);
246 
247  return kDifOk;
248 }
249 
250 OT_WARN_UNUSED_RESULT
251 dif_result_t dif_otp_ctrl_irq_disable_all(
252  const dif_otp_ctrl_t *otp_ctrl,
253  dif_otp_ctrl_irq_enable_snapshot_t *snapshot) {
254  if (otp_ctrl == NULL) {
255  return kDifBadArg;
256  }
257 
258  // Pass the current interrupt state to the caller, if requested.
259  if (snapshot != NULL) {
260  *snapshot = mmio_region_read32(otp_ctrl->base_addr,
261  (ptrdiff_t)OTP_CTRL_INTR_ENABLE_REG_OFFSET);
262  }
263 
264  // Disable all interrupts.
265  mmio_region_write32(otp_ctrl->base_addr,
266  (ptrdiff_t)OTP_CTRL_INTR_ENABLE_REG_OFFSET, 0u);
267 
268  return kDifOk;
269 }
270 
271 OT_WARN_UNUSED_RESULT
272 dif_result_t dif_otp_ctrl_irq_restore_all(
273  const dif_otp_ctrl_t *otp_ctrl,
274  const dif_otp_ctrl_irq_enable_snapshot_t *snapshot) {
275  if (otp_ctrl == NULL || snapshot == NULL) {
276  return kDifBadArg;
277  }
278 
279  mmio_region_write32(otp_ctrl->base_addr,
280  (ptrdiff_t)OTP_CTRL_INTR_ENABLE_REG_OFFSET, *snapshot);
281 
282  return kDifOk;
283 }
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