Software APIs
dif_otp_ctrl_autogen.c
1 // Copyright lowRISC contributors (OpenTitan project).
2 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3 // SPDX-License-Identifier: Apache-2.0
4 
5 // THIS FILE HAS BEEN GENERATED, DO NOT EDIT MANUALLY. COMMAND:
6 // util/make_new_dif.py --mode=regen --only=autogen
7 
8 #include "sw/device/lib/dif/autogen/dif_otp_ctrl_autogen.h"
9 
10 #include <stdint.h>
11 
12 #include "sw/device/lib/dif/dif_base.h"
13 
14 #include "otp_ctrl_regs.h" // Generated.
15 
16 OT_WARN_UNUSED_RESULT
17 dif_result_t dif_otp_ctrl_init(mmio_region_t base_addr,
18  dif_otp_ctrl_t *otp_ctrl) {
19  if (otp_ctrl == NULL) {
20  return kDifBadArg;
21  }
22 
23  otp_ctrl->base_addr = base_addr;
24 
25  return kDifOk;
26 }
27 
28 dif_result_t dif_otp_ctrl_alert_force(const dif_otp_ctrl_t *otp_ctrl,
29  dif_otp_ctrl_alert_t alert) {
30  if (otp_ctrl == NULL) {
31  return kDifBadArg;
32  }
33 
34  bitfield_bit32_index_t alert_idx;
35  switch (alert) {
36  case kDifOtpCtrlAlertFatalMacroError:
37  alert_idx = OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_BIT;
38  break;
39  case kDifOtpCtrlAlertFatalCheckError:
40  alert_idx = OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_BIT;
41  break;
42  case kDifOtpCtrlAlertFatalBusIntegError:
43  alert_idx = OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_BIT;
44  break;
45  case kDifOtpCtrlAlertFatalPrimOtpAlert:
46  alert_idx = OTP_CTRL_ALERT_TEST_FATAL_PRIM_OTP_ALERT_BIT;
47  break;
48  case kDifOtpCtrlAlertRecovPrimOtpAlert:
49  alert_idx = OTP_CTRL_ALERT_TEST_RECOV_PRIM_OTP_ALERT_BIT;
50  break;
51  default:
52  return kDifBadArg;
53  }
54 
55  uint32_t alert_test_reg = bitfield_bit32_write(0, alert_idx, true);
56  mmio_region_write32(otp_ctrl->base_addr,
57  (ptrdiff_t)OTP_CTRL_ALERT_TEST_REG_OFFSET,
58  alert_test_reg);
59 
60  return kDifOk;
61 }
62 
63 /**
64  * Get the corresponding interrupt register bit offset of the IRQ.
65  */
66 static bool otp_ctrl_get_irq_bit_index(dif_otp_ctrl_irq_t irq,
67  bitfield_bit32_index_t *index_out) {
68  switch (irq) {
69  case kDifOtpCtrlIrqOtpOperationDone:
70  *index_out = OTP_CTRL_INTR_COMMON_OTP_OPERATION_DONE_BIT;
71  break;
72  case kDifOtpCtrlIrqOtpError:
73  *index_out = OTP_CTRL_INTR_COMMON_OTP_ERROR_BIT;
74  break;
75  default:
76  return false;
77  }
78 
79  return true;
80 }
81 
82 static dif_irq_type_t irq_types[] = {
83  kDifIrqTypeEvent,
84  kDifIrqTypeEvent,
85 };
86 
87 OT_WARN_UNUSED_RESULT
88 dif_result_t dif_otp_ctrl_irq_get_type(const dif_otp_ctrl_t *otp_ctrl,
89  dif_otp_ctrl_irq_t irq,
90  dif_irq_type_t *type) {
91  if (otp_ctrl == NULL || type == NULL || irq == kDifOtpCtrlIrqOtpError + 1) {
92  return kDifBadArg;
93  }
94 
95  *type = irq_types[irq];
96 
97  return kDifOk;
98 }
99 
100 OT_WARN_UNUSED_RESULT
101 dif_result_t dif_otp_ctrl_irq_get_state(
102  const dif_otp_ctrl_t *otp_ctrl,
103  dif_otp_ctrl_irq_state_snapshot_t *snapshot) {
104  if (otp_ctrl == NULL || snapshot == NULL) {
105  return kDifBadArg;
106  }
107 
108  *snapshot = mmio_region_read32(otp_ctrl->base_addr,
109  (ptrdiff_t)OTP_CTRL_INTR_STATE_REG_OFFSET);
110 
111  return kDifOk;
112 }
113 
114 OT_WARN_UNUSED_RESULT
115 dif_result_t dif_otp_ctrl_irq_acknowledge_state(
116  const dif_otp_ctrl_t *otp_ctrl,
117  dif_otp_ctrl_irq_state_snapshot_t snapshot) {
118  if (otp_ctrl == NULL) {
119  return kDifBadArg;
120  }
121 
122  mmio_region_write32(otp_ctrl->base_addr,
123  (ptrdiff_t)OTP_CTRL_INTR_STATE_REG_OFFSET, snapshot);
124 
125  return kDifOk;
126 }
127 
128 OT_WARN_UNUSED_RESULT
129 dif_result_t dif_otp_ctrl_irq_is_pending(const dif_otp_ctrl_t *otp_ctrl,
130  dif_otp_ctrl_irq_t irq,
131  bool *is_pending) {
132  if (otp_ctrl == NULL || is_pending == NULL) {
133  return kDifBadArg;
134  }
135 
136  bitfield_bit32_index_t index;
137  if (!otp_ctrl_get_irq_bit_index(irq, &index)) {
138  return kDifBadArg;
139  }
140 
141  uint32_t intr_state_reg = mmio_region_read32(
142  otp_ctrl->base_addr, (ptrdiff_t)OTP_CTRL_INTR_STATE_REG_OFFSET);
143 
144  *is_pending = bitfield_bit32_read(intr_state_reg, index);
145 
146  return kDifOk;
147 }
148 
149 OT_WARN_UNUSED_RESULT
150 dif_result_t dif_otp_ctrl_irq_acknowledge_all(const dif_otp_ctrl_t *otp_ctrl) {
151  if (otp_ctrl == NULL) {
152  return kDifBadArg;
153  }
154 
155  // Writing to the register clears the corresponding bits (Write-one clear).
156  mmio_region_write32(otp_ctrl->base_addr,
157  (ptrdiff_t)OTP_CTRL_INTR_STATE_REG_OFFSET, UINT32_MAX);
158 
159  return kDifOk;
160 }
161 
162 OT_WARN_UNUSED_RESULT
163 dif_result_t dif_otp_ctrl_irq_acknowledge(const dif_otp_ctrl_t *otp_ctrl,
164  dif_otp_ctrl_irq_t irq) {
165  if (otp_ctrl == NULL) {
166  return kDifBadArg;
167  }
168 
169  bitfield_bit32_index_t index;
170  if (!otp_ctrl_get_irq_bit_index(irq, &index)) {
171  return kDifBadArg;
172  }
173 
174  // Writing to the register clears the corresponding bits (Write-one clear).
175  uint32_t intr_state_reg = bitfield_bit32_write(0, index, true);
176  mmio_region_write32(otp_ctrl->base_addr,
177  (ptrdiff_t)OTP_CTRL_INTR_STATE_REG_OFFSET,
178  intr_state_reg);
179 
180  return kDifOk;
181 }
182 
183 OT_WARN_UNUSED_RESULT
184 dif_result_t dif_otp_ctrl_irq_force(const dif_otp_ctrl_t *otp_ctrl,
185  dif_otp_ctrl_irq_t irq, const bool val) {
186  if (otp_ctrl == NULL) {
187  return kDifBadArg;
188  }
189 
190  bitfield_bit32_index_t index;
191  if (!otp_ctrl_get_irq_bit_index(irq, &index)) {
192  return kDifBadArg;
193  }
194 
195  uint32_t intr_test_reg = bitfield_bit32_write(0, index, val);
196  mmio_region_write32(otp_ctrl->base_addr,
197  (ptrdiff_t)OTP_CTRL_INTR_TEST_REG_OFFSET, intr_test_reg);
198 
199  return kDifOk;
200 }
201 
202 OT_WARN_UNUSED_RESULT
203 dif_result_t dif_otp_ctrl_irq_get_enabled(const dif_otp_ctrl_t *otp_ctrl,
204  dif_otp_ctrl_irq_t irq,
205  dif_toggle_t *state) {
206  if (otp_ctrl == NULL || state == NULL) {
207  return kDifBadArg;
208  }
209 
210  bitfield_bit32_index_t index;
211  if (!otp_ctrl_get_irq_bit_index(irq, &index)) {
212  return kDifBadArg;
213  }
214 
215  uint32_t intr_enable_reg = mmio_region_read32(
216  otp_ctrl->base_addr, (ptrdiff_t)OTP_CTRL_INTR_ENABLE_REG_OFFSET);
217 
218  bool is_enabled = bitfield_bit32_read(intr_enable_reg, index);
219  *state = is_enabled ? kDifToggleEnabled : kDifToggleDisabled;
220 
221  return kDifOk;
222 }
223 
224 OT_WARN_UNUSED_RESULT
225 dif_result_t dif_otp_ctrl_irq_set_enabled(const dif_otp_ctrl_t *otp_ctrl,
226  dif_otp_ctrl_irq_t irq,
227  dif_toggle_t state) {
228  if (otp_ctrl == NULL) {
229  return kDifBadArg;
230  }
231 
232  bitfield_bit32_index_t index;
233  if (!otp_ctrl_get_irq_bit_index(irq, &index)) {
234  return kDifBadArg;
235  }
236 
237  uint32_t intr_enable_reg = mmio_region_read32(
238  otp_ctrl->base_addr, (ptrdiff_t)OTP_CTRL_INTR_ENABLE_REG_OFFSET);
239 
240  bool enable_bit = (state == kDifToggleEnabled) ? true : false;
241  intr_enable_reg = bitfield_bit32_write(intr_enable_reg, index, enable_bit);
242  mmio_region_write32(otp_ctrl->base_addr,
243  (ptrdiff_t)OTP_CTRL_INTR_ENABLE_REG_OFFSET,
244  intr_enable_reg);
245 
246  return kDifOk;
247 }
248 
249 OT_WARN_UNUSED_RESULT
250 dif_result_t dif_otp_ctrl_irq_disable_all(
251  const dif_otp_ctrl_t *otp_ctrl,
252  dif_otp_ctrl_irq_enable_snapshot_t *snapshot) {
253  if (otp_ctrl == NULL) {
254  return kDifBadArg;
255  }
256 
257  // Pass the current interrupt state to the caller, if requested.
258  if (snapshot != NULL) {
259  *snapshot = mmio_region_read32(otp_ctrl->base_addr,
260  (ptrdiff_t)OTP_CTRL_INTR_ENABLE_REG_OFFSET);
261  }
262 
263  // Disable all interrupts.
264  mmio_region_write32(otp_ctrl->base_addr,
265  (ptrdiff_t)OTP_CTRL_INTR_ENABLE_REG_OFFSET, 0u);
266 
267  return kDifOk;
268 }
269 
270 OT_WARN_UNUSED_RESULT
271 dif_result_t dif_otp_ctrl_irq_restore_all(
272  const dif_otp_ctrl_t *otp_ctrl,
273  const dif_otp_ctrl_irq_enable_snapshot_t *snapshot) {
274  if (otp_ctrl == NULL || snapshot == NULL) {
275  return kDifBadArg;
276  }
277 
278  mmio_region_write32(otp_ctrl->base_addr,
279  (ptrdiff_t)OTP_CTRL_INTR_ENABLE_REG_OFFSET, *snapshot);
280 
281  return kDifOk;
282 }
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