Software APIs
dif_otbn_autogen.c
1 // Copyright lowRISC contributors (OpenTitan project).
2 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3 // SPDX-License-Identifier: Apache-2.0
4 
5 // THIS FILE HAS BEEN GENERATED, DO NOT EDIT MANUALLY. COMMAND:
6 // util/make_new_dif.py --mode=regen --only=autogen
7 
9 
10 #include <stdint.h>
11 
13 
14 #include "otbn_regs.h" // Generated.
15 
18  if (otbn == NULL) {
19  return kDifBadArg;
20  }
21 
22  otbn->base_addr = base_addr;
23 
24  return kDifOk;
25 }
26 
28  dif_otbn_alert_t alert) {
29  if (otbn == NULL) {
30  return kDifBadArg;
31  }
32 
33  bitfield_bit32_index_t alert_idx;
34  switch (alert) {
35  case kDifOtbnAlertFatal:
36  alert_idx = OTBN_ALERT_TEST_FATAL_BIT;
37  break;
38  case kDifOtbnAlertRecov:
39  alert_idx = OTBN_ALERT_TEST_RECOV_BIT;
40  break;
41  default:
42  return kDifBadArg;
43  }
44 
45  uint32_t alert_test_reg = bitfield_bit32_write(0, alert_idx, true);
46  mmio_region_write32(otbn->base_addr, (ptrdiff_t)OTBN_ALERT_TEST_REG_OFFSET,
47  alert_test_reg);
48 
49  return kDifOk;
50 }
51 
52 /**
53  * Get the corresponding interrupt register bit offset of the IRQ.
54  */
55 static bool otbn_get_irq_bit_index(dif_otbn_irq_t irq,
56  bitfield_bit32_index_t *index_out) {
57  switch (irq) {
58  case kDifOtbnIrqDone:
59  *index_out = OTBN_INTR_COMMON_DONE_BIT;
60  break;
61  default:
62  return false;
63  }
64 
65  return true;
66 }
67 
68 static dif_irq_type_t irq_types[] = {
70 };
71 
74  dif_irq_type_t *type) {
75  if (otbn == NULL || type == NULL || irq == kDifOtbnIrqDone + 1) {
76  return kDifBadArg;
77  }
78 
79  *type = irq_types[irq];
80 
81  return kDifOk;
82 }
83 
87  if (otbn == NULL || snapshot == NULL) {
88  return kDifBadArg;
89  }
90 
91  *snapshot = mmio_region_read32(otbn->base_addr,
92  (ptrdiff_t)OTBN_INTR_STATE_REG_OFFSET);
93 
94  return kDifOk;
95 }
96 
99  const dif_otbn_t *otbn, dif_otbn_irq_state_snapshot_t snapshot) {
100  if (otbn == NULL) {
101  return kDifBadArg;
102  }
103 
104  mmio_region_write32(otbn->base_addr, (ptrdiff_t)OTBN_INTR_STATE_REG_OFFSET,
105  snapshot);
106 
107  return kDifOk;
108 }
109 
112  bool *is_pending) {
113  if (otbn == NULL || is_pending == NULL) {
114  return kDifBadArg;
115  }
116 
118  if (!otbn_get_irq_bit_index(irq, &index)) {
119  return kDifBadArg;
120  }
121 
122  uint32_t intr_state_reg = mmio_region_read32(
123  otbn->base_addr, (ptrdiff_t)OTBN_INTR_STATE_REG_OFFSET);
124 
125  *is_pending = bitfield_bit32_read(intr_state_reg, index);
126 
127  return kDifOk;
128 }
129 
132  if (otbn == NULL) {
133  return kDifBadArg;
134  }
135 
136  // Writing to the register clears the corresponding bits (Write-one clear).
137  mmio_region_write32(otbn->base_addr, (ptrdiff_t)OTBN_INTR_STATE_REG_OFFSET,
138  UINT32_MAX);
139 
140  return kDifOk;
141 }
142 
145  dif_otbn_irq_t irq) {
146  if (otbn == NULL) {
147  return kDifBadArg;
148  }
149 
151  if (!otbn_get_irq_bit_index(irq, &index)) {
152  return kDifBadArg;
153  }
154 
155  // Writing to the register clears the corresponding bits (Write-one clear).
156  uint32_t intr_state_reg = bitfield_bit32_write(0, index, true);
157  mmio_region_write32(otbn->base_addr, (ptrdiff_t)OTBN_INTR_STATE_REG_OFFSET,
158  intr_state_reg);
159 
160  return kDifOk;
161 }
162 
165  const bool val) {
166  if (otbn == NULL) {
167  return kDifBadArg;
168  }
169 
171  if (!otbn_get_irq_bit_index(irq, &index)) {
172  return kDifBadArg;
173  }
174 
175  uint32_t intr_test_reg = bitfield_bit32_write(0, index, val);
176  mmio_region_write32(otbn->base_addr, (ptrdiff_t)OTBN_INTR_TEST_REG_OFFSET,
177  intr_test_reg);
178 
179  return kDifOk;
180 }
181 
184  dif_otbn_irq_t irq, dif_toggle_t *state) {
185  if (otbn == NULL || state == NULL) {
186  return kDifBadArg;
187  }
188 
190  if (!otbn_get_irq_bit_index(irq, &index)) {
191  return kDifBadArg;
192  }
193 
194  uint32_t intr_enable_reg = mmio_region_read32(
195  otbn->base_addr, (ptrdiff_t)OTBN_INTR_ENABLE_REG_OFFSET);
196 
197  bool is_enabled = bitfield_bit32_read(intr_enable_reg, index);
198  *state = is_enabled ? kDifToggleEnabled : kDifToggleDisabled;
199 
200  return kDifOk;
201 }
202 
205  dif_otbn_irq_t irq, dif_toggle_t state) {
206  if (otbn == NULL) {
207  return kDifBadArg;
208  }
209 
211  if (!otbn_get_irq_bit_index(irq, &index)) {
212  return kDifBadArg;
213  }
214 
215  uint32_t intr_enable_reg = mmio_region_read32(
216  otbn->base_addr, (ptrdiff_t)OTBN_INTR_ENABLE_REG_OFFSET);
217 
218  bool enable_bit = (state == kDifToggleEnabled) ? true : false;
219  intr_enable_reg = bitfield_bit32_write(intr_enable_reg, index, enable_bit);
220  mmio_region_write32(otbn->base_addr, (ptrdiff_t)OTBN_INTR_ENABLE_REG_OFFSET,
221  intr_enable_reg);
222 
223  return kDifOk;
224 }
225 
228  const dif_otbn_t *otbn, dif_otbn_irq_enable_snapshot_t *snapshot) {
229  if (otbn == NULL) {
230  return kDifBadArg;
231  }
232 
233  // Pass the current interrupt state to the caller, if requested.
234  if (snapshot != NULL) {
235  *snapshot = mmio_region_read32(otbn->base_addr,
236  (ptrdiff_t)OTBN_INTR_ENABLE_REG_OFFSET);
237  }
238 
239  // Disable all interrupts.
240  mmio_region_write32(otbn->base_addr, (ptrdiff_t)OTBN_INTR_ENABLE_REG_OFFSET,
241  0u);
242 
243  return kDifOk;
244 }
245 
248  const dif_otbn_t *otbn, const dif_otbn_irq_enable_snapshot_t *snapshot) {
249  if (otbn == NULL || snapshot == NULL) {
250  return kDifBadArg;
251  }
252 
253  mmio_region_write32(otbn->base_addr, (ptrdiff_t)OTBN_INTR_ENABLE_REG_OFFSET,
254  *snapshot);
255 
256  return kDifOk;
257 }