Software APIs
dif_kmac_autogen.c
1 // Copyright lowRISC contributors (OpenTitan project).
2 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3 // SPDX-License-Identifier: Apache-2.0
4 
5 // THIS FILE HAS BEEN GENERATED, DO NOT EDIT MANUALLY. COMMAND:
6 // util/make_new_dif.py --mode=regen --only=autogen
7 
8 #include "sw/device/lib/dif/autogen/dif_kmac_autogen.h"
9 
10 #include <stdint.h>
11 
12 #include "sw/device/lib/dif/dif_base.h"
13 
14 #include "kmac_regs.h" // Generated.
15 
16 OT_WARN_UNUSED_RESULT
17 dif_result_t dif_kmac_init(mmio_region_t base_addr, dif_kmac_t *kmac) {
18  if (kmac == NULL) {
19  return kDifBadArg;
20  }
21 
22  kmac->base_addr = base_addr;
23 
24  return kDifOk;
25 }
26 
27 dif_result_t dif_kmac_alert_force(const dif_kmac_t *kmac,
28  dif_kmac_alert_t alert) {
29  if (kmac == NULL) {
30  return kDifBadArg;
31  }
32 
33  bitfield_bit32_index_t alert_idx;
34  switch (alert) {
35  case kDifKmacAlertRecovOperationErr:
36  alert_idx = KMAC_ALERT_TEST_RECOV_OPERATION_ERR_BIT;
37  break;
38  case kDifKmacAlertFatalFaultErr:
39  alert_idx = KMAC_ALERT_TEST_FATAL_FAULT_ERR_BIT;
40  break;
41  default:
42  return kDifBadArg;
43  }
44 
45  uint32_t alert_test_reg = bitfield_bit32_write(0, alert_idx, true);
46  mmio_region_write32(kmac->base_addr, (ptrdiff_t)KMAC_ALERT_TEST_REG_OFFSET,
47  alert_test_reg);
48 
49  return kDifOk;
50 }
51 
52 /**
53  * Get the corresponding interrupt register bit offset of the IRQ.
54  */
55 static bool kmac_get_irq_bit_index(dif_kmac_irq_t irq,
56  bitfield_bit32_index_t *index_out) {
57  switch (irq) {
58  case kDifKmacIrqKmacDone:
59  *index_out = KMAC_INTR_COMMON_KMAC_DONE_BIT;
60  break;
61  case kDifKmacIrqFifoEmpty:
62  *index_out = KMAC_INTR_COMMON_FIFO_EMPTY_BIT;
63  break;
64  case kDifKmacIrqKmacErr:
65  *index_out = KMAC_INTR_COMMON_KMAC_ERR_BIT;
66  break;
67  default:
68  return false;
69  }
70 
71  return true;
72 }
73 
74 static dif_irq_type_t irq_types[] = {
75  kDifIrqTypeEvent,
76  kDifIrqTypeStatus,
77  kDifIrqTypeEvent,
78 };
79 
80 OT_WARN_UNUSED_RESULT
81 dif_result_t dif_kmac_irq_get_type(const dif_kmac_t *kmac, dif_kmac_irq_t irq,
82  dif_irq_type_t *type) {
83  if (kmac == NULL || type == NULL || irq < 0 || irq > kDifKmacIrqKmacErr) {
84  return kDifBadArg;
85  }
86 
87  *type = irq_types[irq];
88 
89  return kDifOk;
90 }
91 
92 OT_WARN_UNUSED_RESULT
93 dif_result_t dif_kmac_irq_get_state(const dif_kmac_t *kmac,
94  dif_kmac_irq_state_snapshot_t *snapshot) {
95  if (kmac == NULL || snapshot == NULL) {
96  return kDifBadArg;
97  }
98 
99  *snapshot = mmio_region_read32(kmac->base_addr,
100  (ptrdiff_t)KMAC_INTR_STATE_REG_OFFSET);
101 
102  return kDifOk;
103 }
104 
105 OT_WARN_UNUSED_RESULT
106 dif_result_t dif_kmac_irq_acknowledge_state(
107  const dif_kmac_t *kmac, dif_kmac_irq_state_snapshot_t snapshot) {
108  if (kmac == NULL) {
109  return kDifBadArg;
110  }
111 
112  mmio_region_write32(kmac->base_addr, (ptrdiff_t)KMAC_INTR_STATE_REG_OFFSET,
113  snapshot);
114 
115  return kDifOk;
116 }
117 
118 OT_WARN_UNUSED_RESULT
119 dif_result_t dif_kmac_irq_is_pending(const dif_kmac_t *kmac, dif_kmac_irq_t irq,
120  bool *is_pending) {
121  if (kmac == NULL || is_pending == NULL) {
122  return kDifBadArg;
123  }
124 
125  bitfield_bit32_index_t index;
126  if (!kmac_get_irq_bit_index(irq, &index)) {
127  return kDifBadArg;
128  }
129 
130  uint32_t intr_state_reg = mmio_region_read32(
131  kmac->base_addr, (ptrdiff_t)KMAC_INTR_STATE_REG_OFFSET);
132 
133  *is_pending = bitfield_bit32_read(intr_state_reg, index);
134 
135  return kDifOk;
136 }
137 
138 OT_WARN_UNUSED_RESULT
139 dif_result_t dif_kmac_irq_acknowledge_all(const dif_kmac_t *kmac) {
140  if (kmac == NULL) {
141  return kDifBadArg;
142  }
143 
144  // Writing to the register clears the corresponding bits (Write-one clear).
145  mmio_region_write32(kmac->base_addr, (ptrdiff_t)KMAC_INTR_STATE_REG_OFFSET,
146  UINT32_MAX);
147 
148  return kDifOk;
149 }
150 
151 OT_WARN_UNUSED_RESULT
152 dif_result_t dif_kmac_irq_acknowledge(const dif_kmac_t *kmac,
153  dif_kmac_irq_t irq) {
154  if (kmac == NULL) {
155  return kDifBadArg;
156  }
157 
158  bitfield_bit32_index_t index;
159  if (!kmac_get_irq_bit_index(irq, &index)) {
160  return kDifBadArg;
161  }
162 
163  // Writing to the register clears the corresponding bits (Write-one clear).
164  uint32_t intr_state_reg = bitfield_bit32_write(0, index, true);
165  mmio_region_write32(kmac->base_addr, (ptrdiff_t)KMAC_INTR_STATE_REG_OFFSET,
166  intr_state_reg);
167 
168  return kDifOk;
169 }
170 
171 OT_WARN_UNUSED_RESULT
172 dif_result_t dif_kmac_irq_force(const dif_kmac_t *kmac, dif_kmac_irq_t irq,
173  const bool val) {
174  if (kmac == NULL) {
175  return kDifBadArg;
176  }
177 
178  bitfield_bit32_index_t index;
179  if (!kmac_get_irq_bit_index(irq, &index)) {
180  return kDifBadArg;
181  }
182 
183  uint32_t intr_test_reg = bitfield_bit32_write(0, index, val);
184  mmio_region_write32(kmac->base_addr, (ptrdiff_t)KMAC_INTR_TEST_REG_OFFSET,
185  intr_test_reg);
186 
187  return kDifOk;
188 }
189 
190 OT_WARN_UNUSED_RESULT
191 dif_result_t dif_kmac_irq_get_enabled(const dif_kmac_t *kmac,
192  dif_kmac_irq_t irq, dif_toggle_t *state) {
193  if (kmac == NULL || state == NULL) {
194  return kDifBadArg;
195  }
196 
197  bitfield_bit32_index_t index;
198  if (!kmac_get_irq_bit_index(irq, &index)) {
199  return kDifBadArg;
200  }
201 
202  uint32_t intr_enable_reg = mmio_region_read32(
203  kmac->base_addr, (ptrdiff_t)KMAC_INTR_ENABLE_REG_OFFSET);
204 
205  bool is_enabled = bitfield_bit32_read(intr_enable_reg, index);
206  *state = is_enabled ? kDifToggleEnabled : kDifToggleDisabled;
207 
208  return kDifOk;
209 }
210 
211 OT_WARN_UNUSED_RESULT
212 dif_result_t dif_kmac_irq_set_enabled(const dif_kmac_t *kmac,
213  dif_kmac_irq_t irq, dif_toggle_t state) {
214  if (kmac == NULL) {
215  return kDifBadArg;
216  }
217 
218  bitfield_bit32_index_t index;
219  if (!kmac_get_irq_bit_index(irq, &index)) {
220  return kDifBadArg;
221  }
222 
223  uint32_t intr_enable_reg = mmio_region_read32(
224  kmac->base_addr, (ptrdiff_t)KMAC_INTR_ENABLE_REG_OFFSET);
225 
226  bool enable_bit = (state == kDifToggleEnabled) ? true : false;
227  intr_enable_reg = bitfield_bit32_write(intr_enable_reg, index, enable_bit);
228  mmio_region_write32(kmac->base_addr, (ptrdiff_t)KMAC_INTR_ENABLE_REG_OFFSET,
229  intr_enable_reg);
230 
231  return kDifOk;
232 }
233 
234 OT_WARN_UNUSED_RESULT
235 dif_result_t dif_kmac_irq_disable_all(
236  const dif_kmac_t *kmac, dif_kmac_irq_enable_snapshot_t *snapshot) {
237  if (kmac == NULL) {
238  return kDifBadArg;
239  }
240 
241  // Pass the current interrupt state to the caller, if requested.
242  if (snapshot != NULL) {
243  *snapshot = mmio_region_read32(kmac->base_addr,
244  (ptrdiff_t)KMAC_INTR_ENABLE_REG_OFFSET);
245  }
246 
247  // Disable all interrupts.
248  mmio_region_write32(kmac->base_addr, (ptrdiff_t)KMAC_INTR_ENABLE_REG_OFFSET,
249  0u);
250 
251  return kDifOk;
252 }
253 
254 OT_WARN_UNUSED_RESULT
255 dif_result_t dif_kmac_irq_restore_all(
256  const dif_kmac_t *kmac, const dif_kmac_irq_enable_snapshot_t *snapshot) {
257  if (kmac == NULL || snapshot == NULL) {
258  return kDifBadArg;
259  }
260 
261  mmio_region_write32(kmac->base_addr, (ptrdiff_t)KMAC_INTR_ENABLE_REG_OFFSET,
262  *snapshot);
263 
264  return kDifOk;
265 }
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