Software APIs
dif_hmac_autogen.c
1 // Copyright lowRISC contributors (OpenTitan project).
2 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3 // SPDX-License-Identifier: Apache-2.0
4 
5 // THIS FILE HAS BEEN GENERATED, DO NOT EDIT MANUALLY. COMMAND:
6 // util/make_new_dif.py --mode=regen --only=autogen
7 
8 #include "sw/device/lib/dif/autogen/dif_hmac_autogen.h"
9 
10 #include <stdint.h>
11 
12 #include "sw/device/lib/dif/dif_base.h"
13 
14 #include "hmac_regs.h" // Generated.
15 
16 OT_WARN_UNUSED_RESULT
17 dif_result_t dif_hmac_init(mmio_region_t base_addr, dif_hmac_t *hmac) {
18  if (hmac == NULL) {
19  return kDifBadArg;
20  }
21 
22  hmac->base_addr = base_addr;
23 
24  return kDifOk;
25 }
26 
27 dif_result_t dif_hmac_alert_force(const dif_hmac_t *hmac,
28  dif_hmac_alert_t alert) {
29  if (hmac == NULL) {
30  return kDifBadArg;
31  }
32 
33  bitfield_bit32_index_t alert_idx;
34  switch (alert) {
35  case kDifHmacAlertFatalFault:
36  alert_idx = HMAC_ALERT_TEST_FATAL_FAULT_BIT;
37  break;
38  default:
39  return kDifBadArg;
40  }
41 
42  uint32_t alert_test_reg = bitfield_bit32_write(0, alert_idx, true);
43  mmio_region_write32(hmac->base_addr, (ptrdiff_t)HMAC_ALERT_TEST_REG_OFFSET,
44  alert_test_reg);
45 
46  return kDifOk;
47 }
48 
49 /**
50  * Get the corresponding interrupt register bit offset of the IRQ.
51  */
52 static bool hmac_get_irq_bit_index(dif_hmac_irq_t irq,
53  bitfield_bit32_index_t *index_out) {
54  switch (irq) {
55  case kDifHmacIrqHmacDone:
56  *index_out = HMAC_INTR_COMMON_HMAC_DONE_BIT;
57  break;
58  case kDifHmacIrqFifoEmpty:
59  *index_out = HMAC_INTR_COMMON_FIFO_EMPTY_BIT;
60  break;
61  case kDifHmacIrqHmacErr:
62  *index_out = HMAC_INTR_COMMON_HMAC_ERR_BIT;
63  break;
64  default:
65  return false;
66  }
67 
68  return true;
69 }
70 
71 static dif_irq_type_t irq_types[] = {
72  kDifIrqTypeEvent,
73  kDifIrqTypeStatus,
74  kDifIrqTypeEvent,
75 };
76 
77 OT_WARN_UNUSED_RESULT
78 dif_result_t dif_hmac_irq_get_type(const dif_hmac_t *hmac, dif_hmac_irq_t irq,
79  dif_irq_type_t *type) {
80  if (hmac == NULL || type == NULL || irq < 0 || irq > kDifHmacIrqHmacErr) {
81  return kDifBadArg;
82  }
83 
84  *type = irq_types[irq];
85 
86  return kDifOk;
87 }
88 
89 OT_WARN_UNUSED_RESULT
90 dif_result_t dif_hmac_irq_get_state(const dif_hmac_t *hmac,
91  dif_hmac_irq_state_snapshot_t *snapshot) {
92  if (hmac == NULL || snapshot == NULL) {
93  return kDifBadArg;
94  }
95 
96  *snapshot = mmio_region_read32(hmac->base_addr,
97  (ptrdiff_t)HMAC_INTR_STATE_REG_OFFSET);
98 
99  return kDifOk;
100 }
101 
102 OT_WARN_UNUSED_RESULT
103 dif_result_t dif_hmac_irq_acknowledge_state(
104  const dif_hmac_t *hmac, dif_hmac_irq_state_snapshot_t snapshot) {
105  if (hmac == NULL) {
106  return kDifBadArg;
107  }
108 
109  mmio_region_write32(hmac->base_addr, (ptrdiff_t)HMAC_INTR_STATE_REG_OFFSET,
110  snapshot);
111 
112  return kDifOk;
113 }
114 
115 OT_WARN_UNUSED_RESULT
116 dif_result_t dif_hmac_irq_is_pending(const dif_hmac_t *hmac, dif_hmac_irq_t irq,
117  bool *is_pending) {
118  if (hmac == NULL || is_pending == NULL) {
119  return kDifBadArg;
120  }
121 
122  bitfield_bit32_index_t index;
123  if (!hmac_get_irq_bit_index(irq, &index)) {
124  return kDifBadArg;
125  }
126 
127  uint32_t intr_state_reg = mmio_region_read32(
128  hmac->base_addr, (ptrdiff_t)HMAC_INTR_STATE_REG_OFFSET);
129 
130  *is_pending = bitfield_bit32_read(intr_state_reg, index);
131 
132  return kDifOk;
133 }
134 
135 OT_WARN_UNUSED_RESULT
136 dif_result_t dif_hmac_irq_acknowledge_all(const dif_hmac_t *hmac) {
137  if (hmac == NULL) {
138  return kDifBadArg;
139  }
140 
141  // Writing to the register clears the corresponding bits (Write-one clear).
142  mmio_region_write32(hmac->base_addr, (ptrdiff_t)HMAC_INTR_STATE_REG_OFFSET,
143  UINT32_MAX);
144 
145  return kDifOk;
146 }
147 
148 OT_WARN_UNUSED_RESULT
149 dif_result_t dif_hmac_irq_acknowledge(const dif_hmac_t *hmac,
150  dif_hmac_irq_t irq) {
151  if (hmac == NULL) {
152  return kDifBadArg;
153  }
154 
155  bitfield_bit32_index_t index;
156  if (!hmac_get_irq_bit_index(irq, &index)) {
157  return kDifBadArg;
158  }
159 
160  // Writing to the register clears the corresponding bits (Write-one clear).
161  uint32_t intr_state_reg = bitfield_bit32_write(0, index, true);
162  mmio_region_write32(hmac->base_addr, (ptrdiff_t)HMAC_INTR_STATE_REG_OFFSET,
163  intr_state_reg);
164 
165  return kDifOk;
166 }
167 
168 OT_WARN_UNUSED_RESULT
169 dif_result_t dif_hmac_irq_force(const dif_hmac_t *hmac, dif_hmac_irq_t irq,
170  const bool val) {
171  if (hmac == NULL) {
172  return kDifBadArg;
173  }
174 
175  bitfield_bit32_index_t index;
176  if (!hmac_get_irq_bit_index(irq, &index)) {
177  return kDifBadArg;
178  }
179 
180  uint32_t intr_test_reg = bitfield_bit32_write(0, index, val);
181  mmio_region_write32(hmac->base_addr, (ptrdiff_t)HMAC_INTR_TEST_REG_OFFSET,
182  intr_test_reg);
183 
184  return kDifOk;
185 }
186 
187 OT_WARN_UNUSED_RESULT
188 dif_result_t dif_hmac_irq_get_enabled(const dif_hmac_t *hmac,
189  dif_hmac_irq_t irq, dif_toggle_t *state) {
190  if (hmac == NULL || state == NULL) {
191  return kDifBadArg;
192  }
193 
194  bitfield_bit32_index_t index;
195  if (!hmac_get_irq_bit_index(irq, &index)) {
196  return kDifBadArg;
197  }
198 
199  uint32_t intr_enable_reg = mmio_region_read32(
200  hmac->base_addr, (ptrdiff_t)HMAC_INTR_ENABLE_REG_OFFSET);
201 
202  bool is_enabled = bitfield_bit32_read(intr_enable_reg, index);
203  *state = is_enabled ? kDifToggleEnabled : kDifToggleDisabled;
204 
205  return kDifOk;
206 }
207 
208 OT_WARN_UNUSED_RESULT
209 dif_result_t dif_hmac_irq_set_enabled(const dif_hmac_t *hmac,
210  dif_hmac_irq_t irq, dif_toggle_t state) {
211  if (hmac == NULL) {
212  return kDifBadArg;
213  }
214 
215  bitfield_bit32_index_t index;
216  if (!hmac_get_irq_bit_index(irq, &index)) {
217  return kDifBadArg;
218  }
219 
220  uint32_t intr_enable_reg = mmio_region_read32(
221  hmac->base_addr, (ptrdiff_t)HMAC_INTR_ENABLE_REG_OFFSET);
222 
223  bool enable_bit = (state == kDifToggleEnabled) ? true : false;
224  intr_enable_reg = bitfield_bit32_write(intr_enable_reg, index, enable_bit);
225  mmio_region_write32(hmac->base_addr, (ptrdiff_t)HMAC_INTR_ENABLE_REG_OFFSET,
226  intr_enable_reg);
227 
228  return kDifOk;
229 }
230 
231 OT_WARN_UNUSED_RESULT
232 dif_result_t dif_hmac_irq_disable_all(
233  const dif_hmac_t *hmac, dif_hmac_irq_enable_snapshot_t *snapshot) {
234  if (hmac == NULL) {
235  return kDifBadArg;
236  }
237 
238  // Pass the current interrupt state to the caller, if requested.
239  if (snapshot != NULL) {
240  *snapshot = mmio_region_read32(hmac->base_addr,
241  (ptrdiff_t)HMAC_INTR_ENABLE_REG_OFFSET);
242  }
243 
244  // Disable all interrupts.
245  mmio_region_write32(hmac->base_addr, (ptrdiff_t)HMAC_INTR_ENABLE_REG_OFFSET,
246  0u);
247 
248  return kDifOk;
249 }
250 
251 OT_WARN_UNUSED_RESULT
252 dif_result_t dif_hmac_irq_restore_all(
253  const dif_hmac_t *hmac, const dif_hmac_irq_enable_snapshot_t *snapshot) {
254  if (hmac == NULL || snapshot == NULL) {
255  return kDifBadArg;
256  }
257 
258  mmio_region_write32(hmac->base_addr, (ptrdiff_t)HMAC_INTR_ENABLE_REG_OFFSET,
259  *snapshot);
260 
261  return kDifOk;
262 }
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