Software APIs
dif_flash_ctrl_autogen.c
1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
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11// THIS FILE HAS BEEN GENERATED, DO NOT EDIT MANUALLY. COMMAND:
12// util/autogen_dif.py -i
13// hw/top_englishbreakfast/ip_autogen/flash_ctrl/data/flash_ctrl.hjson -o
14// bazel-out/k8-fastbuild-ST-835ede605883/bin/sw/device/lib/dif/autogen
15
16
17#include <stdint.h>
18
19#include "sw/device/lib/dif/dif_base.h"
20#include "sw/device/lib/dif/autogen/dif_flash_ctrl_autogen.h"
21
22#include "hw/top/flash_ctrl_regs.h" // Generated.
23
24
25OT_WARN_UNUSED_RESULT
26dif_result_t dif_flash_ctrl_init(
27 mmio_region_t base_addr,
28 dif_flash_ctrl_t *flash_ctrl) {
29 if (flash_ctrl == NULL) {
30 return kDifBadArg;
31 }
32
33 flash_ctrl->dt = kDtFlashCtrlCount;
34 flash_ctrl->base_addr = base_addr;
35
36 return kDifOk;
37}
38
39OT_WARN_UNUSED_RESULT
40dif_result_t dif_flash_ctrl_init_from_dt(
41 dt_flash_ctrl_t dt,
42 dif_flash_ctrl_t *flash_ctrl) {
43 if (flash_ctrl == NULL) {
44 return kDifBadArg;
45 }
46
47 flash_ctrl->dt = dt;
48 flash_ctrl->base_addr = mmio_region_from_addr(dt_flash_ctrl_primary_reg_block(dt));
49
50 return kDifOk;
51}
52
53dif_result_t dif_flash_ctrl_get_dt(
54 const dif_flash_ctrl_t *flash_ctrl,
55 dt_flash_ctrl_t *dt) {
56 if ((int)flash_ctrl->dt == kDtFlashCtrlCount || dt == NULL) {
57 return kDifBadArg;
58 }
59 *dt = flash_ctrl->dt;
60 return kDifOk;
61}
62
63 dif_result_t dif_flash_ctrl_alert_force(
64 const dif_flash_ctrl_t *flash_ctrl,
65 dif_flash_ctrl_alert_t alert) {
66 if (flash_ctrl == NULL) {
67 return kDifBadArg;
68 }
69
70 bitfield_bit32_index_t alert_idx;
71 switch (alert) {
72 case kDifFlashCtrlAlertRecovErr:
73 alert_idx = FLASH_CTRL_ALERT_TEST_RECOV_ERR_BIT;
74 break;
75 case kDifFlashCtrlAlertFatalStdErr:
76 alert_idx = FLASH_CTRL_ALERT_TEST_FATAL_STD_ERR_BIT;
77 break;
78 case kDifFlashCtrlAlertFatalErr:
79 alert_idx = FLASH_CTRL_ALERT_TEST_FATAL_ERR_BIT;
80 break;
81 case kDifFlashCtrlAlertFatalPrimFlashAlert:
82 alert_idx = FLASH_CTRL_ALERT_TEST_FATAL_PRIM_FLASH_ALERT_BIT;
83 break;
84 case kDifFlashCtrlAlertRecovPrimFlashAlert:
85 alert_idx = FLASH_CTRL_ALERT_TEST_RECOV_PRIM_FLASH_ALERT_BIT;
86 break;
87 default:
88 return kDifBadArg;
89 }
90
91 uint32_t alert_test_reg = bitfield_bit32_write(0, alert_idx, true);
92 // Keep the alert test enabled: writing 0 to the regwen bit locks the register.
93 alert_test_reg = bitfield_bit32_write(
94 alert_test_reg, FLASH_CTRL_ALERT_TEST_REGWEN_BIT, true);
95 mmio_region_write32(
96 flash_ctrl->base_addr,
97 (ptrdiff_t)FLASH_CTRL_ALERT_TEST_REG_OFFSET,
98 alert_test_reg);
99
100
101 return kDifOk;
102}
103
104
105 /**
106 * Get the corresponding interrupt register bit offset of the IRQ.
107 */
108 static bool flash_ctrl_get_irq_bit_index(
109 dif_flash_ctrl_irq_t irq,
110 bitfield_bit32_index_t *index_out) {
111
112 switch (irq) {
113 case kDtFlashCtrlIrqProgEmpty:
114 *index_out = FLASH_CTRL_INTR_COMMON_PROG_EMPTY_BIT;
115 break;
116 case kDtFlashCtrlIrqProgLvl:
117 *index_out = FLASH_CTRL_INTR_COMMON_PROG_LVL_BIT;
118 break;
119 case kDtFlashCtrlIrqRdFull:
120 *index_out = FLASH_CTRL_INTR_COMMON_RD_FULL_BIT;
121 break;
122 case kDtFlashCtrlIrqRdLvl:
123 *index_out = FLASH_CTRL_INTR_COMMON_RD_LVL_BIT;
124 break;
125 case kDtFlashCtrlIrqOpDone:
126 *index_out = FLASH_CTRL_INTR_COMMON_OP_DONE_BIT;
127 break;
128 case kDtFlashCtrlIrqCorrErr:
129 *index_out = FLASH_CTRL_INTR_COMMON_CORR_ERR_BIT;
130 break;
131 default:
132 return false;
133 }
134
135 return true;
136 }
137
138 static dif_irq_type_t irq_types[] = {
139 kDifIrqTypeStatus,
140 kDifIrqTypeStatus,
141 kDifIrqTypeStatus,
142 kDifIrqTypeStatus,
143 kDifIrqTypeEvent,
144 kDifIrqTypeEvent,
145 };
146
147 OT_WARN_UNUSED_RESULT
148 dif_result_t dif_flash_ctrl_irq_get_type(
149 const dif_flash_ctrl_t *flash_ctrl,
150 dif_flash_ctrl_irq_t irq,
151 dif_irq_type_t *type) {
152
153
154 if (flash_ctrl == NULL ||
155 type == NULL ||
156 irq < kDifFlashCtrlIrqProgEmpty ||
157 irq > kDifFlashCtrlIrqCorrErr) {
158 return kDifBadArg;
159 }
160
161 *type = irq_types[irq];
162
163 return kDifOk;
164 }
165
166 OT_WARN_UNUSED_RESULT
167 dif_result_t dif_flash_ctrl_irq_get_state(
168 const dif_flash_ctrl_t *flash_ctrl,
169 dif_flash_ctrl_irq_state_snapshot_t *snapshot) {
170
171 if (flash_ctrl == NULL || snapshot == NULL) {
172 return kDifBadArg;
173 }
174
175 *snapshot = mmio_region_read32(
176 flash_ctrl->base_addr,
177 (ptrdiff_t)FLASH_CTRL_INTR_STATE_REG_OFFSET);
178
179
180 return kDifOk;
181 }
182
183 OT_WARN_UNUSED_RESULT
184 dif_result_t dif_flash_ctrl_irq_acknowledge_state(
185 const dif_flash_ctrl_t *flash_ctrl,
186 dif_flash_ctrl_irq_state_snapshot_t snapshot) {
187 if (flash_ctrl == NULL) {
188 return kDifBadArg;
189 }
190
191 mmio_region_write32(
192 flash_ctrl->base_addr,
193 (ptrdiff_t)FLASH_CTRL_INTR_STATE_REG_OFFSET,
194 snapshot);
195
196
197 return kDifOk;
198 }
199
200 OT_WARN_UNUSED_RESULT
201 dif_result_t dif_flash_ctrl_irq_is_pending(
202 const dif_flash_ctrl_t *flash_ctrl,
203 dif_flash_ctrl_irq_t irq,
204 bool *is_pending) {
205
206 if (flash_ctrl == NULL || is_pending == NULL) {
207 return kDifBadArg;
208 }
209
210 bitfield_bit32_index_t index;
211 if (!flash_ctrl_get_irq_bit_index(irq, &index)) {
212 return kDifBadArg;
213 }
214
215 uint32_t intr_state_reg = mmio_region_read32(
216 flash_ctrl->base_addr,
217 (ptrdiff_t)FLASH_CTRL_INTR_STATE_REG_OFFSET);
218
219
220 *is_pending = bitfield_bit32_read(intr_state_reg, index);
221
222 return kDifOk;
223 }
224
225 OT_WARN_UNUSED_RESULT
226 dif_result_t dif_flash_ctrl_irq_acknowledge_all(
227 const dif_flash_ctrl_t *flash_ctrl
228 ) {
229
230 if (flash_ctrl == NULL) {
231 return kDifBadArg;
232 }
233
234 // Writing to the register clears the corresponding bits (Write-one clear).
235 mmio_region_write32(
236 flash_ctrl->base_addr,
237 (ptrdiff_t)FLASH_CTRL_INTR_STATE_REG_OFFSET,
238 UINT32_MAX);
239
240
241 return kDifOk;
242 }
243
244 OT_WARN_UNUSED_RESULT
245 dif_result_t dif_flash_ctrl_irq_acknowledge(
246 const dif_flash_ctrl_t *flash_ctrl,
247 dif_flash_ctrl_irq_t irq) {
248
249 if (flash_ctrl == NULL) {
250 return kDifBadArg;
251 }
252
253 bitfield_bit32_index_t index;
254 if (!flash_ctrl_get_irq_bit_index(irq, &index)) {
255 return kDifBadArg;
256 }
257
258 // Writing to the register clears the corresponding bits (Write-one clear).
259 uint32_t intr_state_reg = bitfield_bit32_write(0, index, true);
260 mmio_region_write32(
261 flash_ctrl->base_addr,
262 (ptrdiff_t)FLASH_CTRL_INTR_STATE_REG_OFFSET,
263 intr_state_reg);
264
265
266 return kDifOk;
267 }
268
269 OT_WARN_UNUSED_RESULT
270 dif_result_t dif_flash_ctrl_irq_force(
271 const dif_flash_ctrl_t *flash_ctrl,
272 dif_flash_ctrl_irq_t irq,
273 const bool val) {
274
275 if (flash_ctrl == NULL) {
276 return kDifBadArg;
277 }
278
279 bitfield_bit32_index_t index;
280 if (!flash_ctrl_get_irq_bit_index(irq, &index)) {
281 return kDifBadArg;
282 }
283
284 uint32_t intr_test_reg = bitfield_bit32_write(0, index, val);
285 mmio_region_write32(
286 flash_ctrl->base_addr,
287 (ptrdiff_t)FLASH_CTRL_INTR_TEST_REG_OFFSET,
288 intr_test_reg);
289
290
291 return kDifOk;
292 }
293
294 OT_WARN_UNUSED_RESULT
295 dif_result_t dif_flash_ctrl_irq_get_enabled(
296 const dif_flash_ctrl_t *flash_ctrl,
297 dif_flash_ctrl_irq_t irq,
298 dif_toggle_t *state) {
299
300 if (flash_ctrl == NULL || state == NULL) {
301 return kDifBadArg;
302 }
303
304 bitfield_bit32_index_t index;
305 if (!flash_ctrl_get_irq_bit_index(irq, &index)) {
306 return kDifBadArg;
307 }
308
309 uint32_t intr_enable_reg = mmio_region_read32(
310 flash_ctrl->base_addr,
311 (ptrdiff_t)FLASH_CTRL_INTR_ENABLE_REG_OFFSET);
312
313
314 bool is_enabled = bitfield_bit32_read(intr_enable_reg, index);
315 *state = is_enabled ?
316 kDifToggleEnabled : kDifToggleDisabled;
317
318 return kDifOk;
319 }
320
321 OT_WARN_UNUSED_RESULT
322 dif_result_t dif_flash_ctrl_irq_set_enabled(
323 const dif_flash_ctrl_t *flash_ctrl,
324 dif_flash_ctrl_irq_t irq,
325 dif_toggle_t state) {
326
327 if (flash_ctrl == NULL) {
328 return kDifBadArg;
329 }
330
331 bitfield_bit32_index_t index;
332 if (!flash_ctrl_get_irq_bit_index(irq, &index)) {
333 return kDifBadArg;
334 }
335
336 uint32_t intr_enable_reg = mmio_region_read32(
337 flash_ctrl->base_addr,
338 (ptrdiff_t)FLASH_CTRL_INTR_ENABLE_REG_OFFSET);
339
340
341 bool enable_bit = (state == kDifToggleEnabled) ? true : false;
342 intr_enable_reg = bitfield_bit32_write(intr_enable_reg, index, enable_bit);
343 mmio_region_write32(
344 flash_ctrl->base_addr,
345 (ptrdiff_t)FLASH_CTRL_INTR_ENABLE_REG_OFFSET,
346 intr_enable_reg);
347
348
349 return kDifOk;
350 }
351
352 OT_WARN_UNUSED_RESULT
353 dif_result_t dif_flash_ctrl_irq_disable_all(
354 const dif_flash_ctrl_t *flash_ctrl,
355 dif_flash_ctrl_irq_enable_snapshot_t *snapshot) {
356
357 if (flash_ctrl == NULL) {
358 return kDifBadArg;
359 }
360
361 // Pass the current interrupt state to the caller, if requested.
362 if (snapshot != NULL) {
363 *snapshot = mmio_region_read32(
364 flash_ctrl->base_addr,
365 (ptrdiff_t)FLASH_CTRL_INTR_ENABLE_REG_OFFSET);
366
367 }
368
369 // Disable all interrupts.
370 mmio_region_write32(
371 flash_ctrl->base_addr,
372 (ptrdiff_t)FLASH_CTRL_INTR_ENABLE_REG_OFFSET,
373 0u);
374
375
376 return kDifOk;
377 }
378
379 OT_WARN_UNUSED_RESULT
380 dif_result_t dif_flash_ctrl_irq_restore_all(
381 const dif_flash_ctrl_t *flash_ctrl,
382 const dif_flash_ctrl_irq_enable_snapshot_t *snapshot) {
383
384 if (flash_ctrl == NULL || snapshot == NULL) {
385 return kDifBadArg;
386 }
387
388 mmio_region_write32(
389 flash_ctrl->base_addr,
390 (ptrdiff_t)FLASH_CTRL_INTR_ENABLE_REG_OFFSET,
391 *snapshot);
392
393
394 return kDifOk;
395 }
396