Software APIs
dif_flash_ctrl_autogen.c
1 // Copyright lowRISC contributors (OpenTitan project).
2 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3 // SPDX-License-Identifier: Apache-2.0
4 
5 // THIS FILE HAS BEEN GENERATED, DO NOT EDIT MANUALLY. COMMAND:
6 // util/make_new_dif.py --mode=regen --only=autogen
7 
8 #include "sw/device/lib/dif/autogen/dif_flash_ctrl_autogen.h"
9 
10 #include <stdint.h>
11 
12 #include "sw/device/lib/dif/dif_base.h"
13 
14 #include "flash_ctrl_regs.h" // Generated.
15 
16 OT_WARN_UNUSED_RESULT
17 dif_result_t dif_flash_ctrl_init(mmio_region_t base_addr,
18  dif_flash_ctrl_t *flash_ctrl) {
19  if (flash_ctrl == NULL) {
20  return kDifBadArg;
21  }
22 
23  flash_ctrl->base_addr = base_addr;
24 
25  return kDifOk;
26 }
27 
28 dif_result_t dif_flash_ctrl_alert_force(const dif_flash_ctrl_t *flash_ctrl,
29  dif_flash_ctrl_alert_t alert) {
30  if (flash_ctrl == NULL) {
31  return kDifBadArg;
32  }
33 
34  bitfield_bit32_index_t alert_idx;
35  switch (alert) {
36  case kDifFlashCtrlAlertRecovErr:
37  alert_idx = FLASH_CTRL_ALERT_TEST_RECOV_ERR_BIT;
38  break;
39  case kDifFlashCtrlAlertFatalStdErr:
40  alert_idx = FLASH_CTRL_ALERT_TEST_FATAL_STD_ERR_BIT;
41  break;
42  case kDifFlashCtrlAlertFatalErr:
43  alert_idx = FLASH_CTRL_ALERT_TEST_FATAL_ERR_BIT;
44  break;
45  case kDifFlashCtrlAlertFatalPrimFlashAlert:
46  alert_idx = FLASH_CTRL_ALERT_TEST_FATAL_PRIM_FLASH_ALERT_BIT;
47  break;
48  case kDifFlashCtrlAlertRecovPrimFlashAlert:
49  alert_idx = FLASH_CTRL_ALERT_TEST_RECOV_PRIM_FLASH_ALERT_BIT;
50  break;
51  default:
52  return kDifBadArg;
53  }
54 
55  uint32_t alert_test_reg = bitfield_bit32_write(0, alert_idx, true);
56  mmio_region_write32(flash_ctrl->base_addr,
57  (ptrdiff_t)FLASH_CTRL_ALERT_TEST_REG_OFFSET,
58  alert_test_reg);
59 
60  return kDifOk;
61 }
62 
63 /**
64  * Get the corresponding interrupt register bit offset of the IRQ.
65  */
66 static bool flash_ctrl_get_irq_bit_index(dif_flash_ctrl_irq_t irq,
67  bitfield_bit32_index_t *index_out) {
68  switch (irq) {
69  case kDifFlashCtrlIrqProgEmpty:
70  *index_out = FLASH_CTRL_INTR_COMMON_PROG_EMPTY_BIT;
71  break;
72  case kDifFlashCtrlIrqProgLvl:
73  *index_out = FLASH_CTRL_INTR_COMMON_PROG_LVL_BIT;
74  break;
75  case kDifFlashCtrlIrqRdFull:
76  *index_out = FLASH_CTRL_INTR_COMMON_RD_FULL_BIT;
77  break;
78  case kDifFlashCtrlIrqRdLvl:
79  *index_out = FLASH_CTRL_INTR_COMMON_RD_LVL_BIT;
80  break;
81  case kDifFlashCtrlIrqOpDone:
82  *index_out = FLASH_CTRL_INTR_COMMON_OP_DONE_BIT;
83  break;
84  case kDifFlashCtrlIrqCorrErr:
85  *index_out = FLASH_CTRL_INTR_COMMON_CORR_ERR_BIT;
86  break;
87  default:
88  return false;
89  }
90 
91  return true;
92 }
93 
94 static dif_irq_type_t irq_types[] = {
95  kDifIrqTypeStatus, kDifIrqTypeStatus, kDifIrqTypeStatus,
96  kDifIrqTypeStatus, kDifIrqTypeEvent, kDifIrqTypeEvent,
97 };
98 
99 OT_WARN_UNUSED_RESULT
100 dif_result_t dif_flash_ctrl_irq_get_type(const dif_flash_ctrl_t *flash_ctrl,
101  dif_flash_ctrl_irq_t irq,
102  dif_irq_type_t *type) {
103  if (flash_ctrl == NULL || type == NULL || irq < 0 ||
104  irq > kDifFlashCtrlIrqCorrErr) {
105  return kDifBadArg;
106  }
107 
108  *type = irq_types[irq];
109 
110  return kDifOk;
111 }
112 
113 OT_WARN_UNUSED_RESULT
114 dif_result_t dif_flash_ctrl_irq_get_state(
115  const dif_flash_ctrl_t *flash_ctrl,
116  dif_flash_ctrl_irq_state_snapshot_t *snapshot) {
117  if (flash_ctrl == NULL || snapshot == NULL) {
118  return kDifBadArg;
119  }
120 
121  *snapshot = mmio_region_read32(flash_ctrl->base_addr,
122  (ptrdiff_t)FLASH_CTRL_INTR_STATE_REG_OFFSET);
123 
124  return kDifOk;
125 }
126 
127 OT_WARN_UNUSED_RESULT
128 dif_result_t dif_flash_ctrl_irq_acknowledge_state(
129  const dif_flash_ctrl_t *flash_ctrl,
130  dif_flash_ctrl_irq_state_snapshot_t snapshot) {
131  if (flash_ctrl == NULL) {
132  return kDifBadArg;
133  }
134 
135  mmio_region_write32(flash_ctrl->base_addr,
136  (ptrdiff_t)FLASH_CTRL_INTR_STATE_REG_OFFSET, snapshot);
137 
138  return kDifOk;
139 }
140 
141 OT_WARN_UNUSED_RESULT
142 dif_result_t dif_flash_ctrl_irq_is_pending(const dif_flash_ctrl_t *flash_ctrl,
143  dif_flash_ctrl_irq_t irq,
144  bool *is_pending) {
145  if (flash_ctrl == NULL || is_pending == NULL) {
146  return kDifBadArg;
147  }
148 
149  bitfield_bit32_index_t index;
150  if (!flash_ctrl_get_irq_bit_index(irq, &index)) {
151  return kDifBadArg;
152  }
153 
154  uint32_t intr_state_reg = mmio_region_read32(
155  flash_ctrl->base_addr, (ptrdiff_t)FLASH_CTRL_INTR_STATE_REG_OFFSET);
156 
157  *is_pending = bitfield_bit32_read(intr_state_reg, index);
158 
159  return kDifOk;
160 }
161 
162 OT_WARN_UNUSED_RESULT
163 dif_result_t dif_flash_ctrl_irq_acknowledge_all(
164  const dif_flash_ctrl_t *flash_ctrl) {
165  if (flash_ctrl == NULL) {
166  return kDifBadArg;
167  }
168 
169  // Writing to the register clears the corresponding bits (Write-one clear).
170  mmio_region_write32(flash_ctrl->base_addr,
171  (ptrdiff_t)FLASH_CTRL_INTR_STATE_REG_OFFSET, UINT32_MAX);
172 
173  return kDifOk;
174 }
175 
176 OT_WARN_UNUSED_RESULT
177 dif_result_t dif_flash_ctrl_irq_acknowledge(const dif_flash_ctrl_t *flash_ctrl,
178  dif_flash_ctrl_irq_t irq) {
179  if (flash_ctrl == NULL) {
180  return kDifBadArg;
181  }
182 
183  bitfield_bit32_index_t index;
184  if (!flash_ctrl_get_irq_bit_index(irq, &index)) {
185  return kDifBadArg;
186  }
187 
188  // Writing to the register clears the corresponding bits (Write-one clear).
189  uint32_t intr_state_reg = bitfield_bit32_write(0, index, true);
190  mmio_region_write32(flash_ctrl->base_addr,
191  (ptrdiff_t)FLASH_CTRL_INTR_STATE_REG_OFFSET,
192  intr_state_reg);
193 
194  return kDifOk;
195 }
196 
197 OT_WARN_UNUSED_RESULT
198 dif_result_t dif_flash_ctrl_irq_force(const dif_flash_ctrl_t *flash_ctrl,
199  dif_flash_ctrl_irq_t irq,
200  const bool val) {
201  if (flash_ctrl == NULL) {
202  return kDifBadArg;
203  }
204 
205  bitfield_bit32_index_t index;
206  if (!flash_ctrl_get_irq_bit_index(irq, &index)) {
207  return kDifBadArg;
208  }
209 
210  uint32_t intr_test_reg = bitfield_bit32_write(0, index, val);
211  mmio_region_write32(flash_ctrl->base_addr,
212  (ptrdiff_t)FLASH_CTRL_INTR_TEST_REG_OFFSET,
213  intr_test_reg);
214 
215  return kDifOk;
216 }
217 
218 OT_WARN_UNUSED_RESULT
219 dif_result_t dif_flash_ctrl_irq_get_enabled(const dif_flash_ctrl_t *flash_ctrl,
220  dif_flash_ctrl_irq_t irq,
221  dif_toggle_t *state) {
222  if (flash_ctrl == NULL || state == NULL) {
223  return kDifBadArg;
224  }
225 
226  bitfield_bit32_index_t index;
227  if (!flash_ctrl_get_irq_bit_index(irq, &index)) {
228  return kDifBadArg;
229  }
230 
231  uint32_t intr_enable_reg = mmio_region_read32(
232  flash_ctrl->base_addr, (ptrdiff_t)FLASH_CTRL_INTR_ENABLE_REG_OFFSET);
233 
234  bool is_enabled = bitfield_bit32_read(intr_enable_reg, index);
235  *state = is_enabled ? kDifToggleEnabled : kDifToggleDisabled;
236 
237  return kDifOk;
238 }
239 
240 OT_WARN_UNUSED_RESULT
241 dif_result_t dif_flash_ctrl_irq_set_enabled(const dif_flash_ctrl_t *flash_ctrl,
242  dif_flash_ctrl_irq_t irq,
243  dif_toggle_t state) {
244  if (flash_ctrl == NULL) {
245  return kDifBadArg;
246  }
247 
248  bitfield_bit32_index_t index;
249  if (!flash_ctrl_get_irq_bit_index(irq, &index)) {
250  return kDifBadArg;
251  }
252 
253  uint32_t intr_enable_reg = mmio_region_read32(
254  flash_ctrl->base_addr, (ptrdiff_t)FLASH_CTRL_INTR_ENABLE_REG_OFFSET);
255 
256  bool enable_bit = (state == kDifToggleEnabled) ? true : false;
257  intr_enable_reg = bitfield_bit32_write(intr_enable_reg, index, enable_bit);
258  mmio_region_write32(flash_ctrl->base_addr,
259  (ptrdiff_t)FLASH_CTRL_INTR_ENABLE_REG_OFFSET,
260  intr_enable_reg);
261 
262  return kDifOk;
263 }
264 
265 OT_WARN_UNUSED_RESULT
266 dif_result_t dif_flash_ctrl_irq_disable_all(
267  const dif_flash_ctrl_t *flash_ctrl,
268  dif_flash_ctrl_irq_enable_snapshot_t *snapshot) {
269  if (flash_ctrl == NULL) {
270  return kDifBadArg;
271  }
272 
273  // Pass the current interrupt state to the caller, if requested.
274  if (snapshot != NULL) {
275  *snapshot = mmio_region_read32(
276  flash_ctrl->base_addr, (ptrdiff_t)FLASH_CTRL_INTR_ENABLE_REG_OFFSET);
277  }
278 
279  // Disable all interrupts.
280  mmio_region_write32(flash_ctrl->base_addr,
281  (ptrdiff_t)FLASH_CTRL_INTR_ENABLE_REG_OFFSET, 0u);
282 
283  return kDifOk;
284 }
285 
286 OT_WARN_UNUSED_RESULT
287 dif_result_t dif_flash_ctrl_irq_restore_all(
288  const dif_flash_ctrl_t *flash_ctrl,
289  const dif_flash_ctrl_irq_enable_snapshot_t *snapshot) {
290  if (flash_ctrl == NULL || snapshot == NULL) {
291  return kDifBadArg;
292  }
293 
294  mmio_region_write32(flash_ctrl->base_addr,
295  (ptrdiff_t)FLASH_CTRL_INTR_ENABLE_REG_OFFSET, *snapshot);
296 
297  return kDifOk;
298 }
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