142dif_flash_ctrl_device_info_t dif_flash_ctrl_get_device_info(
void) {
143 const dif_flash_ctrl_device_info_t info = {
144 .num_banks = FLASH_CTRL_PARAM_REG_NUM_BANKS,
145 .bytes_per_word = FLASH_CTRL_PARAM_BYTES_PER_WORD,
146 .bytes_per_page = FLASH_CTRL_PARAM_BYTES_PER_PAGE,
147 .data_pages = FLASH_CTRL_PARAM_REG_PAGES_PER_BANK,
148 .info0_pages = FLASH_CTRL_PARAM_NUM_INFOS0,
149 .info1_pages = FLASH_CTRL_PARAM_NUM_INFOS1,
150 .info2_pages = FLASH_CTRL_PARAM_NUM_INFOS2,
241 if (handle == NULL) {
245 mmio_region_read32(handle->
dev.
base_addr, FLASH_CTRL_INIT_REG_OFFSET);
246 if (bitfield_bit32_read(reg, FLASH_CTRL_INIT_VAL_BIT)) {
250 uint32_t value = bitfield_bit32_write(0, FLASH_CTRL_INIT_VAL_BIT,
true);
251 mmio_region_write32(handle->
dev.
base_addr, FLASH_CTRL_INIT_REG_OFFSET, value);
258 if (handle == NULL || status_out == NULL) {
262 mmio_region_read32(handle->
dev.
base_addr, FLASH_CTRL_STATUS_REG_OFFSET);
264 .read_fifo_full = bitfield_bit32_read(reg, FLASH_CTRL_STATUS_RD_FULL_BIT),
266 bitfield_bit32_read(reg, FLASH_CTRL_STATUS_RD_EMPTY_BIT),
268 bitfield_bit32_read(reg, FLASH_CTRL_STATUS_PROG_FULL_BIT),
270 bitfield_bit32_read(reg, FLASH_CTRL_STATUS_PROG_EMPTY_BIT),
271 .controller_init_wip =
272 bitfield_bit32_read(reg, FLASH_CTRL_STATUS_INIT_WIP_BIT),
273 .controller_initialized =
274 bitfield_bit32_read(reg, FLASH_CTRL_STATUS_INITIALIZED_BIT),
284 if (handle == NULL || allowed_types_out == NULL) {
288 uint32_t reg = mmio_region_read32(handle->
dev.
base_addr,
289 FLASH_CTRL_PROG_TYPE_EN_REG_OFFSET);
292 bitfield_bit32_read(reg, FLASH_CTRL_PROG_TYPE_EN_NORMAL_BIT),
294 bitfield_bit32_read(reg, FLASH_CTRL_PROG_TYPE_EN_REPAIR_BIT),
296 *allowed_types_out = allowed_types;
304 if (handle == NULL) {
308 uint32_t ctrl_regwen = mmio_region_read32(handle->
dev.
base_addr,
309 FLASH_CTRL_CTRL_REGWEN_REG_OFFSET);
310 if (!bitfield_bit32_read(ctrl_regwen, FLASH_CTRL_CTRL_REGWEN_EN_BIT)) {
315 reg = bitfield_bit32_write(reg, FLASH_CTRL_PROG_TYPE_EN_NORMAL_BIT,
317 reg = bitfield_bit32_write(reg, FLASH_CTRL_PROG_TYPE_EN_REPAIR_BIT,
319 mmio_region_write32(handle->
dev.
base_addr, FLASH_CTRL_PROG_TYPE_EN_REG_OFFSET,
327 if (handle == NULL) {
330 uint32_t ctrl_regwen = mmio_region_read32(handle->
dev.
base_addr,
331 FLASH_CTRL_CTRL_REGWEN_REG_OFFSET);
332 if (!bitfield_bit32_read(ctrl_regwen, FLASH_CTRL_CTRL_REGWEN_EN_BIT)) {
336 uint32_t control_reg = bitfield_field32_write(0, FLASH_CTRL_CONTROL_NUM_FIELD,
338 switch (transaction.op) {
341 bitfield_field32_write(control_reg, FLASH_CTRL_CONTROL_OP_FIELD,
342 FLASH_CTRL_CONTROL_OP_VALUE_READ);
346 bitfield_field32_write(control_reg, FLASH_CTRL_CONTROL_OP_FIELD,
347 FLASH_CTRL_CONTROL_OP_VALUE_PROG);
348 control_reg = bitfield_bit32_write(
349 control_reg, FLASH_CTRL_CONTROL_PROG_SEL_BIT,
false);
353 bitfield_field32_write(control_reg, FLASH_CTRL_CONTROL_OP_FIELD,
354 FLASH_CTRL_CONTROL_OP_VALUE_PROG);
355 control_reg = bitfield_bit32_write(control_reg,
356 FLASH_CTRL_CONTROL_PROG_SEL_BIT,
true);
360 bitfield_field32_write(control_reg, FLASH_CTRL_CONTROL_OP_FIELD,
361 FLASH_CTRL_CONTROL_OP_VALUE_ERASE);
362 control_reg = bitfield_bit32_write(
363 control_reg, FLASH_CTRL_CONTROL_ERASE_SEL_BIT,
false);
367 bitfield_field32_write(control_reg, FLASH_CTRL_CONTROL_OP_FIELD,
368 FLASH_CTRL_CONTROL_OP_VALUE_ERASE);
369 control_reg = bitfield_bit32_write(
370 control_reg, FLASH_CTRL_CONTROL_ERASE_SEL_BIT,
true);
377 case kDifFlashCtrlPartitionTypeData:
378 control_reg = bitfield_bit32_write(
379 control_reg, FLASH_CTRL_CONTROL_PARTITION_SEL_BIT,
false);
381 case kDifFlashCtrlPartitionTypeInfo:
383 bitfield_field32_write(control_reg, FLASH_CTRL_CONTROL_INFO_SEL_FIELD,
385 control_reg = bitfield_bit32_write(
386 control_reg, FLASH_CTRL_CONTROL_PARTITION_SEL_BIT,
true);
392 mmio_region_write32(handle->
dev.
base_addr, FLASH_CTRL_CONTROL_REG_OFFSET,
394 mmio_region_write32(handle->
dev.
base_addr, FLASH_CTRL_ADDR_REG_OFFSET,
396 mmio_region_write32(handle->
dev.
base_addr, FLASH_CTRL_CONTROL_REG_OFFSET,
397 control_reg | (1u << FLASH_CTRL_CONTROL_START_BIT));
493 const uint32_t *data) {
494 if (handle == NULL || data == NULL) {
503 const uint32_t control_reg =
504 mmio_region_read32(handle->
dev.
base_addr, FLASH_CTRL_CONTROL_REG_OFFSET);
506 bitfield_field32_read(control_reg, FLASH_CTRL_CONTROL_OP_FIELD);
507 if (op != FLASH_CTRL_CONTROL_OP_VALUE_PROG) {
510 return dif_flash_ctrl_prog_fifo_push_unsafe(handle, word_count, data);
532 uint32_t word_count, uint32_t *data) {
533 if (handle == NULL || data == NULL) {
542 const uint32_t control_reg =
543 mmio_region_read32(handle->
dev.
base_addr, FLASH_CTRL_CONTROL_REG_OFFSET);
545 bitfield_field32_read(control_reg, FLASH_CTRL_CONTROL_OP_FIELD);
546 if (op != FLASH_CTRL_CONTROL_OP_VALUE_READ) {
549 return dif_flash_ctrl_read_fifo_pop_unsafe(handle, word_count, data);
556 if (handle == NULL || error_code_out == NULL) {
559 const uint32_t code_reg =
560 mmio_region_read32(handle->
dev.
base_addr, FLASH_CTRL_ERR_CODE_REG_OFFSET);
561 dif_flash_ctrl_error_codes_t codes = {
562 .memory_properties_error =
563 bitfield_bit32_read(code_reg, FLASH_CTRL_ERR_CODE_MP_ERR_BIT),
565 bitfield_bit32_read(code_reg, FLASH_CTRL_ERR_CODE_RD_ERR_BIT),
567 bitfield_bit32_read(code_reg, FLASH_CTRL_ERR_CODE_PROG_WIN_ERR_BIT),
569 bitfield_bit32_read(code_reg, FLASH_CTRL_ERR_CODE_PROG_TYPE_ERR_BIT),
570 .shadow_register_error =
571 bitfield_bit32_read(code_reg, FLASH_CTRL_ERR_CODE_UPDATE_ERR_BIT),
574 const uint32_t address_reg =
575 mmio_region_read32(handle->
dev.
base_addr, FLASH_CTRL_ERR_ADDR_REG_OFFSET);
577 .address = address_reg,
580 *error_code_out = error_code;
587 if (handle == NULL) {
590 uint32_t code_reg = 0;
591 code_reg = bitfield_bit32_write(code_reg, FLASH_CTRL_ERR_CODE_MP_ERR_BIT,
593 code_reg = bitfield_bit32_write(code_reg, FLASH_CTRL_ERR_CODE_RD_ERR_BIT,
595 code_reg = bitfield_bit32_write(
597 code_reg = bitfield_bit32_write(
598 code_reg, FLASH_CTRL_ERR_CODE_PROG_TYPE_ERR_BIT, codes.
prog_type_error);
599 code_reg = bitfield_bit32_write(code_reg, FLASH_CTRL_ERR_CODE_UPDATE_ERR_BIT,
601 mmio_region_write32(handle->
dev.
base_addr, FLASH_CTRL_ERR_CODE_REG_OFFSET,
608 dif_flash_ctrl_output_t *out) {
609 if (handle == NULL || out == NULL) {
615 uint32_t status_reg = mmio_region_read32(handle->
dev.
base_addr,
616 FLASH_CTRL_OP_STATUS_REG_OFFSET);
617 if (!bitfield_bit32_read(status_reg, FLASH_CTRL_OP_STATUS_DONE_BIT)) {
625 dif_flash_ctrl_output_t output = {
627 bitfield_bit32_read(status_reg, FLASH_CTRL_OP_STATUS_DONE_BIT),
629 bitfield_bit32_read(status_reg, FLASH_CTRL_OP_STATUS_ERR_BIT),
630 .error_code = error_code_tmp};
632 mmio_region_write32(handle->
dev.
base_addr, FLASH_CTRL_OP_STATUS_REG_OFFSET,
642 if (handle == NULL || region >= FLASH_CTRL_PARAM_NUM_REGIONS) {
648 dif_flash_ctrl_data_region_is_locked(handle, region, &locked));
653 ptrdiff_t mp_reg_offset = get_data_region_mp_reg_offset(region);
654 uint32_t mp_reg = mmio_region_read32(handle->
dev.
base_addr, mp_reg_offset);
657 mp_reg = bitfield_field32_write(
658 mp_reg, FLASH_CTRL_MP_REGION_CFG_0_EN_0_FIELD, kMultiBitBool4True);
661 mp_reg = bitfield_field32_write(
662 mp_reg, FLASH_CTRL_MP_REGION_CFG_0_EN_0_FIELD, kMultiBitBool4False);
667 mmio_region_write32(handle->
dev.
base_addr, mp_reg_offset, mp_reg);
675 if (handle == NULL || enabled_out == NULL ||
676 region >= FLASH_CTRL_PARAM_NUM_REGIONS) {
679 ptrdiff_t mp_reg_offset = get_data_region_mp_reg_offset(region);
680 uint32_t mp_reg = mmio_region_read32(handle->
dev.
base_addr, mp_reg_offset);
681 if (bitfield_field32_read(mp_reg, FLASH_CTRL_MP_REGION_CFG_0_EN_0_FIELD) ==
682 kMultiBitBool4True) {
694 if (handle == NULL || region.
bank >= FLASH_CTRL_PARAM_REG_NUM_BANKS ||
701 dif_flash_ctrl_info_region_is_locked(handle, region, &locked));
706 ptrdiff_t mp_reg_offset = get_info_region_mp_reg_offset(region);
707 uint32_t mp_reg = mmio_region_read32(handle->
dev.
base_addr, mp_reg_offset);
710 mp_reg = bitfield_field32_write(
711 mp_reg, FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_EN_0_FIELD,
715 mp_reg = bitfield_field32_write(
716 mp_reg, FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_EN_0_FIELD,
717 kMultiBitBool4False);
722 mmio_region_write32(handle->
dev.
base_addr, mp_reg_offset, mp_reg);
730 if (handle == NULL || enabled_out == NULL ||
731 region.
bank >= FLASH_CTRL_PARAM_REG_NUM_BANKS ||
736 ptrdiff_t mp_reg_offset = get_info_region_mp_reg_offset(region);
737 uint32_t mp_reg = mmio_region_read32(handle->
dev.
base_addr, mp_reg_offset);
738 if (bitfield_field32_read(mp_reg, FLASH_CTRL_MP_REGION_CFG_0_EN_0_FIELD) ==
739 kMultiBitBool4True) {
751 if (handle == NULL) {
755 reg = bitfield_field32_write(reg, FLASH_CTRL_DEFAULT_REGION_RD_EN_FIELD,
757 reg = bitfield_field32_write(reg, FLASH_CTRL_DEFAULT_REGION_PROG_EN_FIELD,
759 reg = bitfield_field32_write(reg, FLASH_CTRL_DEFAULT_REGION_ERASE_EN_FIELD,
761 reg = bitfield_field32_write(reg, FLASH_CTRL_DEFAULT_REGION_SCRAMBLE_EN_FIELD,
763 reg = bitfield_field32_write(reg, FLASH_CTRL_DEFAULT_REGION_ECC_EN_FIELD,
765 reg = bitfield_field32_write(reg, FLASH_CTRL_DEFAULT_REGION_HE_EN_FIELD,
768 FLASH_CTRL_DEFAULT_REGION_REG_OFFSET, reg);
776 if (handle == NULL || properties_out == NULL) {
779 const uint32_t reg = mmio_region_read32(handle->
dev.
base_addr,
780 FLASH_CTRL_DEFAULT_REGION_REG_OFFSET);
783 bitfield_field32_read(reg, FLASH_CTRL_DEFAULT_REGION_RD_EN_FIELD),
785 bitfield_field32_read(reg, FLASH_CTRL_DEFAULT_REGION_PROG_EN_FIELD),
787 bitfield_field32_read(reg, FLASH_CTRL_DEFAULT_REGION_ERASE_EN_FIELD),
788 .scramble_en = bitfield_field32_read(
789 reg, FLASH_CTRL_DEFAULT_REGION_SCRAMBLE_EN_FIELD),
791 bitfield_field32_read(reg, FLASH_CTRL_DEFAULT_REGION_ECC_EN_FIELD),
793 bitfield_field32_read(reg, FLASH_CTRL_DEFAULT_REGION_HE_EN_FIELD),
795 *properties_out = properties;
803 const uint32_t page_limit =
804 FLASH_CTRL_PARAM_REG_NUM_BANKS * FLASH_CTRL_PARAM_REG_PAGES_PER_BANK;
805 if (handle == NULL || region >= FLASH_CTRL_PARAM_NUM_REGIONS ||
806 config.
base + config.
size > page_limit) {
812 dif_flash_ctrl_data_region_is_locked(handle, region, &locked));
817 ptrdiff_t mp_reg_offset = get_data_region_mp_reg_offset(region);
818 uint32_t reg = mmio_region_read32(handle->
dev.
base_addr, mp_reg_offset);
819 reg = bitfield_field32_write(reg, FLASH_CTRL_MP_REGION_CFG_0_RD_EN_0_FIELD,
821 reg = bitfield_field32_write(reg, FLASH_CTRL_MP_REGION_CFG_0_PROG_EN_0_FIELD,
823 reg = bitfield_field32_write(reg, FLASH_CTRL_MP_REGION_CFG_0_ERASE_EN_0_FIELD,
825 reg = bitfield_field32_write(reg,
826 FLASH_CTRL_MP_REGION_CFG_0_SCRAMBLE_EN_0_FIELD,
828 reg = bitfield_field32_write(reg, FLASH_CTRL_MP_REGION_CFG_0_ECC_EN_0_FIELD,
830 reg = bitfield_field32_write(reg, FLASH_CTRL_MP_REGION_CFG_0_HE_EN_0_FIELD,
833 mmio_region_write32(handle->
dev.
base_addr, mp_reg_offset, reg);
836 mp_reg_offset = get_data_region_reg_offset(region);
838 reg = bitfield_field32_write(0, FLASH_CTRL_MP_REGION_0_BASE_0_FIELD,
840 reg = bitfield_field32_write(reg, FLASH_CTRL_MP_REGION_0_SIZE_0_FIELD,
842 mmio_region_write32(handle->
dev.
base_addr, mp_reg_offset, reg);
850 if (handle == NULL || config_out == NULL ||
851 region >= FLASH_CTRL_PARAM_NUM_REGIONS) {
855 ptrdiff_t mp_reg_offset = get_data_region_mp_reg_offset(region);
856 uint32_t reg = mmio_region_read32(handle->
dev.
base_addr, mp_reg_offset);
859 bitfield_field32_read(reg, FLASH_CTRL_MP_REGION_CFG_0_RD_EN_0_FIELD);
861 bitfield_field32_read(reg, FLASH_CTRL_MP_REGION_CFG_0_PROG_EN_0_FIELD);
863 bitfield_field32_read(reg, FLASH_CTRL_MP_REGION_CFG_0_ERASE_EN_0_FIELD);
865 reg, FLASH_CTRL_MP_REGION_CFG_0_SCRAMBLE_EN_0_FIELD);
867 bitfield_field32_read(reg, FLASH_CTRL_MP_REGION_CFG_0_ECC_EN_0_FIELD);
869 bitfield_field32_read(reg, FLASH_CTRL_MP_REGION_CFG_0_HE_EN_0_FIELD);
871 mp_reg_offset = get_data_region_reg_offset(region);
872 reg = mmio_region_read32(handle->
dev.
base_addr, mp_reg_offset);
873 config.
base = bitfield_field32_read(reg, FLASH_CTRL_MP_REGION_0_BASE_0_FIELD);
874 config.
size = bitfield_field32_read(reg, FLASH_CTRL_MP_REGION_0_SIZE_0_FIELD);
875 *config_out = config;
883 if (handle == NULL || region.
bank >= FLASH_CTRL_PARAM_REG_NUM_BANKS ||
891 dif_flash_ctrl_info_region_is_locked(handle, region, &locked));
896 ptrdiff_t mp_reg_offset = get_info_region_mp_reg_offset(region);
897 uint32_t reg = mmio_region_read32(handle->
dev.
base_addr, mp_reg_offset);
898 reg = bitfield_field32_write(reg, FLASH_CTRL_MP_REGION_CFG_0_RD_EN_0_FIELD,
900 reg = bitfield_field32_write(reg, FLASH_CTRL_MP_REGION_CFG_0_PROG_EN_0_FIELD,
902 reg = bitfield_field32_write(reg, FLASH_CTRL_MP_REGION_CFG_0_ERASE_EN_0_FIELD,
904 reg = bitfield_field32_write(reg,
905 FLASH_CTRL_MP_REGION_CFG_0_SCRAMBLE_EN_0_FIELD,
907 reg = bitfield_field32_write(reg, FLASH_CTRL_MP_REGION_CFG_0_ECC_EN_0_FIELD,
909 reg = bitfield_field32_write(reg, FLASH_CTRL_MP_REGION_CFG_0_HE_EN_0_FIELD,
911 mmio_region_write32(handle->
dev.
base_addr, mp_reg_offset, reg);
919 if (handle == NULL || properties_out == NULL ||
920 region.
bank >= FLASH_CTRL_PARAM_REG_NUM_BANKS ||
926 ptrdiff_t mp_reg_offset = get_info_region_mp_reg_offset(region);
927 const uint32_t reg = mmio_region_read32(handle->
dev.
base_addr, mp_reg_offset);
929 properties.
rd_en = bitfield_field32_read(
930 reg, FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_RD_EN_0_FIELD);
931 properties.
prog_en = bitfield_field32_read(
932 reg, FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_PROG_EN_0_FIELD);
933 properties.
erase_en = bitfield_field32_read(
934 reg, FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_ERASE_EN_0_FIELD);
936 reg, FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_SCRAMBLE_EN_0_FIELD);
937 properties.
ecc_en = bitfield_field32_read(
938 reg, FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_ECC_EN_0_FIELD);
940 reg, FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_HE_EN_0_FIELD);
941 *properties_out = properties;
948 if (handle == NULL || region >= FLASH_CTRL_PARAM_NUM_REGIONS) {
954 dif_flash_ctrl_data_region_is_locked(handle, region, &locked));
959 ptrdiff_t lock_reg_offset = get_data_region_lock_reg_offset(region);
960 uint32_t reg = bitfield_bit32_write(
961 0, FLASH_CTRL_REGION_CFG_REGWEN_0_REGION_0_BIT,
false);
962 mmio_region_write32(handle->
dev.
base_addr, lock_reg_offset, reg);
969 if (handle == NULL || region.
bank >= FLASH_CTRL_PARAM_REG_NUM_BANKS ||
977 dif_flash_ctrl_info_region_is_locked(handle, region, &locked));
982 ptrdiff_t lock_reg_offset = get_info_region_lock_reg_offset(region);
983 uint32_t reg = bitfield_bit32_write(
984 0, FLASH_CTRL_BANK0_INFO0_REGWEN_0_REGION_0_BIT,
false);
985 mmio_region_write32(handle->
dev.
base_addr, lock_reg_offset, reg);
992 if (handle == NULL || locked_out == NULL ||
993 region >= FLASH_CTRL_PARAM_NUM_REGIONS) {
996 ptrdiff_t lock_reg_offset = get_data_region_lock_reg_offset(region);
997 uint32_t reg = mmio_region_read32(handle->
dev.
base_addr, lock_reg_offset);
999 !bitfield_bit32_read(reg, FLASH_CTRL_REGION_CFG_REGWEN_0_REGION_0_BIT);
1007 if (handle == NULL || locked_out == NULL ||
1008 region.
bank >= FLASH_CTRL_PARAM_REG_NUM_BANKS ||
1014 ptrdiff_t lock_reg_offset = get_info_region_lock_reg_offset(region);
1015 uint32_t reg = mmio_region_read32(handle->
dev.
base_addr, lock_reg_offset);
1017 !bitfield_bit32_read(reg, FLASH_CTRL_BANK0_INFO0_REGWEN_0_REGION_0_BIT);
1024 if (handle == NULL || bank >= FLASH_CTRL_PARAM_REG_NUM_BANKS) {
1030 dif_flash_ctrl_bank_configuration_is_locked(handle, &locked));
1036 uint32_t value = mmio_region_read32(
1037 handle->
dev.
base_addr, FLASH_CTRL_MP_BANK_CFG_SHADOWED_REG_OFFSET);
1040 value = bitfield_bit32_write(value, index,
true);
1043 value = bitfield_bit32_write(value, index,
false);
1048 mmio_region_write32_shadowed(
1049 handle->
dev.
base_addr, FLASH_CTRL_MP_BANK_CFG_SHADOWED_REG_OFFSET, value);
1109 if (handle == NULL || level > FLASH_CTRL_FIFO_LVL_PROG_MASK) {
1113 mmio_region_read32(handle->
dev.
base_addr, FLASH_CTRL_FIFO_LVL_REG_OFFSET);
1114 reg = bitfield_field32_write(reg, FLASH_CTRL_FIFO_LVL_PROG_FIELD, level);
1115 mmio_region_write32(handle->
dev.
base_addr, FLASH_CTRL_FIFO_LVL_REG_OFFSET,
1123 if (handle == NULL || level > FLASH_CTRL_FIFO_LVL_RD_MASK) {
1127 mmio_region_read32(handle->
dev.
base_addr, FLASH_CTRL_FIFO_LVL_REG_OFFSET);
1128 reg = bitfield_field32_write(reg, FLASH_CTRL_FIFO_LVL_RD_FIELD, level);
1129 mmio_region_write32(handle->
dev.
base_addr, FLASH_CTRL_FIFO_LVL_REG_OFFSET,
1137 uint32_t *read_out) {
1138 if (handle == NULL) {
1141 const uint32_t reg =
1142 mmio_region_read32(handle->
dev.
base_addr, FLASH_CTRL_FIFO_LVL_REG_OFFSET);
1143 if (prog_out != NULL) {
1144 *prog_out = bitfield_field32_read(reg, FLASH_CTRL_FIFO_LVL_PROG_FIELD);
1146 if (read_out != NULL) {
1147 *read_out = bitfield_field32_read(reg, FLASH_CTRL_FIFO_LVL_RD_FIELD);
1155 if (handle == NULL) {
1158 uint32_t reg = bitfield_bit32_write(0, FLASH_CTRL_FIFO_RST_EN_BIT,
true);
1159 mmio_region_write32(handle->
dev.
base_addr, FLASH_CTRL_FIFO_RST_REG_OFFSET,
1161 reg = bitfield_bit32_write(0, FLASH_CTRL_FIFO_RST_EN_BIT,
false);
1162 mmio_region_write32(handle->
dev.
base_addr, FLASH_CTRL_FIFO_RST_REG_OFFSET,
1169 dif_flash_ctrl_faults_t *faults_out) {
1170 if (handle == NULL || faults_out == NULL) {
1173 uint32_t reg = mmio_region_read32(handle->
dev.
base_addr,
1174 FLASH_CTRL_FAULT_STATUS_REG_OFFSET);
1175 dif_flash_ctrl_faults_t faults;
1177 bitfield_bit32_read(reg, FLASH_CTRL_FAULT_STATUS_MP_ERR_BIT);
1179 bitfield_bit32_read(reg, FLASH_CTRL_FAULT_STATUS_RD_ERR_BIT);
1181 bitfield_bit32_read(reg, FLASH_CTRL_FAULT_STATUS_PROG_WIN_ERR_BIT);
1183 bitfield_bit32_read(reg, FLASH_CTRL_FAULT_STATUS_PROG_TYPE_ERR_BIT);
1185 bitfield_bit32_read(reg, FLASH_CTRL_FAULT_STATUS_HOST_GNT_ERR_BIT);
1187 FLASH_CTRL_STD_FAULT_STATUS_REG_OFFSET);
1189 bitfield_bit32_read(reg, FLASH_CTRL_STD_FAULT_STATUS_REG_INTG_ERR_BIT);
1191 bitfield_bit32_read(reg, FLASH_CTRL_STD_FAULT_STATUS_PROG_INTG_ERR_BIT);
1193 bitfield_bit32_read(reg, FLASH_CTRL_STD_FAULT_STATUS_LCMGR_ERR_BIT);
1195 bitfield_bit32_read(reg, FLASH_CTRL_STD_FAULT_STATUS_STORAGE_ERR_BIT);
1196 *faults_out = faults;
1203 dif_flash_ctrl_ecc_errors_t *errors_out) {
1204 if (handle == NULL || errors_out == NULL ||
1205 bank > FLASH_CTRL_PARAM_REG_NUM_BANKS) {
1209 ptrdiff_t last_addr_reg_offset;
1210#if FLASH_CTRL_PARAM_REG_NUM_BANKS > 2
1211#error "Revise this function to handle more banks."
1215 FLASH_CTRL_ECC_SINGLE_ERR_CNT_ECC_SINGLE_ERR_CNT_0_FIELD;
1216 last_addr_reg_offset = FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_REG_OFFSET;
1219 FLASH_CTRL_ECC_SINGLE_ERR_CNT_ECC_SINGLE_ERR_CNT_1_FIELD;
1220 last_addr_reg_offset = FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_REG_OFFSET;
1223 uint32_t reg = mmio_region_read32(handle->
dev.
base_addr,
1224 FLASH_CTRL_ECC_SINGLE_ERR_CNT_REG_OFFSET);
1226 bitfield_field32_read(reg, error_count_field);
1228 mmio_region_read32(handle->
dev.
base_addr, last_addr_reg_offset);
1235 dif_flash_ctrl_phy_status_t *status_out) {
1236 if (handle == NULL || status_out == NULL) {
1239 const uint32_t reg = mmio_region_read32(handle->
dev.
base_addr,
1240 FLASH_CTRL_PHY_STATUS_REG_OFFSET);
1241 dif_flash_ctrl_phy_status_t
status = {
1243 bitfield_bit32_read(reg, FLASH_CTRL_PHY_STATUS_INIT_WIP_BIT),
1244 .prog_normal_available =
1245 bitfield_bit32_read(reg, FLASH_CTRL_PHY_STATUS_PROG_NORMAL_AVAIL_BIT),
1246 .prog_repair_available =
1247 bitfield_bit32_read(reg, FLASH_CTRL_PHY_STATUS_PROG_REPAIR_AVAIL_BIT),