Software APIs
dif_flash_ctrl.c
1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4
5#include "sw/device/lib/dif/dif_flash_ctrl.h"
6
7#include <assert.h>
8
9#include "sw/device/lib/base/bitfield.h"
10#include "sw/device/lib/base/macros.h"
11#include "sw/device/lib/base/multibits.h"
12
13// Generated.
14#include "hw/top/flash_ctrl_regs.h"
15
16/**
17 * Helper function to get the offset of a data region's configuration register.
18 * Does not check that the region actually exists, which is deferred to callers.
19 * Since data region registers are split into two (one containing properties the
20 * other containing address info), there are two helper functions below.
21 *
22 * @param region The data region's index.
23 * @return The offset from the flash controller's base address where the region
24 * configuration register is located.
25 */
26OT_WARN_UNUSED_RESULT
27static ptrdiff_t get_data_region_mp_reg_offset(uint32_t region) {
28 return FLASH_CTRL_MP_REGION_CFG_0_REG_OFFSET +
29 (ptrdiff_t)region * (ptrdiff_t)sizeof(uint32_t);
30}
31
32OT_WARN_UNUSED_RESULT
33static ptrdiff_t get_data_region_reg_offset(uint32_t region) {
34 return FLASH_CTRL_MP_REGION_0_REG_OFFSET +
35 (ptrdiff_t)region * (ptrdiff_t)sizeof(uint32_t);
36}
37
38OT_WARN_UNUSED_RESULT
39static ptrdiff_t get_data_region_lock_reg_offset(uint32_t region) {
40 return FLASH_CTRL_REGION_CFG_REGWEN_0_REG_OFFSET +
41 (ptrdiff_t)region * (ptrdiff_t)sizeof(uint32_t);
42}
43
44// The info region register tables have contents that depend on a particular
45// number of flash banks. If that number changes, the tables will need to be
46// updated.
47static_assert(FLASH_CTRL_PARAM_REG_NUM_BANKS == 2,
48 "Please update the info region register tables.");
49
50// TODO: Can we populate the number of info partition types in the header too?
51// The number of different types of info regions.
52#ifndef FLASH_CTRL_NUM_INFO_TYPES
53#define FLASH_CTRL_NUM_INFO_TYPES 3
54#endif
55
56// A more convenient mapping between the info regions and their configuration
57// register offset.
58static const ptrdiff_t
59 kInfoConfigOffsets[FLASH_CTRL_NUM_INFO_TYPES]
60 [FLASH_CTRL_PARAM_REG_NUM_BANKS] = {
61 {
62 FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_REG_OFFSET,
63 FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_REG_OFFSET,
64 },
65 {
66 FLASH_CTRL_BANK0_INFO1_PAGE_CFG_REG_OFFSET,
67 FLASH_CTRL_BANK1_INFO1_PAGE_CFG_REG_OFFSET,
68 },
69 {
70 FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_REG_OFFSET,
71 FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_REG_OFFSET,
72 },
73};
74
75static const ptrdiff_t
76 kInfoLockOffsets[FLASH_CTRL_NUM_INFO_TYPES]
77 [FLASH_CTRL_PARAM_REG_NUM_BANKS] = {
78 {
79 FLASH_CTRL_BANK0_INFO0_REGWEN_0_REG_OFFSET,
80 FLASH_CTRL_BANK1_INFO0_REGWEN_0_REG_OFFSET,
81 },
82 {
83 FLASH_CTRL_BANK0_INFO1_REGWEN_REG_OFFSET,
84 FLASH_CTRL_BANK1_INFO1_REGWEN_REG_OFFSET,
85 },
86 {
87 FLASH_CTRL_BANK0_INFO2_REGWEN_0_REG_OFFSET,
88 FLASH_CTRL_BANK1_INFO2_REGWEN_0_REG_OFFSET,
89 },
90};
91
92static const uint32_t kNumInfoPagesPerBank[FLASH_CTRL_NUM_INFO_TYPES] = {
93 FLASH_CTRL_PARAM_NUM_INFOS0,
94 FLASH_CTRL_PARAM_NUM_INFOS1,
95 FLASH_CTRL_PARAM_NUM_INFOS2,
96};
97
98/**
99 * Helper function to get the offset of an info region's configuration register.
100 * Does not check that the region actually exists, which is deferred to callers.
101 *
102 * @param region The info region's description.
103 * @return The offset from the flash controller's base address where the region
104 * configuration register is located.
105 */
106OT_WARN_UNUSED_RESULT
107static ptrdiff_t get_info_region_mp_reg_offset(
108 dif_flash_ctrl_info_region_t region) {
109 return kInfoConfigOffsets[region.partition_id][region.bank] +
110 (ptrdiff_t)region.page * (ptrdiff_t)sizeof(uint32_t);
111}
112
113OT_WARN_UNUSED_RESULT
114static ptrdiff_t get_info_region_lock_reg_offset(
115 dif_flash_ctrl_info_region_t region) {
116 return kInfoLockOffsets[region.partition_id][region.bank] +
117 (ptrdiff_t)region.page * (ptrdiff_t)sizeof(uint32_t);
118}
119
120OT_WARN_UNUSED_RESULT
121dif_result_t dif_flash_ctrl_init_state(dif_flash_ctrl_state_t *handle,
122 mmio_region_t base_addr) {
123 if (handle == NULL) {
124 return kDifBadArg;
125 }
126 dif_result_t result = dif_flash_ctrl_init(base_addr, &handle->dev);
127 if (result != kDifOk) {
128 return result;
129 }
130 handle->words_remaining = 0;
131 handle->transaction_pending = false;
132 return kDifOk;
133}
134
135dif_result_t dif_flash_ctrl_init_state_from_dt(dif_flash_ctrl_state_t *handle,
136 dt_flash_ctrl_t dt) {
137 return dif_flash_ctrl_init_state(
138 handle, mmio_region_from_addr(dt_flash_ctrl_primary_reg_block(dt)));
139}
140
141OT_WARN_UNUSED_RESULT
142dif_flash_ctrl_device_info_t dif_flash_ctrl_get_device_info(void) {
143 const dif_flash_ctrl_device_info_t info = {
144 .num_banks = FLASH_CTRL_PARAM_REG_NUM_BANKS,
145 .bytes_per_word = FLASH_CTRL_PARAM_BYTES_PER_WORD,
146 .bytes_per_page = FLASH_CTRL_PARAM_BYTES_PER_PAGE,
147 .data_pages = FLASH_CTRL_PARAM_REG_PAGES_PER_BANK,
148 .info0_pages = FLASH_CTRL_PARAM_NUM_INFOS0,
149 .info1_pages = FLASH_CTRL_PARAM_NUM_INFOS1,
150 .info2_pages = FLASH_CTRL_PARAM_NUM_INFOS2,
151 };
152 return info;
153}
154
155OT_WARN_UNUSED_RESULT
156dif_result_t dif_flash_ctrl_set_flash_enablement(dif_flash_ctrl_state_t *handle,
157 dif_toggle_t enable) {
158 enum multi_bit_bool disable_flash;
159 if (handle == NULL) {
160 return kDifBadArg;
161 }
162 // TODO: Get agreement on how multi-bit bools are used. This register has
163 // negative logic for dif_toggle_t and treats "invalid" values differently
164 // from the typical "true => enable" registers.
165 switch (enable) {
166 case kDifToggleEnabled:
167 disable_flash = kMultiBitBool4False;
168 break;
169 case kDifToggleDisabled:
170 disable_flash = kMultiBitBool4True;
171 break;
172 default:
173 return kDifBadArg;
174 }
175 mmio_region_write32(handle->dev.base_addr, FLASH_CTRL_DIS_REG_OFFSET,
176 disable_flash);
177 return kDifOk;
178}
179
180OT_WARN_UNUSED_RESULT
181dif_result_t dif_flash_ctrl_get_flash_enablement(
182 const dif_flash_ctrl_state_t *handle, dif_toggle_t *enabled_out) {
183 if (handle == NULL || enabled_out == NULL) {
184 return kDifBadArg;
185 }
186 uint32_t reg =
187 mmio_region_read32(handle->dev.base_addr, FLASH_CTRL_DIS_REG_OFFSET);
188 enum multi_bit_bool flash_disabled =
189 bitfield_field32_read(reg, FLASH_CTRL_DIS_VAL_FIELD);
190 // TODO: As above, determine if there is a convention for multi-bit bools
191 // where "true => disable", and consider creating a common function to handle
192 // conversion.
193 if (flash_disabled == kMultiBitBool4False) {
194 *enabled_out = kDifToggleEnabled;
195 } else {
196 *enabled_out = kDifToggleDisabled;
197 }
198 return kDifOk;
199}
200
201OT_WARN_UNUSED_RESULT
202dif_result_t dif_flash_ctrl_set_exec_enablement(dif_flash_ctrl_state_t *handle,
203 dif_toggle_t enable) {
204 uint32_t value;
205 if (handle == NULL) {
206 return kDifBadArg;
207 }
208 switch (enable) {
209 case kDifToggleEnabled:
210 value = FLASH_CTRL_PARAM_EXEC_EN;
211 break;
212 case kDifToggleDisabled:
213 value = 0;
214 break;
215 default:
216 return kDifBadArg;
217 }
218 mmio_region_write32(handle->dev.base_addr, FLASH_CTRL_EXEC_REG_OFFSET, value);
219 return kDifOk;
220}
221
222OT_WARN_UNUSED_RESULT
223dif_result_t dif_flash_ctrl_get_exec_enablement(
224 const dif_flash_ctrl_state_t *handle, dif_toggle_t *enabled_out) {
225 if (handle == NULL || enabled_out == NULL) {
226 return kDifBadArg;
227 }
228 uint32_t reg =
229 mmio_region_read32(handle->dev.base_addr, FLASH_CTRL_EXEC_REG_OFFSET);
230 if (reg == FLASH_CTRL_PARAM_EXEC_EN) {
231 *enabled_out = kDifToggleEnabled;
232 } else {
233 *enabled_out = kDifToggleDisabled;
234 }
235 return kDifOk;
236}
237
238OT_WARN_UNUSED_RESULT
239dif_result_t dif_flash_ctrl_start_controller_init(
240 dif_flash_ctrl_state_t *handle) {
241 if (handle == NULL) {
242 return kDifBadArg;
243 }
244 const uint32_t reg =
245 mmio_region_read32(handle->dev.base_addr, FLASH_CTRL_INIT_REG_OFFSET);
246 if (bitfield_bit32_read(reg, FLASH_CTRL_INIT_VAL_BIT)) {
247 // Controller initialization may only be requested once.
248 return kDifError;
249 }
250 uint32_t value = bitfield_bit32_write(0, FLASH_CTRL_INIT_VAL_BIT, true);
251 mmio_region_write32(handle->dev.base_addr, FLASH_CTRL_INIT_REG_OFFSET, value);
252 return kDifOk;
253}
254
255OT_WARN_UNUSED_RESULT
256dif_result_t dif_flash_ctrl_get_status(const dif_flash_ctrl_state_t *handle,
257 dif_flash_ctrl_status_t *status_out) {
258 if (handle == NULL || status_out == NULL) {
259 return kDifBadArg;
260 }
261 uint32_t reg =
262 mmio_region_read32(handle->dev.base_addr, FLASH_CTRL_STATUS_REG_OFFSET);
263 dif_flash_ctrl_status_t status = {
264 .read_fifo_full = bitfield_bit32_read(reg, FLASH_CTRL_STATUS_RD_FULL_BIT),
265 .read_fifo_empty =
266 bitfield_bit32_read(reg, FLASH_CTRL_STATUS_RD_EMPTY_BIT),
267 .prog_fifo_full =
268 bitfield_bit32_read(reg, FLASH_CTRL_STATUS_PROG_FULL_BIT),
269 .prog_fifo_empty =
270 bitfield_bit32_read(reg, FLASH_CTRL_STATUS_PROG_EMPTY_BIT),
271 .controller_init_wip =
272 bitfield_bit32_read(reg, FLASH_CTRL_STATUS_INIT_WIP_BIT),
273 .controller_initialized =
274 bitfield_bit32_read(reg, FLASH_CTRL_STATUS_INITIALIZED_BIT),
275 };
276 *status_out = status;
277 return kDifOk;
278}
279
280OT_WARN_UNUSED_RESULT
281dif_result_t dif_flash_ctrl_get_allowed_prog_types(
282 const dif_flash_ctrl_state_t *handle,
283 dif_flash_ctrl_prog_capabilities_t *allowed_types_out) {
284 if (handle == NULL || allowed_types_out == NULL) {
285 return kDifBadArg;
286 }
287
288 uint32_t reg = mmio_region_read32(handle->dev.base_addr,
289 FLASH_CTRL_PROG_TYPE_EN_REG_OFFSET);
290 dif_flash_ctrl_prog_capabilities_t allowed_types = {
291 .normal_prog_type =
292 bitfield_bit32_read(reg, FLASH_CTRL_PROG_TYPE_EN_NORMAL_BIT),
293 .repair_prog_type =
294 bitfield_bit32_read(reg, FLASH_CTRL_PROG_TYPE_EN_REPAIR_BIT),
295 };
296 *allowed_types_out = allowed_types;
297 return kDifOk;
298}
299
300OT_WARN_UNUSED_RESULT
301dif_result_t dif_flash_ctrl_disallow_prog_types(
302 dif_flash_ctrl_state_t *handle,
303 dif_flash_ctrl_prog_capabilities_t types_to_disallow) {
304 if (handle == NULL) {
305 return kDifBadArg;
306 }
307
308 uint32_t ctrl_regwen = mmio_region_read32(handle->dev.base_addr,
309 FLASH_CTRL_CTRL_REGWEN_REG_OFFSET);
310 if (!bitfield_bit32_read(ctrl_regwen, FLASH_CTRL_CTRL_REGWEN_EN_BIT)) {
311 return kDifUnavailable;
312 }
313
314 uint32_t reg = 0;
315 reg = bitfield_bit32_write(reg, FLASH_CTRL_PROG_TYPE_EN_NORMAL_BIT,
316 !types_to_disallow.normal_prog_type);
317 reg = bitfield_bit32_write(reg, FLASH_CTRL_PROG_TYPE_EN_REPAIR_BIT,
318 !types_to_disallow.repair_prog_type);
319 mmio_region_write32(handle->dev.base_addr, FLASH_CTRL_PROG_TYPE_EN_REG_OFFSET,
320 reg);
321 return kDifOk;
322}
323
324OT_WARN_UNUSED_RESULT
325dif_result_t dif_flash_ctrl_start_unsafe(
326 dif_flash_ctrl_state_t *handle, dif_flash_ctrl_transaction_t transaction) {
327 if (handle == NULL) {
328 return kDifBadArg;
329 }
330 uint32_t ctrl_regwen = mmio_region_read32(handle->dev.base_addr,
331 FLASH_CTRL_CTRL_REGWEN_REG_OFFSET);
332 if (!bitfield_bit32_read(ctrl_regwen, FLASH_CTRL_CTRL_REGWEN_EN_BIT)) {
333 return kDifUnavailable;
334 }
335
336 uint32_t control_reg = bitfield_field32_write(0, FLASH_CTRL_CONTROL_NUM_FIELD,
337 transaction.word_count - 1);
338 switch (transaction.op) {
339 case kDifFlashCtrlOpRead:
340 control_reg =
341 bitfield_field32_write(control_reg, FLASH_CTRL_CONTROL_OP_FIELD,
342 FLASH_CTRL_CONTROL_OP_VALUE_READ);
343 break;
344 case kDifFlashCtrlOpProgram:
345 control_reg =
346 bitfield_field32_write(control_reg, FLASH_CTRL_CONTROL_OP_FIELD,
347 FLASH_CTRL_CONTROL_OP_VALUE_PROG);
348 control_reg = bitfield_bit32_write(
349 control_reg, FLASH_CTRL_CONTROL_PROG_SEL_BIT, false);
350 break;
351 case kDifFlashCtrlOpProgramRepair:
352 control_reg =
353 bitfield_field32_write(control_reg, FLASH_CTRL_CONTROL_OP_FIELD,
354 FLASH_CTRL_CONTROL_OP_VALUE_PROG);
355 control_reg = bitfield_bit32_write(control_reg,
356 FLASH_CTRL_CONTROL_PROG_SEL_BIT, true);
357 break;
358 case kDifFlashCtrlOpPageErase:
359 control_reg =
360 bitfield_field32_write(control_reg, FLASH_CTRL_CONTROL_OP_FIELD,
361 FLASH_CTRL_CONTROL_OP_VALUE_ERASE);
362 control_reg = bitfield_bit32_write(
363 control_reg, FLASH_CTRL_CONTROL_ERASE_SEL_BIT, false);
364 break;
365 case kDifFlashCtrlOpBankErase:
366 control_reg =
367 bitfield_field32_write(control_reg, FLASH_CTRL_CONTROL_OP_FIELD,
368 FLASH_CTRL_CONTROL_OP_VALUE_ERASE);
369 control_reg = bitfield_bit32_write(
370 control_reg, FLASH_CTRL_CONTROL_ERASE_SEL_BIT, true);
371 break;
372 default:
373 return kDifBadArg;
374 }
375
376 switch (transaction.partition_type) {
377 case kDifFlashCtrlPartitionTypeData:
378 control_reg = bitfield_bit32_write(
379 control_reg, FLASH_CTRL_CONTROL_PARTITION_SEL_BIT, false);
380 break;
381 case kDifFlashCtrlPartitionTypeInfo:
382 control_reg =
383 bitfield_field32_write(control_reg, FLASH_CTRL_CONTROL_INFO_SEL_FIELD,
384 transaction.partition_id);
385 control_reg = bitfield_bit32_write(
386 control_reg, FLASH_CTRL_CONTROL_PARTITION_SEL_BIT, true);
387 break;
388 default:
389 return kDifBadArg;
390 }
391
392 mmio_region_write32(handle->dev.base_addr, FLASH_CTRL_CONTROL_REG_OFFSET,
393 control_reg);
394 mmio_region_write32(handle->dev.base_addr, FLASH_CTRL_ADDR_REG_OFFSET,
395 transaction.byte_address);
396 mmio_region_write32(handle->dev.base_addr, FLASH_CTRL_CONTROL_REG_OFFSET,
397 control_reg | (1u << FLASH_CTRL_CONTROL_START_BIT));
398 if (transaction.op == kDifFlashCtrlOpPageErase ||
399 transaction.op == kDifFlashCtrlOpBankErase) {
400 // Erase operations don't use the FIFO
401 handle->words_remaining = 0;
402 } else {
403 handle->words_remaining = transaction.word_count;
404 }
405 handle->transaction_pending = true;
406 return kDifOk;
407}
408
409OT_WARN_UNUSED_RESULT
410dif_result_t dif_flash_ctrl_start(dif_flash_ctrl_state_t *handle,
411 dif_flash_ctrl_transaction_t transaction) {
412 if (handle == NULL) {
413 return kDifBadArg;
414 }
415
416 if (transaction.partition_type == kDifFlashCtrlPartitionTypeInfo &&
417 transaction.partition_id >= FLASH_CTRL_NUM_INFO_TYPES) {
418 return kDifBadArg;
419 }
420
421 const uint32_t max_word_count = FLASH_CTRL_CONTROL_NUM_MASK;
422 if ((transaction.op != kDifFlashCtrlOpPageErase) &&
423 (transaction.op != kDifFlashCtrlOpBankErase)) {
424 if (transaction.word_count - 1 > max_word_count ||
425 transaction.word_count == 0) {
426 return kDifBadArg;
427 }
428 }
429
430 if (handle->transaction_pending) {
431 return kDifUnavailable;
432 }
433
434 // Disallow starting a new transaction if the FIFOs haven't been emptied yet.
435 dif_flash_ctrl_status_t status;
436 dif_result_t result = dif_flash_ctrl_get_status(handle, &status);
437 if (result != kDifOk) {
438 return result;
439 }
440 if (!status.read_fifo_empty || !status.prog_fifo_empty) {
441 return kDifIpFifoFull;
442 }
443
444 return dif_flash_ctrl_start_unsafe(handle, transaction);
445}
446
447OT_WARN_UNUSED_RESULT
448dif_result_t dif_flash_ctrl_suspend_erase(dif_flash_ctrl_state_t *handle) {
449 if (handle == NULL) {
450 return kDifBadArg;
451 }
452 uint32_t reg =
453 bitfield_bit32_write(0, FLASH_CTRL_ERASE_SUSPEND_REQ_BIT, true);
454 mmio_region_write32(handle->dev.base_addr,
455 FLASH_CTRL_ERASE_SUSPEND_REG_OFFSET, reg);
456 return kDifOk;
457}
458
459OT_WARN_UNUSED_RESULT
460dif_result_t dif_flash_ctrl_get_erase_suspend_status(
461 dif_flash_ctrl_state_t *handle, bool *request_pending_out) {
462 if (handle == NULL || request_pending_out == NULL) {
463 return kDifBadArg;
464 }
465 uint32_t reg = mmio_region_read32(handle->dev.base_addr,
466 FLASH_CTRL_ERASE_SUSPEND_REG_OFFSET);
467 *request_pending_out =
468 bitfield_bit32_read(reg, FLASH_CTRL_ERASE_SUSPEND_REQ_BIT);
469 return kDifOk;
470}
471
472// TODO(awill): Function to report the maximum FIFO size?
473
474OT_WARN_UNUSED_RESULT
475dif_result_t dif_flash_ctrl_prog_fifo_push_unsafe(
476 dif_flash_ctrl_state_t *handle, uint32_t word_count, const uint32_t *data) {
477 if (handle == NULL || data == NULL) {
478 return kDifBadArg;
479 }
480 uint32_t written = 0;
481 while (written < word_count) {
482 mmio_region_write32(handle->dev.base_addr, FLASH_CTRL_PROG_FIFO_REG_OFFSET,
483 data[written]);
484 ++written;
485 }
486 handle->words_remaining -= written;
487 return kDifOk;
488}
489
490OT_WARN_UNUSED_RESULT
491dif_result_t dif_flash_ctrl_prog_fifo_push(dif_flash_ctrl_state_t *handle,
492 uint32_t word_count,
493 const uint32_t *data) {
494 if (handle == NULL || data == NULL) {
495 return kDifBadArg;
496 }
497 if (!handle->transaction_pending) {
498 return kDifError;
499 }
500 if (handle->words_remaining < word_count) {
501 return kDifBadArg;
502 }
503 const uint32_t control_reg =
504 mmio_region_read32(handle->dev.base_addr, FLASH_CTRL_CONTROL_REG_OFFSET);
505 const uint32_t op =
506 bitfield_field32_read(control_reg, FLASH_CTRL_CONTROL_OP_FIELD);
507 if (op != FLASH_CTRL_CONTROL_OP_VALUE_PROG) {
508 return kDifError;
509 }
510 return dif_flash_ctrl_prog_fifo_push_unsafe(handle, word_count, data);
511}
512
513OT_WARN_UNUSED_RESULT
514dif_result_t dif_flash_ctrl_read_fifo_pop_unsafe(dif_flash_ctrl_state_t *handle,
515 uint32_t word_count,
516 uint32_t *data) {
517 if (handle == NULL || data == NULL) {
518 return kDifBadArg;
519 }
520 uint32_t read = 0;
521 while (read < word_count) {
522 data[read] = mmio_region_read32(handle->dev.base_addr,
523 FLASH_CTRL_RD_FIFO_REG_OFFSET);
524 ++read;
525 }
526 handle->words_remaining -= read;
527 return kDifOk;
528}
529
530OT_WARN_UNUSED_RESULT
531dif_result_t dif_flash_ctrl_read_fifo_pop(dif_flash_ctrl_state_t *handle,
532 uint32_t word_count, uint32_t *data) {
533 if (handle == NULL || data == NULL) {
534 return kDifBadArg;
535 }
536 if (!handle->transaction_pending) {
537 return kDifError;
538 }
539 if (handle->words_remaining < word_count) {
540 return kDifBadArg;
541 }
542 const uint32_t control_reg =
543 mmio_region_read32(handle->dev.base_addr, FLASH_CTRL_CONTROL_REG_OFFSET);
544 const uint32_t op =
545 bitfield_field32_read(control_reg, FLASH_CTRL_CONTROL_OP_FIELD);
546 if (op != FLASH_CTRL_CONTROL_OP_VALUE_READ) {
547 return kDifError;
548 }
549 return dif_flash_ctrl_read_fifo_pop_unsafe(handle, word_count, data);
550}
551
552OT_WARN_UNUSED_RESULT
553dif_result_t dif_flash_ctrl_get_error_codes(
554 const dif_flash_ctrl_state_t *handle,
555 dif_flash_ctrl_error_t *error_code_out) {
556 if (handle == NULL || error_code_out == NULL) {
557 return kDifBadArg;
558 }
559 const uint32_t code_reg =
560 mmio_region_read32(handle->dev.base_addr, FLASH_CTRL_ERR_CODE_REG_OFFSET);
561 dif_flash_ctrl_error_codes_t codes = {
562 .memory_properties_error =
563 bitfield_bit32_read(code_reg, FLASH_CTRL_ERR_CODE_MP_ERR_BIT),
564 .read_error =
565 bitfield_bit32_read(code_reg, FLASH_CTRL_ERR_CODE_RD_ERR_BIT),
566 .prog_window_error =
567 bitfield_bit32_read(code_reg, FLASH_CTRL_ERR_CODE_PROG_WIN_ERR_BIT),
568 .prog_type_error =
569 bitfield_bit32_read(code_reg, FLASH_CTRL_ERR_CODE_PROG_TYPE_ERR_BIT),
570 .shadow_register_error =
571 bitfield_bit32_read(code_reg, FLASH_CTRL_ERR_CODE_UPDATE_ERR_BIT),
572 };
573
574 const uint32_t address_reg =
575 mmio_region_read32(handle->dev.base_addr, FLASH_CTRL_ERR_ADDR_REG_OFFSET);
576 dif_flash_ctrl_error_t error_code = {
577 .address = address_reg,
578 .codes = codes,
579 };
580 *error_code_out = error_code;
581 return kDifOk;
582}
583
584OT_WARN_UNUSED_RESULT
585dif_result_t dif_flash_ctrl_clear_error_codes(
586 dif_flash_ctrl_state_t *handle, dif_flash_ctrl_error_codes_t codes) {
587 if (handle == NULL) {
588 return kDifBadArg;
589 }
590 uint32_t code_reg = 0;
591 code_reg = bitfield_bit32_write(code_reg, FLASH_CTRL_ERR_CODE_MP_ERR_BIT,
592 codes.memory_properties_error);
593 code_reg = bitfield_bit32_write(code_reg, FLASH_CTRL_ERR_CODE_RD_ERR_BIT,
594 codes.read_error);
595 code_reg = bitfield_bit32_write(
596 code_reg, FLASH_CTRL_ERR_CODE_PROG_WIN_ERR_BIT, codes.prog_window_error);
597 code_reg = bitfield_bit32_write(
598 code_reg, FLASH_CTRL_ERR_CODE_PROG_TYPE_ERR_BIT, codes.prog_type_error);
599 code_reg = bitfield_bit32_write(code_reg, FLASH_CTRL_ERR_CODE_UPDATE_ERR_BIT,
600 codes.shadow_register_error);
601 mmio_region_write32(handle->dev.base_addr, FLASH_CTRL_ERR_CODE_REG_OFFSET,
602 code_reg);
603 return kDifOk;
604}
605
606OT_WARN_UNUSED_RESULT
607dif_result_t dif_flash_ctrl_end(dif_flash_ctrl_state_t *handle,
608 dif_flash_ctrl_output_t *out) {
609 if (handle == NULL || out == NULL) {
610 return kDifBadArg;
611 }
612 if (!handle->transaction_pending) {
613 return kDifError;
614 }
615 uint32_t status_reg = mmio_region_read32(handle->dev.base_addr,
616 FLASH_CTRL_OP_STATUS_REG_OFFSET);
617 if (!bitfield_bit32_read(status_reg, FLASH_CTRL_OP_STATUS_DONE_BIT)) {
618 return kDifUnavailable;
619 }
620 if (handle->words_remaining != 0) {
621 return kDifIpFifoFull;
622 }
623 dif_flash_ctrl_error_t error_code_tmp;
624 DIF_RETURN_IF_ERROR(dif_flash_ctrl_get_error_codes(handle, &error_code_tmp));
625 dif_flash_ctrl_output_t output = {
626 .operation_done =
627 bitfield_bit32_read(status_reg, FLASH_CTRL_OP_STATUS_DONE_BIT),
628 .operation_error =
629 bitfield_bit32_read(status_reg, FLASH_CTRL_OP_STATUS_ERR_BIT),
630 .error_code = error_code_tmp};
631 // Clear the operation status
632 mmio_region_write32(handle->dev.base_addr, FLASH_CTRL_OP_STATUS_REG_OFFSET,
633 0);
634 handle->transaction_pending = false;
635 *out = output;
636 return kDifOk;
637}
638
639OT_WARN_UNUSED_RESULT
640dif_result_t dif_flash_ctrl_set_data_region_enablement(
641 dif_flash_ctrl_state_t *handle, uint32_t region, dif_toggle_t enable) {
642 if (handle == NULL || region >= FLASH_CTRL_PARAM_NUM_REGIONS) {
643 return kDifBadArg;
644 }
645
646 bool locked;
647 DIF_RETURN_IF_ERROR(
648 dif_flash_ctrl_data_region_is_locked(handle, region, &locked));
649 if (locked) {
650 return kDifLocked;
651 }
652
653 ptrdiff_t mp_reg_offset = get_data_region_mp_reg_offset(region);
654 uint32_t mp_reg = mmio_region_read32(handle->dev.base_addr, mp_reg_offset);
655 switch (enable) {
656 case kDifToggleEnabled:
657 mp_reg = bitfield_field32_write(
658 mp_reg, FLASH_CTRL_MP_REGION_CFG_0_EN_0_FIELD, kMultiBitBool4True);
659 break;
660 case kDifToggleDisabled:
661 mp_reg = bitfield_field32_write(
662 mp_reg, FLASH_CTRL_MP_REGION_CFG_0_EN_0_FIELD, kMultiBitBool4False);
663 break;
664 default:
665 return kDifBadArg;
666 }
667 mmio_region_write32(handle->dev.base_addr, mp_reg_offset, mp_reg);
668 return kDifOk;
669}
670
671OT_WARN_UNUSED_RESULT
672dif_result_t dif_flash_ctrl_get_data_region_enablement(
673 const dif_flash_ctrl_state_t *handle, uint32_t region,
674 dif_toggle_t *enabled_out) {
675 if (handle == NULL || enabled_out == NULL ||
676 region >= FLASH_CTRL_PARAM_NUM_REGIONS) {
677 return kDifBadArg;
678 }
679 ptrdiff_t mp_reg_offset = get_data_region_mp_reg_offset(region);
680 uint32_t mp_reg = mmio_region_read32(handle->dev.base_addr, mp_reg_offset);
681 if (bitfield_field32_read(mp_reg, FLASH_CTRL_MP_REGION_CFG_0_EN_0_FIELD) ==
682 kMultiBitBool4True) {
683 *enabled_out = kDifToggleEnabled;
684 } else {
685 *enabled_out = kDifToggleDisabled;
686 }
687 return kDifOk;
688}
689
690OT_WARN_UNUSED_RESULT
691dif_result_t dif_flash_ctrl_set_info_region_enablement(
692 dif_flash_ctrl_state_t *handle, dif_flash_ctrl_info_region_t region,
693 dif_toggle_t enable) {
694 if (handle == NULL || region.bank >= FLASH_CTRL_PARAM_REG_NUM_BANKS ||
695 region.partition_id >= FLASH_CTRL_NUM_INFO_TYPES ||
696 region.page > kNumInfoPagesPerBank[region.partition_id]) {
697 return kDifBadArg;
698 }
699 bool locked;
700 DIF_RETURN_IF_ERROR(
701 dif_flash_ctrl_info_region_is_locked(handle, region, &locked));
702 if (locked) {
703 return kDifLocked;
704 }
705
706 ptrdiff_t mp_reg_offset = get_info_region_mp_reg_offset(region);
707 uint32_t mp_reg = mmio_region_read32(handle->dev.base_addr, mp_reg_offset);
708 switch (enable) {
709 case kDifToggleEnabled:
710 mp_reg = bitfield_field32_write(
711 mp_reg, FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_EN_0_FIELD,
712 kMultiBitBool4True);
713 break;
714 case kDifToggleDisabled:
715 mp_reg = bitfield_field32_write(
716 mp_reg, FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_EN_0_FIELD,
717 kMultiBitBool4False);
718 break;
719 default:
720 return kDifBadArg;
721 }
722 mmio_region_write32(handle->dev.base_addr, mp_reg_offset, mp_reg);
723 return kDifOk;
724}
725
726OT_WARN_UNUSED_RESULT
727dif_result_t dif_flash_ctrl_get_info_region_enablement(
728 const dif_flash_ctrl_state_t *handle, dif_flash_ctrl_info_region_t region,
729 dif_toggle_t *enabled_out) {
730 if (handle == NULL || enabled_out == NULL ||
731 region.bank >= FLASH_CTRL_PARAM_REG_NUM_BANKS ||
732 region.partition_id >= FLASH_CTRL_NUM_INFO_TYPES ||
733 region.page > kNumInfoPagesPerBank[region.partition_id]) {
734 return kDifBadArg;
735 }
736 ptrdiff_t mp_reg_offset = get_info_region_mp_reg_offset(region);
737 uint32_t mp_reg = mmio_region_read32(handle->dev.base_addr, mp_reg_offset);
738 if (bitfield_field32_read(mp_reg, FLASH_CTRL_MP_REGION_CFG_0_EN_0_FIELD) ==
739 kMultiBitBool4True) {
740 *enabled_out = kDifToggleEnabled;
741 } else {
742 *enabled_out = kDifToggleDisabled;
743 }
744 return kDifOk;
745}
746
747OT_WARN_UNUSED_RESULT
748dif_result_t dif_flash_ctrl_set_default_region_properties(
749 dif_flash_ctrl_state_t *handle,
750 dif_flash_ctrl_region_properties_t properties) {
751 if (handle == NULL) {
752 return kDifBadArg;
753 }
754 uint32_t reg = 0;
755 reg = bitfield_field32_write(reg, FLASH_CTRL_DEFAULT_REGION_RD_EN_FIELD,
756 properties.rd_en);
757 reg = bitfield_field32_write(reg, FLASH_CTRL_DEFAULT_REGION_PROG_EN_FIELD,
758 properties.prog_en);
759 reg = bitfield_field32_write(reg, FLASH_CTRL_DEFAULT_REGION_ERASE_EN_FIELD,
760 properties.erase_en);
761 reg = bitfield_field32_write(reg, FLASH_CTRL_DEFAULT_REGION_SCRAMBLE_EN_FIELD,
762 properties.scramble_en);
763 reg = bitfield_field32_write(reg, FLASH_CTRL_DEFAULT_REGION_ECC_EN_FIELD,
764 properties.ecc_en);
765 reg = bitfield_field32_write(reg, FLASH_CTRL_DEFAULT_REGION_HE_EN_FIELD,
766 properties.high_endurance_en);
767 mmio_region_write32(handle->dev.base_addr,
768 FLASH_CTRL_DEFAULT_REGION_REG_OFFSET, reg);
769 return kDifOk;
770}
771
772OT_WARN_UNUSED_RESULT
773dif_result_t dif_flash_ctrl_get_default_region_properties(
774 const dif_flash_ctrl_state_t *handle,
775 dif_flash_ctrl_region_properties_t *properties_out) {
776 if (handle == NULL || properties_out == NULL) {
777 return kDifBadArg;
778 }
779 const uint32_t reg = mmio_region_read32(handle->dev.base_addr,
780 FLASH_CTRL_DEFAULT_REGION_REG_OFFSET);
781 dif_flash_ctrl_region_properties_t properties = {
782 .rd_en =
783 bitfield_field32_read(reg, FLASH_CTRL_DEFAULT_REGION_RD_EN_FIELD),
784 .prog_en =
785 bitfield_field32_read(reg, FLASH_CTRL_DEFAULT_REGION_PROG_EN_FIELD),
786 .erase_en =
787 bitfield_field32_read(reg, FLASH_CTRL_DEFAULT_REGION_ERASE_EN_FIELD),
788 .scramble_en = bitfield_field32_read(
789 reg, FLASH_CTRL_DEFAULT_REGION_SCRAMBLE_EN_FIELD),
790 .ecc_en =
791 bitfield_field32_read(reg, FLASH_CTRL_DEFAULT_REGION_ECC_EN_FIELD),
792 .high_endurance_en =
793 bitfield_field32_read(reg, FLASH_CTRL_DEFAULT_REGION_HE_EN_FIELD),
794 };
795 *properties_out = properties;
796 return kDifOk;
797}
798
799OT_WARN_UNUSED_RESULT
800dif_result_t dif_flash_ctrl_set_data_region_properties(
801 dif_flash_ctrl_state_t *handle, uint32_t region,
802 dif_flash_ctrl_data_region_properties_t config) {
803 const uint32_t page_limit =
804 FLASH_CTRL_PARAM_REG_NUM_BANKS * FLASH_CTRL_PARAM_REG_PAGES_PER_BANK;
805 if (handle == NULL || region >= FLASH_CTRL_PARAM_NUM_REGIONS ||
806 config.base + config.size > page_limit) {
807 return kDifBadArg;
808 }
809
810 bool locked;
811 DIF_RETURN_IF_ERROR(
812 dif_flash_ctrl_data_region_is_locked(handle, region, &locked));
813 if (locked) {
814 return kDifLocked;
815 }
816
817 ptrdiff_t mp_reg_offset = get_data_region_mp_reg_offset(region);
818 uint32_t reg = mmio_region_read32(handle->dev.base_addr, mp_reg_offset);
819 reg = bitfield_field32_write(reg, FLASH_CTRL_MP_REGION_CFG_0_RD_EN_0_FIELD,
820 config.properties.rd_en);
821 reg = bitfield_field32_write(reg, FLASH_CTRL_MP_REGION_CFG_0_PROG_EN_0_FIELD,
822 config.properties.prog_en);
823 reg = bitfield_field32_write(reg, FLASH_CTRL_MP_REGION_CFG_0_ERASE_EN_0_FIELD,
824 config.properties.erase_en);
825 reg = bitfield_field32_write(reg,
826 FLASH_CTRL_MP_REGION_CFG_0_SCRAMBLE_EN_0_FIELD,
827 config.properties.scramble_en);
828 reg = bitfield_field32_write(reg, FLASH_CTRL_MP_REGION_CFG_0_ECC_EN_0_FIELD,
829 config.properties.ecc_en);
830 reg = bitfield_field32_write(reg, FLASH_CTRL_MP_REGION_CFG_0_HE_EN_0_FIELD,
831 config.properties.high_endurance_en);
832
833 mmio_region_write32(handle->dev.base_addr, mp_reg_offset, reg);
834
835 // size and base are stored in different registers
836 mp_reg_offset = get_data_region_reg_offset(region);
837
838 reg = bitfield_field32_write(0, FLASH_CTRL_MP_REGION_0_BASE_0_FIELD,
839 config.base);
840 reg = bitfield_field32_write(reg, FLASH_CTRL_MP_REGION_0_SIZE_0_FIELD,
841 config.size);
842 mmio_region_write32(handle->dev.base_addr, mp_reg_offset, reg);
843 return kDifOk;
844}
845
846OT_WARN_UNUSED_RESULT
847dif_result_t dif_flash_ctrl_get_data_region_properties(
848 const dif_flash_ctrl_state_t *handle, uint32_t region,
849 dif_flash_ctrl_data_region_properties_t *config_out) {
850 if (handle == NULL || config_out == NULL ||
851 region >= FLASH_CTRL_PARAM_NUM_REGIONS) {
852 return kDifBadArg;
853 }
854
855 ptrdiff_t mp_reg_offset = get_data_region_mp_reg_offset(region);
856 uint32_t reg = mmio_region_read32(handle->dev.base_addr, mp_reg_offset);
857 dif_flash_ctrl_data_region_properties_t config;
858 config.properties.rd_en =
859 bitfield_field32_read(reg, FLASH_CTRL_MP_REGION_CFG_0_RD_EN_0_FIELD);
860 config.properties.prog_en =
861 bitfield_field32_read(reg, FLASH_CTRL_MP_REGION_CFG_0_PROG_EN_0_FIELD);
862 config.properties.erase_en =
863 bitfield_field32_read(reg, FLASH_CTRL_MP_REGION_CFG_0_ERASE_EN_0_FIELD);
864 config.properties.scramble_en = bitfield_field32_read(
865 reg, FLASH_CTRL_MP_REGION_CFG_0_SCRAMBLE_EN_0_FIELD);
866 config.properties.ecc_en =
867 bitfield_field32_read(reg, FLASH_CTRL_MP_REGION_CFG_0_ECC_EN_0_FIELD);
868 config.properties.high_endurance_en =
869 bitfield_field32_read(reg, FLASH_CTRL_MP_REGION_CFG_0_HE_EN_0_FIELD);
870
871 mp_reg_offset = get_data_region_reg_offset(region);
872 reg = mmio_region_read32(handle->dev.base_addr, mp_reg_offset);
873 config.base = bitfield_field32_read(reg, FLASH_CTRL_MP_REGION_0_BASE_0_FIELD);
874 config.size = bitfield_field32_read(reg, FLASH_CTRL_MP_REGION_0_SIZE_0_FIELD);
875 *config_out = config;
876 return kDifOk;
877}
878
879OT_WARN_UNUSED_RESULT
880dif_result_t dif_flash_ctrl_set_info_region_properties(
881 dif_flash_ctrl_state_t *handle, dif_flash_ctrl_info_region_t region,
882 dif_flash_ctrl_region_properties_t properties) {
883 if (handle == NULL || region.bank >= FLASH_CTRL_PARAM_REG_NUM_BANKS ||
884 region.partition_id >= FLASH_CTRL_NUM_INFO_TYPES ||
885 region.page > kNumInfoPagesPerBank[region.partition_id]) {
886 return kDifBadArg;
887 }
888
889 bool locked;
890 DIF_RETURN_IF_ERROR(
891 dif_flash_ctrl_info_region_is_locked(handle, region, &locked));
892 if (locked) {
893 return kDifLocked;
894 }
895
896 ptrdiff_t mp_reg_offset = get_info_region_mp_reg_offset(region);
897 uint32_t reg = mmio_region_read32(handle->dev.base_addr, mp_reg_offset);
898 reg = bitfield_field32_write(
899 reg, FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_RD_EN_0_FIELD, properties.rd_en);
900 reg = bitfield_field32_write(
901 reg, FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_PROG_EN_0_FIELD,
902 properties.prog_en);
903 reg = bitfield_field32_write(
904 reg, FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_ERASE_EN_0_FIELD,
905 properties.erase_en);
906 reg = bitfield_field32_write(
907 reg, FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_SCRAMBLE_EN_0_FIELD,
908 properties.scramble_en);
909 reg = bitfield_field32_write(
910 reg, FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_ECC_EN_0_FIELD, properties.ecc_en);
911 reg = bitfield_field32_write(reg,
912 FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_HE_EN_0_FIELD,
913 properties.high_endurance_en);
914 mmio_region_write32(handle->dev.base_addr, mp_reg_offset, reg);
915 return kDifOk;
916}
917
918OT_WARN_UNUSED_RESULT
919dif_result_t dif_flash_ctrl_get_info_region_properties(
920 const dif_flash_ctrl_state_t *handle, dif_flash_ctrl_info_region_t region,
921 dif_flash_ctrl_region_properties_t *properties_out) {
922 if (handle == NULL || properties_out == NULL ||
923 region.bank >= FLASH_CTRL_PARAM_REG_NUM_BANKS ||
924 region.partition_id >= FLASH_CTRL_NUM_INFO_TYPES ||
925 region.page > kNumInfoPagesPerBank[region.partition_id]) {
926 return kDifBadArg;
927 }
928
929 ptrdiff_t mp_reg_offset = get_info_region_mp_reg_offset(region);
930 const uint32_t reg = mmio_region_read32(handle->dev.base_addr, mp_reg_offset);
931 dif_flash_ctrl_region_properties_t properties;
932 properties.rd_en = bitfield_field32_read(
933 reg, FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_RD_EN_0_FIELD);
934 properties.prog_en = bitfield_field32_read(
935 reg, FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_PROG_EN_0_FIELD);
936 properties.erase_en = bitfield_field32_read(
937 reg, FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_ERASE_EN_0_FIELD);
938 properties.scramble_en = bitfield_field32_read(
939 reg, FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_SCRAMBLE_EN_0_FIELD);
940 properties.ecc_en = bitfield_field32_read(
941 reg, FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_ECC_EN_0_FIELD);
942 properties.high_endurance_en = bitfield_field32_read(
943 reg, FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_HE_EN_0_FIELD);
944 *properties_out = properties;
945 return kDifOk;
946}
947
948OT_WARN_UNUSED_RESULT
949dif_result_t dif_flash_ctrl_lock_data_region_properties(
950 dif_flash_ctrl_state_t *handle, uint32_t region) {
951 if (handle == NULL || region >= FLASH_CTRL_PARAM_NUM_REGIONS) {
952 return kDifBadArg;
953 }
954
955 bool locked;
956 DIF_RETURN_IF_ERROR(
957 dif_flash_ctrl_data_region_is_locked(handle, region, &locked));
958 if (locked) {
959 return kDifOk;
960 }
961
962 ptrdiff_t lock_reg_offset = get_data_region_lock_reg_offset(region);
963 uint32_t reg = bitfield_bit32_write(
964 0, FLASH_CTRL_REGION_CFG_REGWEN_0_REGION_0_BIT, false);
965 mmio_region_write32(handle->dev.base_addr, lock_reg_offset, reg);
966 return kDifOk;
967}
968
969OT_WARN_UNUSED_RESULT
970dif_result_t dif_flash_ctrl_lock_info_region_properties(
971 dif_flash_ctrl_state_t *handle, dif_flash_ctrl_info_region_t region) {
972 if (handle == NULL || region.bank >= FLASH_CTRL_PARAM_REG_NUM_BANKS ||
973 region.partition_id >= FLASH_CTRL_NUM_INFO_TYPES ||
974 region.page > kNumInfoPagesPerBank[region.partition_id]) {
975 return kDifBadArg;
976 }
977
978 bool locked;
979 DIF_RETURN_IF_ERROR(
980 dif_flash_ctrl_info_region_is_locked(handle, region, &locked));
981 if (locked) {
982 return kDifOk;
983 }
984
985 ptrdiff_t lock_reg_offset = get_info_region_lock_reg_offset(region);
986 uint32_t reg = bitfield_bit32_write(
987 0, FLASH_CTRL_BANK0_INFO0_REGWEN_0_REGION_0_BIT, false);
988 mmio_region_write32(handle->dev.base_addr, lock_reg_offset, reg);
989 return kDifOk;
990}
991
992OT_WARN_UNUSED_RESULT
993dif_result_t dif_flash_ctrl_data_region_is_locked(
994 const dif_flash_ctrl_state_t *handle, uint32_t region, bool *locked_out) {
995 if (handle == NULL || locked_out == NULL ||
996 region >= FLASH_CTRL_PARAM_NUM_REGIONS) {
997 return kDifBadArg;
998 }
999 ptrdiff_t lock_reg_offset = get_data_region_lock_reg_offset(region);
1000 uint32_t reg = mmio_region_read32(handle->dev.base_addr, lock_reg_offset);
1001 *locked_out =
1002 !bitfield_bit32_read(reg, FLASH_CTRL_REGION_CFG_REGWEN_0_REGION_0_BIT);
1003 return kDifOk;
1004}
1005
1006OT_WARN_UNUSED_RESULT
1007dif_result_t dif_flash_ctrl_info_region_is_locked(
1008 const dif_flash_ctrl_state_t *handle, dif_flash_ctrl_info_region_t region,
1009 bool *locked_out) {
1010 if (handle == NULL || locked_out == NULL ||
1011 region.bank >= FLASH_CTRL_PARAM_REG_NUM_BANKS ||
1012 region.partition_id >= FLASH_CTRL_NUM_INFO_TYPES ||
1013 region.page > kNumInfoPagesPerBank[region.partition_id]) {
1014 return kDifBadArg;
1015 }
1016
1017 ptrdiff_t lock_reg_offset = get_info_region_lock_reg_offset(region);
1018 uint32_t reg = mmio_region_read32(handle->dev.base_addr, lock_reg_offset);
1019 *locked_out =
1020 !bitfield_bit32_read(reg, FLASH_CTRL_BANK0_INFO0_REGWEN_0_REGION_0_BIT);
1021 return kDifOk;
1022}
1023
1024OT_WARN_UNUSED_RESULT
1025dif_result_t dif_flash_ctrl_set_bank_erase_enablement(
1026 dif_flash_ctrl_state_t *handle, uint32_t bank, dif_toggle_t enable) {
1027 if (handle == NULL || bank >= FLASH_CTRL_PARAM_REG_NUM_BANKS) {
1028 return kDifBadArg;
1029 }
1030
1031 bool locked;
1032 DIF_RETURN_IF_ERROR(
1033 dif_flash_ctrl_bank_configuration_is_locked(handle, &locked));
1034 if (locked) {
1035 return kDifLocked;
1036 }
1037
1038 bitfield_bit32_index_t index = bank;
1039 uint32_t value = mmio_region_read32(
1040 handle->dev.base_addr, FLASH_CTRL_MP_BANK_CFG_SHADOWED_REG_OFFSET);
1041 switch (enable) {
1042 case kDifToggleEnabled:
1043 value = bitfield_bit32_write(value, index, true);
1044 break;
1045 case kDifToggleDisabled:
1046 value = bitfield_bit32_write(value, index, false);
1047 break;
1048 default:
1049 return kDifBadArg;
1050 }
1051 mmio_region_write32_shadowed(
1052 handle->dev.base_addr, FLASH_CTRL_MP_BANK_CFG_SHADOWED_REG_OFFSET, value);
1053 return kDifOk;
1054}
1055
1056OT_WARN_UNUSED_RESULT
1057dif_result_t dif_flash_ctrl_get_bank_erase_enablement(
1058 const dif_flash_ctrl_state_t *handle, uint32_t bank,
1059 dif_toggle_t *enabled_out) {
1060 if (handle == NULL || enabled_out == NULL ||
1061 bank >= FLASH_CTRL_PARAM_REG_NUM_BANKS) {
1062 return kDifBadArg;
1063 }
1064 uint32_t reg = mmio_region_read32(handle->dev.base_addr,
1065 FLASH_CTRL_MP_BANK_CFG_SHADOWED_REG_OFFSET);
1066 bitfield_bit32_index_t index = bank;
1067 bool enabled = bitfield_bit32_read(reg, index);
1068 if (enabled) {
1069 *enabled_out = kDifToggleEnabled;
1070 } else {
1071 *enabled_out = kDifToggleDisabled;
1072 }
1073 return kDifOk;
1074}
1075
1076OT_WARN_UNUSED_RESULT
1077dif_result_t dif_flash_ctrl_lock_bank_configuration(
1078 dif_flash_ctrl_state_t *handle) {
1079 if (handle == NULL) {
1080 return kDifBadArg;
1081 }
1082
1083 bool locked;
1084 DIF_RETURN_IF_ERROR(
1085 dif_flash_ctrl_bank_configuration_is_locked(handle, &locked));
1086 if (locked) {
1087 return kDifLocked;
1088 }
1089
1090 uint32_t reg =
1091 bitfield_bit32_write(0, FLASH_CTRL_BANK_CFG_REGWEN_BANK_BIT, false);
1092 mmio_region_write32(handle->dev.base_addr,
1093 FLASH_CTRL_BANK_CFG_REGWEN_REG_OFFSET, reg);
1094 return kDifOk;
1095}
1096
1097OT_WARN_UNUSED_RESULT
1098dif_result_t dif_flash_ctrl_bank_configuration_is_locked(
1099 const dif_flash_ctrl_state_t *handle, bool *locked_out) {
1100 if (handle == NULL || locked_out == NULL) {
1101 return kDifBadArg;
1102 }
1103 const uint32_t reg = mmio_region_read32(
1104 handle->dev.base_addr, FLASH_CTRL_BANK_CFG_REGWEN_REG_OFFSET);
1105 *locked_out = !bitfield_bit32_read(reg, FLASH_CTRL_BANK_CFG_REGWEN_BANK_BIT);
1106 return kDifOk;
1107}
1108
1109OT_WARN_UNUSED_RESULT
1110dif_result_t dif_flash_ctrl_set_prog_fifo_watermark(
1111 dif_flash_ctrl_state_t *handle, uint32_t level) {
1112 if (handle == NULL || level > FLASH_CTRL_FIFO_LVL_PROG_MASK) {
1113 return kDifBadArg;
1114 }
1115 uint32_t reg =
1116 mmio_region_read32(handle->dev.base_addr, FLASH_CTRL_FIFO_LVL_REG_OFFSET);
1117 reg = bitfield_field32_write(reg, FLASH_CTRL_FIFO_LVL_PROG_FIELD, level);
1118 mmio_region_write32(handle->dev.base_addr, FLASH_CTRL_FIFO_LVL_REG_OFFSET,
1119 reg);
1120 return kDifOk;
1121}
1122
1123OT_WARN_UNUSED_RESULT
1124dif_result_t dif_flash_ctrl_set_read_fifo_watermark(
1125 dif_flash_ctrl_state_t *handle, uint32_t level) {
1126 if (handle == NULL || level > FLASH_CTRL_FIFO_LVL_RD_MASK) {
1127 return kDifBadArg;
1128 }
1129 uint32_t reg =
1130 mmio_region_read32(handle->dev.base_addr, FLASH_CTRL_FIFO_LVL_REG_OFFSET);
1131 reg = bitfield_field32_write(reg, FLASH_CTRL_FIFO_LVL_RD_FIELD, level);
1132 mmio_region_write32(handle->dev.base_addr, FLASH_CTRL_FIFO_LVL_REG_OFFSET,
1133 reg);
1134 return kDifOk;
1135}
1136
1137OT_WARN_UNUSED_RESULT
1138dif_result_t dif_flash_ctrl_get_fifo_watermarks(
1139 const dif_flash_ctrl_state_t *handle, uint32_t *prog_out,
1140 uint32_t *read_out) {
1141 if (handle == NULL) {
1142 return kDifBadArg;
1143 }
1144 const uint32_t reg =
1145 mmio_region_read32(handle->dev.base_addr, FLASH_CTRL_FIFO_LVL_REG_OFFSET);
1146 if (prog_out != NULL) {
1147 *prog_out = bitfield_field32_read(reg, FLASH_CTRL_FIFO_LVL_PROG_FIELD);
1148 }
1149 if (read_out != NULL) {
1150 *read_out = bitfield_field32_read(reg, FLASH_CTRL_FIFO_LVL_RD_FIELD);
1151 }
1152 return kDifOk;
1153}
1154
1155// TODO: Allow splitting up turning the reset on and off?
1156OT_WARN_UNUSED_RESULT
1157dif_result_t dif_flash_ctrl_reset_fifos(dif_flash_ctrl_state_t *handle) {
1158 if (handle == NULL) {
1159 return kDifBadArg;
1160 }
1161 uint32_t reg = bitfield_bit32_write(0, FLASH_CTRL_FIFO_RST_EN_BIT, true);
1162 mmio_region_write32(handle->dev.base_addr, FLASH_CTRL_FIFO_RST_REG_OFFSET,
1163 reg);
1164 reg = bitfield_bit32_write(0, FLASH_CTRL_FIFO_RST_EN_BIT, false);
1165 mmio_region_write32(handle->dev.base_addr, FLASH_CTRL_FIFO_RST_REG_OFFSET,
1166 reg);
1167 return kDifOk;
1168}
1169
1170OT_WARN_UNUSED_RESULT
1171dif_result_t dif_flash_ctrl_get_faults(const dif_flash_ctrl_state_t *handle,
1172 dif_flash_ctrl_faults_t *faults_out) {
1173 if (handle == NULL || faults_out == NULL) {
1174 return kDifBadArg;
1175 }
1176 uint32_t reg = mmio_region_read32(handle->dev.base_addr,
1177 FLASH_CTRL_FAULT_STATUS_REG_OFFSET);
1178 dif_flash_ctrl_faults_t faults;
1179 faults.memory_properties_error =
1180 bitfield_bit32_read(reg, FLASH_CTRL_FAULT_STATUS_MP_ERR_BIT);
1181 faults.read_error =
1182 bitfield_bit32_read(reg, FLASH_CTRL_FAULT_STATUS_RD_ERR_BIT);
1183 faults.prog_window_error =
1184 bitfield_bit32_read(reg, FLASH_CTRL_FAULT_STATUS_PROG_WIN_ERR_BIT);
1185 faults.prog_type_error =
1186 bitfield_bit32_read(reg, FLASH_CTRL_FAULT_STATUS_PROG_TYPE_ERR_BIT);
1187 faults.host_gnt_error =
1188 bitfield_bit32_read(reg, FLASH_CTRL_FAULT_STATUS_HOST_GNT_ERR_BIT);
1189 reg = mmio_region_read32(handle->dev.base_addr,
1190 FLASH_CTRL_STD_FAULT_STATUS_REG_OFFSET);
1191 faults.register_integrity_error =
1192 bitfield_bit32_read(reg, FLASH_CTRL_STD_FAULT_STATUS_REG_INTG_ERR_BIT);
1193 faults.phy_integrity_error =
1194 bitfield_bit32_read(reg, FLASH_CTRL_STD_FAULT_STATUS_PROG_INTG_ERR_BIT);
1195 faults.lifecycle_manager_error =
1196 bitfield_bit32_read(reg, FLASH_CTRL_STD_FAULT_STATUS_LCMGR_ERR_BIT);
1197 faults.shadow_storage_error =
1198 bitfield_bit32_read(reg, FLASH_CTRL_STD_FAULT_STATUS_STORAGE_ERR_BIT);
1199 *faults_out = faults;
1200 return kDifOk;
1201}
1202
1203OT_WARN_UNUSED_RESULT
1204dif_result_t dif_flash_ctrl_get_ecc_errors(
1205 const dif_flash_ctrl_state_t *handle, uint32_t bank,
1206 dif_flash_ctrl_ecc_errors_t *errors_out) {
1207 if (handle == NULL || errors_out == NULL ||
1208 bank > FLASH_CTRL_PARAM_REG_NUM_BANKS) {
1209 return kDifBadArg;
1210 }
1211 bitfield_field32_t error_count_field;
1212 ptrdiff_t last_addr_reg_offset;
1213#if FLASH_CTRL_PARAM_REG_NUM_BANKS > 2
1214#error "Revise this function to handle more banks."
1215#endif
1216 if (bank == 0) {
1217 error_count_field =
1218 FLASH_CTRL_ECC_SINGLE_ERR_CNT_ECC_SINGLE_ERR_CNT_0_FIELD;
1219 last_addr_reg_offset = FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_REG_OFFSET;
1220 } else {
1221 error_count_field =
1222 FLASH_CTRL_ECC_SINGLE_ERR_CNT_ECC_SINGLE_ERR_CNT_1_FIELD;
1223 last_addr_reg_offset = FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_REG_OFFSET;
1224 }
1225
1226 uint32_t reg = mmio_region_read32(handle->dev.base_addr,
1227 FLASH_CTRL_ECC_SINGLE_ERR_CNT_REG_OFFSET);
1228 errors_out->single_bit_error_count =
1229 bitfield_field32_read(reg, error_count_field);
1230 errors_out->last_error_address =
1231 mmio_region_read32(handle->dev.base_addr, last_addr_reg_offset);
1232 return kDifOk;
1233}
1234
1235OT_WARN_UNUSED_RESULT
1236dif_result_t dif_flash_ctrl_get_phy_status(
1237 const dif_flash_ctrl_state_t *handle,
1238 dif_flash_ctrl_phy_status_t *status_out) {
1239 if (handle == NULL || status_out == NULL) {
1240 return kDifBadArg;
1241 }
1242 const uint32_t reg = mmio_region_read32(handle->dev.base_addr,
1243 FLASH_CTRL_PHY_STATUS_REG_OFFSET);
1244 dif_flash_ctrl_phy_status_t status = {
1245 .phy_init_wip =
1246 bitfield_bit32_read(reg, FLASH_CTRL_PHY_STATUS_INIT_WIP_BIT),
1247 .prog_normal_available =
1248 bitfield_bit32_read(reg, FLASH_CTRL_PHY_STATUS_PROG_NORMAL_AVAIL_BIT),
1249 .prog_repair_available =
1250 bitfield_bit32_read(reg, FLASH_CTRL_PHY_STATUS_PROG_REPAIR_AVAIL_BIT),
1251 };
1252 *status_out = status;
1253 return kDifOk;
1254}
1255
1256OT_WARN_UNUSED_RESULT
1257dif_result_t dif_flash_ctrl_set_scratch(dif_flash_ctrl_state_t *handle,
1258 uint32_t value) {
1259 if (handle == NULL) {
1260 return kDifBadArg;
1261 }
1262 mmio_region_write32(handle->dev.base_addr, FLASH_CTRL_SCRATCH_REG_OFFSET,
1263 value);
1264 return kDifOk;
1265}
1266
1267OT_WARN_UNUSED_RESULT
1268dif_result_t dif_flash_ctrl_get_scratch(const dif_flash_ctrl_state_t *handle,
1269 uint32_t *value_out) {
1270 if (handle == NULL || value_out == NULL) {
1271 return kDifBadArg;
1272 }
1273 *value_out =
1274 mmio_region_read32(handle->dev.base_addr, FLASH_CTRL_SCRATCH_REG_OFFSET);
1275 return kDifOk;
1276}