Software APIs
dif_entropy_src_unittest.cc
1 // Copyright lowRISC contributors (OpenTitan project).
2 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3 // SPDX-License-Identifier: Apache-2.0
4 
6 
7 #include "gtest/gtest.h"
9 #include "sw/device/lib/base/mock_mmio.h"
10 #include "sw/device/lib/base/multibits.h"
13 
14 #include "entropy_src_regs.h" // Generated
15 
16 namespace dif_entropy_src_unittest {
17 namespace {
18 
19 class EntropySrcTest : public testing::Test, public mock_mmio::MmioTest {
20  protected:
21  const dif_entropy_src_t entropy_src_ = {.base_addr = dev().region()};
22 };
23 
24 class ConfigTest : public EntropySrcTest {
25  protected:
26  dif_entropy_src_config_t config_ = {
27  .fips_enable = false,
28  .fips_flag = true,
29  .rng_fips = true,
30  .route_to_firmware = false,
31  .bypass_conditioner = false,
32  .single_bit_mode = kDifEntropySrcSingleBitModeDisabled,
33  .health_test_window_size = 1};
34 };
35 
36 TEST_F(ConfigTest, NullHandle) {
38  dif_entropy_src_configure(nullptr, config_, kDifToggleEnabled));
39 }
40 
41 TEST_F(ConfigTest, BadEnabled) {
42  EXPECT_DIF_BADARG(dif_entropy_src_configure(&entropy_src_, config_,
43  static_cast<dif_toggle_t>(2)));
44 }
45 
46 TEST_F(ConfigTest, BadSingleBitMode) {
47  config_.single_bit_mode = static_cast<dif_entropy_src_single_bit_mode_t>(5);
49  dif_entropy_src_configure(&entropy_src_, config_, kDifToggleEnabled));
50 }
51 
52 TEST_F(ConfigTest, Locked) {
53  EXPECT_READ32(ENTROPY_SRC_REGWEN_REG_OFFSET, 0);
54  EXPECT_EQ(
55  dif_entropy_src_configure(&entropy_src_, config_, kDifToggleEnabled),
56  kDifLocked);
57 }
58 
59 struct ConfigParams {
60  bool fips_enable;
61  bool fips_flag;
62  bool rng_fips;
63  bool route_to_firmware;
64  bool bypass_conditioner;
65  dif_entropy_src_single_bit_mode_t single_bit_mode;
66  bool health_test_threshold_scope;
67  uint16_t health_test_window_size;
68  uint16_t alert_threshold;
69  dif_toggle_t enabled;
70 };
71 
73  public testing::WithParamInterface<ConfigParams> {};
74 
75 TEST_P(ConfigTestAllParams, ValidConfigurationMode) {
76  const ConfigParams &test_param = GetParam();
77  config_.fips_enable = test_param.fips_enable;
78  config_.fips_flag = test_param.fips_flag;
79  config_.rng_fips = test_param.rng_fips;
80  config_.route_to_firmware = test_param.route_to_firmware;
81  config_.bypass_conditioner = test_param.bypass_conditioner;
82  config_.single_bit_mode = test_param.single_bit_mode;
83  config_.health_test_threshold_scope = test_param.health_test_threshold_scope;
84  config_.health_test_window_size = test_param.health_test_window_size;
85  config_.alert_threshold = test_param.alert_threshold;
86 
87  EXPECT_READ32(ENTROPY_SRC_REGWEN_REG_OFFSET, 1);
88 
89  multi_bit_bool_t route_to_firmware_mubi =
90  test_param.route_to_firmware ? kMultiBitBool4True : kMultiBitBool4False;
91  multi_bit_bool_t bypass_conditioner_mubi =
92  test_param.bypass_conditioner ? kMultiBitBool4True : kMultiBitBool4False;
93 
94  EXPECT_WRITE32(
95  ENTROPY_SRC_ENTROPY_CONTROL_REG_OFFSET,
96  {
97  {ENTROPY_SRC_ENTROPY_CONTROL_ES_ROUTE_OFFSET, route_to_firmware_mubi},
98  {ENTROPY_SRC_ENTROPY_CONTROL_ES_TYPE_OFFSET, bypass_conditioner_mubi},
99  });
100 
101  multi_bit_bool_t fips_enable_mubi =
102  test_param.fips_enable ? kMultiBitBool4True : kMultiBitBool4False;
103  multi_bit_bool_t fips_flag_mubi =
104  test_param.fips_flag ? kMultiBitBool4True : kMultiBitBool4False;
105  multi_bit_bool_t rng_fips_mubi =
106  test_param.rng_fips ? kMultiBitBool4True : kMultiBitBool4False;
107  multi_bit_bool_t threshold_scope_mubi = test_param.health_test_threshold_scope
108  ? kMultiBitBool4True
109  : kMultiBitBool4False;
110  multi_bit_bool_t rng_bit_enable_mubi =
111  test_param.single_bit_mode == kDifEntropySrcSingleBitModeDisabled
112  ? kMultiBitBool4False
113  : kMultiBitBool4True;
114  uint8_t rng_bit_sel =
115  test_param.single_bit_mode == kDifEntropySrcSingleBitModeDisabled
116  ? 0
117  : test_param.single_bit_mode;
118 
119  EXPECT_WRITE32(
120  ENTROPY_SRC_CONF_REG_OFFSET,
121  {
122  {ENTROPY_SRC_CONF_FIPS_ENABLE_OFFSET, fips_enable_mubi},
123  {ENTROPY_SRC_CONF_ENTROPY_DATA_REG_ENABLE_OFFSET,
124  route_to_firmware_mubi},
125  {ENTROPY_SRC_CONF_FIPS_FLAG_OFFSET, fips_flag_mubi},
126  {ENTROPY_SRC_CONF_RNG_FIPS_OFFSET, rng_fips_mubi},
127  {ENTROPY_SRC_CONF_THRESHOLD_SCOPE_OFFSET, threshold_scope_mubi},
128  {ENTROPY_SRC_CONF_RNG_BIT_ENABLE_OFFSET, rng_bit_enable_mubi},
129  {ENTROPY_SRC_CONF_RNG_BIT_SEL_OFFSET, rng_bit_sel},
130  });
131 
132  EXPECT_WRITE32(ENTROPY_SRC_HEALTH_TEST_WINDOWS_REG_OFFSET,
133  {{ENTROPY_SRC_HEALTH_TEST_WINDOWS_BYPASS_WINDOW_OFFSET,
134  ENTROPY_SRC_HEALTH_TEST_WINDOWS_REG_RESVAL >>
135  ENTROPY_SRC_HEALTH_TEST_WINDOWS_BYPASS_WINDOW_OFFSET},
136  {ENTROPY_SRC_HEALTH_TEST_WINDOWS_FIPS_WINDOW_OFFSET,
137  test_param.health_test_window_size}});
138 
139  EXPECT_WRITE32(ENTROPY_SRC_ALERT_THRESHOLD_REG_OFFSET,
140  {{ENTROPY_SRC_ALERT_THRESHOLD_ALERT_THRESHOLD_INV_OFFSET,
141  static_cast<decltype(test_param.alert_threshold)>(
142  ~test_param.alert_threshold)},
143  {ENTROPY_SRC_ALERT_THRESHOLD_ALERT_THRESHOLD_OFFSET,
144  test_param.alert_threshold}});
145 
146  EXPECT_WRITE32(ENTROPY_SRC_MODULE_ENABLE_REG_OFFSET,
147  {
148  {ENTROPY_SRC_MODULE_ENABLE_MODULE_ENABLE_OFFSET,
149  dif_toggle_to_multi_bit_bool4(test_param.enabled)},
150  });
151 
153  dif_entropy_src_configure(&entropy_src_, config_, test_param.enabled));
154 }
155 
156 INSTANTIATE_TEST_SUITE_P(ConfigTestAllParams, ConfigTestAllParams,
157  testing::Values(
158  // Test FIPS enabled.
159  ConfigParams{true, true, true, false, false,
161  false, 0xFFFF, 2, kDifToggleEnabled},
162  // Test route to firmware.
163  ConfigParams{false, true, true, true, false,
165  false, 2, kDifToggleEnabled},
166  // Test bypass conditioner.
167  ConfigParams{false, false, false, false, true,
169  false, 2, kDifToggleEnabled},
170  // Test single_bit_mode.
171  ConfigParams{false, true, true, false, false,
173  512, 2, kDifToggleEnabled},
174  ConfigParams{false, true, true, false, false,
176  256, 2, kDifToggleEnabled},
177  ConfigParams{false, true, true, false, false,
179  128, 2, kDifToggleEnabled},
180  ConfigParams{false, true, true, false, false,
182  64, 2, kDifToggleEnabled},
183  // Test alerts disabled.
184  ConfigParams{false, false, false, false, false,
186  1, 0, kDifToggleDisabled},
187  // Test all disabled.
188  ConfigParams{false, false, false, false, false,
190  1, 2, kDifToggleDisabled},
191  // Test all enabled.
192  ConfigParams{true, true, true, true, false,
194  true, 32, 2, kDifToggleEnabled}));
195 
197  protected:
199  .entropy_insert_enable = true,
200  .buffer_threshold = ENTROPY_SRC_OBSERVE_FIFO_THRESH_REG_RESVAL,
201  };
202 };
203 
204 TEST_F(FwOverrideConfigTest, NullHandle) {
207 }
208 
209 TEST_F(FwOverrideConfigTest, BadBufferThreshold) {
210  config_.buffer_threshold =
211  ENTROPY_SRC_OBSERVE_FIFO_THRESH_OBSERVE_FIFO_THRESH_MASK + 1;
213  &entropy_src_, config_, kDifToggleEnabled));
214 
215  config_.buffer_threshold = 0;
217  &entropy_src_, config_, kDifToggleEnabled));
218 }
219 
220 TEST_F(FwOverrideConfigTest, BadEnabled) {
222  &entropy_src_, config_, static_cast<dif_toggle_t>(2)));
223 }
224 
225 TEST_F(FwOverrideConfigTest, Locked) {
226  EXPECT_READ32(ENTROPY_SRC_REGWEN_REG_OFFSET, 0);
227  EXPECT_EQ(dif_entropy_src_fw_override_configure(&entropy_src_, config_,
229  kDifLocked);
230 }
231 
232 TEST_F(FwOverrideConfigTest, Success) {
233  EXPECT_READ32(ENTROPY_SRC_REGWEN_REG_OFFSET, 1);
234  EXPECT_WRITE32(ENTROPY_SRC_OBSERVE_FIFO_THRESH_REG_OFFSET,
235  config_.buffer_threshold);
236  EXPECT_WRITE32(ENTROPY_SRC_FW_OV_CONTROL_REG_OFFSET, 0x66);
239 
240  EXPECT_READ32(ENTROPY_SRC_REGWEN_REG_OFFSET, 1);
241  EXPECT_WRITE32(ENTROPY_SRC_OBSERVE_FIFO_THRESH_REG_OFFSET,
242  config_.buffer_threshold);
243  EXPECT_WRITE32(ENTROPY_SRC_FW_OV_CONTROL_REG_OFFSET, 0x69);
246 }
247 
249  protected:
252  .high_threshold = 0xFFFF,
253  .low_threshold = 0,
254  };
255 };
256 
257 TEST_F(HealthTestConfigTest, NullHandle) {
259 }
260 
261 TEST_F(HealthTestConfigTest, Locked) {
262  EXPECT_READ32(ENTROPY_SRC_REGWEN_REG_OFFSET, 0);
263  EXPECT_EQ(dif_entropy_src_health_test_configure(&entropy_src_, config_),
264  kDifLocked);
265 }
266 
267 TEST_F(HealthTestConfigTest, BadTestType) {
268  config_.test_type = kDifEntropySrcTestNumVariants;
269  EXPECT_READ32(ENTROPY_SRC_REGWEN_REG_OFFSET, 1);
271  dif_entropy_src_health_test_configure(&entropy_src_, config_));
272 }
273 
274 TEST_F(HealthTestConfigTest, BadLowThreshold) {
275  config_.low_threshold = 0x1;
276  EXPECT_READ32(ENTROPY_SRC_REGWEN_REG_OFFSET, 1);
278  dif_entropy_src_health_test_configure(&entropy_src_, config_));
279 }
280 
281 TEST_F(HealthTestConfigTest, SuccessOneThreshold) {
282  EXPECT_READ32(ENTROPY_SRC_REGWEN_REG_OFFSET, 1);
283  EXPECT_WRITE32(ENTROPY_SRC_REPCNT_THRESHOLDS_REG_OFFSET,
284  config_.high_threshold);
285  EXPECT_DIF_OK(dif_entropy_src_health_test_configure(&entropy_src_, config_));
286 }
287 
288 TEST_F(HealthTestConfigTest, SuccessTwoThresholds) {
289  config_.test_type = kDifEntropySrcTestMarkov;
290  config_.low_threshold = 0xABAB;
291  EXPECT_READ32(ENTROPY_SRC_REGWEN_REG_OFFSET, 1);
292  EXPECT_WRITE32(ENTROPY_SRC_MARKOV_HI_THRESHOLDS_REG_OFFSET,
293  config_.high_threshold);
294  EXPECT_WRITE32(ENTROPY_SRC_MARKOV_LO_THRESHOLDS_REG_OFFSET,
295  config_.low_threshold);
296  EXPECT_DIF_OK(dif_entropy_src_health_test_configure(&entropy_src_, config_));
297 }
298 
299 class SetEnabledTest : public EntropySrcTest {};
300 
301 TEST_F(SetEnabledTest, NullHandle) {
303 }
304 
305 TEST_F(SetEnabledTest, BadToggle) {
307  dif_entropy_src_set_enabled(nullptr, static_cast<dif_toggle_t>(1)));
308 }
309 
310 TEST_F(SetEnabledTest, Locked) {
311  EXPECT_READ32(ENTROPY_SRC_ME_REGWEN_REG_OFFSET, 0);
312  EXPECT_EQ(dif_entropy_src_set_enabled(&entropy_src_, kDifToggleEnabled),
313  kDifLocked);
314 }
315 
316 TEST_F(SetEnabledTest, Success) {
317  // Enable.
318  EXPECT_READ32(ENTROPY_SRC_ME_REGWEN_REG_OFFSET, 1);
319  EXPECT_WRITE32(ENTROPY_SRC_MODULE_ENABLE_REG_OFFSET, kMultiBitBool4True);
321 
322  // Disable.
323  EXPECT_READ32(ENTROPY_SRC_ME_REGWEN_REG_OFFSET, 1);
324  EXPECT_WRITE32(ENTROPY_SRC_MODULE_ENABLE_REG_OFFSET, kMultiBitBool4False);
326 }
327 
328 class LockTest : public EntropySrcTest {};
329 
330 TEST_F(LockTest, NullHandle) {
332 }
333 
334 TEST_F(LockTest, Success) {
335  EXPECT_WRITE32(ENTROPY_SRC_ME_REGWEN_REG_OFFSET, 0);
336  EXPECT_WRITE32(ENTROPY_SRC_SW_REGUPD_REG_OFFSET, 0);
337  EXPECT_DIF_OK(dif_entropy_src_lock(&entropy_src_));
338 }
339 
340 class IsLockedTest : public EntropySrcTest {};
341 
342 TEST_F(IsLockedTest, NullArgs) {
343  bool is_locked;
344  EXPECT_DIF_BADARG(dif_entropy_src_is_locked(nullptr, &is_locked));
345  EXPECT_DIF_BADARG(dif_entropy_src_is_locked(&entropy_src_, nullptr));
346  EXPECT_DIF_BADARG(dif_entropy_src_is_locked(nullptr, nullptr));
347 }
348 
349 TEST_F(IsLockedTest, BadState) {
350  bool is_locked;
351  EXPECT_READ32(ENTROPY_SRC_ME_REGWEN_REG_OFFSET, 1);
352  EXPECT_READ32(ENTROPY_SRC_SW_REGUPD_REG_OFFSET, 0);
353  EXPECT_EQ(dif_entropy_src_is_locked(&entropy_src_, &is_locked), kDifError);
354 
355  EXPECT_READ32(ENTROPY_SRC_ME_REGWEN_REG_OFFSET, 0);
356  EXPECT_READ32(ENTROPY_SRC_SW_REGUPD_REG_OFFSET, 1);
357  EXPECT_EQ(dif_entropy_src_is_locked(&entropy_src_, &is_locked), kDifError);
358 }
359 
360 TEST_F(IsLockedTest, Success) {
361  bool is_locked;
362  EXPECT_READ32(ENTROPY_SRC_ME_REGWEN_REG_OFFSET, 0);
363  EXPECT_READ32(ENTROPY_SRC_SW_REGUPD_REG_OFFSET, 0);
364  EXPECT_DIF_OK(dif_entropy_src_is_locked(&entropy_src_, &is_locked));
365  EXPECT_TRUE(is_locked);
366 
367  EXPECT_READ32(ENTROPY_SRC_ME_REGWEN_REG_OFFSET, 1);
368  EXPECT_READ32(ENTROPY_SRC_SW_REGUPD_REG_OFFSET, 1);
369  EXPECT_DIF_OK(dif_entropy_src_is_locked(&entropy_src_, &is_locked));
370  EXPECT_FALSE(is_locked);
371 }
372 
374 
375 TEST_F(HealthTestStatsGetTest, NullArgs) {
379  dif_entropy_src_get_health_test_stats(&entropy_src_, nullptr));
381 }
382 
383 TEST_F(HealthTestStatsGetTest, Success) {
385 
386  EXPECT_READ32(ENTROPY_SRC_REPCNT_HI_WATERMARKS_REG_OFFSET, 10);
387  EXPECT_READ32(ENTROPY_SRC_REPCNT_TOTAL_FAILS_REG_OFFSET, 10);
388 
389  EXPECT_READ32(ENTROPY_SRC_REPCNTS_HI_WATERMARKS_REG_OFFSET, 10);
390  EXPECT_READ32(ENTROPY_SRC_REPCNTS_TOTAL_FAILS_REG_OFFSET, 10);
391 
392  EXPECT_READ32(ENTROPY_SRC_ADAPTP_HI_WATERMARKS_REG_OFFSET, 10);
393  EXPECT_READ32(ENTROPY_SRC_ADAPTP_LO_WATERMARKS_REG_OFFSET, 10);
394  EXPECT_READ32(ENTROPY_SRC_ADAPTP_HI_TOTAL_FAILS_REG_OFFSET, 10);
395  EXPECT_READ32(ENTROPY_SRC_ADAPTP_LO_TOTAL_FAILS_REG_OFFSET, 10);
396 
397  EXPECT_READ32(ENTROPY_SRC_BUCKET_HI_WATERMARKS_REG_OFFSET, 10);
398  EXPECT_READ32(ENTROPY_SRC_BUCKET_TOTAL_FAILS_REG_OFFSET, 10);
399 
400  EXPECT_READ32(ENTROPY_SRC_MARKOV_HI_WATERMARKS_REG_OFFSET, 10);
401  EXPECT_READ32(ENTROPY_SRC_MARKOV_LO_WATERMARKS_REG_OFFSET, 10);
402  EXPECT_READ32(ENTROPY_SRC_MARKOV_HI_TOTAL_FAILS_REG_OFFSET, 10);
403  EXPECT_READ32(ENTROPY_SRC_MARKOV_LO_TOTAL_FAILS_REG_OFFSET, 10);
404 
405  EXPECT_READ32(ENTROPY_SRC_EXTHT_HI_WATERMARKS_REG_OFFSET, 10);
406  EXPECT_READ32(ENTROPY_SRC_EXTHT_LO_WATERMARKS_REG_OFFSET, 10);
407  EXPECT_READ32(ENTROPY_SRC_EXTHT_HI_TOTAL_FAILS_REG_OFFSET, 10);
408  EXPECT_READ32(ENTROPY_SRC_EXTHT_LO_TOTAL_FAILS_REG_OFFSET, 10);
409 
411  for (uint32_t i = 0; i < kDifEntropySrcTestNumVariants; ++i) {
412  EXPECT_EQ(stats.high_watermark[i], 10);
413  if (i == 2 || i == 4 || i == 5) {
414  EXPECT_EQ(stats.low_watermark[i], 10);
415  } else {
416  EXPECT_EQ(stats.low_watermark[i], 0);
417  }
418 
419  EXPECT_EQ(stats.high_fails[i], 10);
420  if (i == 2 || i == 4 || i == 5) {
421  EXPECT_EQ(stats.low_fails[i], 10);
422  } else {
423  EXPECT_EQ(stats.low_fails[i], 0);
424  }
425  }
426 }
427 
429 
430 TEST_F(GetAlertFailCountsTest, NullArgs) {
434  dif_entropy_src_get_alert_fail_counts(&entropy_src_, nullptr));
436 }
437 
438 TEST_F(GetAlertFailCountsTest, Success) {
440 
441  EXPECT_READ32(ENTROPY_SRC_ALERT_SUMMARY_FAIL_COUNTS_REG_OFFSET, 128);
442  EXPECT_READ32(
443  ENTROPY_SRC_ALERT_FAIL_COUNTS_REG_OFFSET,
444  {{ENTROPY_SRC_ALERT_FAIL_COUNTS_REPCNT_FAIL_COUNT_OFFSET, 0xA},
445  {ENTROPY_SRC_ALERT_FAIL_COUNTS_ADAPTP_HI_FAIL_COUNT_OFFSET, 0xC},
446  {ENTROPY_SRC_ALERT_FAIL_COUNTS_ADAPTP_LO_FAIL_COUNT_OFFSET, 0xC},
447  {ENTROPY_SRC_ALERT_FAIL_COUNTS_BUCKET_FAIL_COUNT_OFFSET, 0xD},
448  {ENTROPY_SRC_ALERT_FAIL_COUNTS_MARKOV_HI_FAIL_COUNT_OFFSET, 0xE},
449  {ENTROPY_SRC_ALERT_FAIL_COUNTS_MARKOV_LO_FAIL_COUNT_OFFSET, 0xE},
450  {ENTROPY_SRC_ALERT_FAIL_COUNTS_REPCNTS_FAIL_COUNT_OFFSET, 0xB}});
451  EXPECT_READ32(
452  ENTROPY_SRC_EXTHT_FAIL_COUNTS_REG_OFFSET,
453  {{ENTROPY_SRC_EXTHT_FAIL_COUNTS_EXTHT_HI_FAIL_COUNT_OFFSET, 0xF},
454  {ENTROPY_SRC_EXTHT_FAIL_COUNTS_EXTHT_LO_FAIL_COUNT_OFFSET, 0xF}});
455  EXPECT_DIF_OK(dif_entropy_src_get_alert_fail_counts(&entropy_src_, &counts));
456 
457  uint8_t num_fails = 0xA;
458  for (uint32_t i = 0; i < kDifEntropySrcTestNumVariants; ++i) {
459  EXPECT_EQ(counts.high_fails[i], num_fails);
460  if (i == 2 || i == 4 || i == 5) {
461  EXPECT_EQ(counts.low_fails[i], num_fails);
462  } else {
463  EXPECT_EQ(counts.low_fails[i], 0);
464  }
465  num_fails++;
466  }
467 }
468 
470 
471 TEST_F(IsEntropyAvailableTest, NullHandle) {
473 }
474 
475 TEST_F(IsEntropyAvailableTest, Unavailable) {
476  EXPECT_READ32(ENTROPY_SRC_INTR_STATE_REG_OFFSET,
477  {{ENTROPY_SRC_INTR_STATE_ES_ENTROPY_VALID_BIT, false}});
478  EXPECT_EQ(dif_entropy_src_is_entropy_available(&entropy_src_),
480 }
481 
482 TEST_F(IsEntropyAvailableTest, Available) {
483  EXPECT_READ32(ENTROPY_SRC_INTR_STATE_REG_OFFSET,
484  {{ENTROPY_SRC_INTR_STATE_ES_ENTROPY_VALID_BIT, true}});
486 }
487 
489 
490 TEST_F(NonBlockingReadTest, NullArgs) {
491  uint32_t word;
493  EXPECT_DIF_BADARG(dif_entropy_src_non_blocking_read(&entropy_src_, nullptr));
495 }
496 
497 TEST_F(NonBlockingReadTest, DataUnavailable) {
498  EXPECT_READ32(ENTROPY_SRC_INTR_STATE_REG_OFFSET, 0);
499  uint32_t word;
500  EXPECT_EQ(dif_entropy_src_non_blocking_read(&entropy_src_, &word),
502 }
503 
504 TEST_F(NonBlockingReadTest, Success) {
505  const uint32_t expected_word = 0x65585497;
506  EXPECT_READ32(ENTROPY_SRC_INTR_STATE_REG_OFFSET,
507  1 << ENTROPY_SRC_INTR_STATE_ES_ENTROPY_VALID_BIT);
508  EXPECT_READ32(ENTROPY_SRC_ENTROPY_DATA_REG_OFFSET, expected_word);
509  EXPECT_READ32(ENTROPY_SRC_INTR_STATE_REG_OFFSET,
510  1 << ENTROPY_SRC_INTR_STATE_ES_ENTROPY_VALID_BIT);
511  EXPECT_WRITE32(ENTROPY_SRC_INTR_STATE_REG_OFFSET,
512  {{ENTROPY_SRC_INTR_STATE_ES_ENTROPY_VALID_BIT, true}});
513 
514  uint32_t word;
515  EXPECT_DIF_OK(dif_entropy_src_non_blocking_read(&entropy_src_, &word));
516  EXPECT_EQ(word, expected_word);
517 }
518 
520 
521 TEST_F(ObserveFifoBlockingReadTest, NullHandle) {
522  uint32_t buf[8];
525 }
526 
527 TEST_F(ObserveFifoBlockingReadTest, BadLength) {
528  uint32_t buf[8];
529  EXPECT_READ32(ENTROPY_SRC_OBSERVE_FIFO_THRESH_REG_OFFSET, 7);
531  dif_entropy_src_observe_fifo_blocking_read(&entropy_src_, buf, 8));
532 }
533 
534 TEST_F(ObserveFifoBlockingReadTest, BadConfig) {
535  uint32_t buf[8];
536  EXPECT_READ32(ENTROPY_SRC_OBSERVE_FIFO_THRESH_REG_OFFSET, 8);
537  EXPECT_READ32(
538  ENTROPY_SRC_FW_OV_CONTROL_REG_OFFSET,
539  {{ENTROPY_SRC_FW_OV_CONTROL_FW_OV_ENTROPY_INSERT_OFFSET,
540  kMultiBitBool4False},
541  {ENTROPY_SRC_FW_OV_CONTROL_FW_OV_MODE_OFFSET, kMultiBitBool4False}});
542  EXPECT_EQ(dif_entropy_src_observe_fifo_blocking_read(&entropy_src_, buf, 8),
543  kDifError);
544 }
545 
546 TEST_F(ObserveFifoBlockingReadTest, SuccessDataThroughAway) {
547  uint32_t buf[4] = {0};
548  EXPECT_READ32(ENTROPY_SRC_OBSERVE_FIFO_THRESH_REG_OFFSET, 4);
549  EXPECT_READ32(
550  ENTROPY_SRC_FW_OV_CONTROL_REG_OFFSET,
551  {{ENTROPY_SRC_FW_OV_CONTROL_FW_OV_ENTROPY_INSERT_OFFSET,
552  kMultiBitBool4False},
553  {ENTROPY_SRC_FW_OV_CONTROL_FW_OV_MODE_OFFSET, kMultiBitBool4True}});
554  EXPECT_READ32(ENTROPY_SRC_INTR_STATE_REG_OFFSET,
555  {{ENTROPY_SRC_INTR_STATE_ES_OBSERVE_FIFO_READY_BIT, 1}});
556  for (size_t i = 0; i < 4; ++i) {
557  EXPECT_READ32(ENTROPY_SRC_FW_OV_RD_DATA_REG_OFFSET, i);
558  }
559  EXPECT_WRITE32(ENTROPY_SRC_INTR_STATE_REG_OFFSET,
560  {{ENTROPY_SRC_INTR_STATE_ES_OBSERVE_FIFO_READY_BIT, 1}});
562  dif_entropy_src_observe_fifo_blocking_read(&entropy_src_, nullptr, 4));
563  for (size_t i = 0; i < 4; ++i) {
564  EXPECT_EQ(buf[i], 0);
565  }
566 }
567 
568 TEST_F(ObserveFifoBlockingReadTest, SuccessDataSave) {
569  uint32_t buf[4];
570  EXPECT_READ32(ENTROPY_SRC_OBSERVE_FIFO_THRESH_REG_OFFSET, 4);
571  EXPECT_READ32(
572  ENTROPY_SRC_FW_OV_CONTROL_REG_OFFSET,
573  {{ENTROPY_SRC_FW_OV_CONTROL_FW_OV_ENTROPY_INSERT_OFFSET,
574  kMultiBitBool4False},
575  {ENTROPY_SRC_FW_OV_CONTROL_FW_OV_MODE_OFFSET, kMultiBitBool4True}});
576  EXPECT_READ32(ENTROPY_SRC_INTR_STATE_REG_OFFSET,
577  {{ENTROPY_SRC_INTR_STATE_ES_OBSERVE_FIFO_READY_BIT, 1}});
578  for (size_t i = 0; i < 4; ++i) {
579  EXPECT_READ32(ENTROPY_SRC_FW_OV_RD_DATA_REG_OFFSET, i);
580  }
581  EXPECT_WRITE32(ENTROPY_SRC_INTR_STATE_REG_OFFSET,
582  {{ENTROPY_SRC_INTR_STATE_ES_OBSERVE_FIFO_READY_BIT, 1}});
584  dif_entropy_src_observe_fifo_blocking_read(&entropy_src_, buf, 4));
585  for (size_t i = 0; i < 4; ++i) {
586  EXPECT_EQ(buf[i], i);
587  }
588 }
589 
591 
592 TEST_F(ObserveFifoWriteTest, NullArgs) {
593  uint32_t buf[8] = {0};
594  EXPECT_DIF_BADARG(dif_entropy_src_fw_ov_data_write(nullptr, buf, 8, nullptr));
596  dif_entropy_src_fw_ov_data_write(&entropy_src_, nullptr, 8, nullptr));
598  dif_entropy_src_fw_ov_data_write(nullptr, nullptr, 8, nullptr));
599 }
600 
601 TEST_F(ObserveFifoWriteTest, BadConfig) {
602  uint32_t buf[8];
603 
604  // Firmware override mode not set.
605  EXPECT_READ32(
606  ENTROPY_SRC_FW_OV_CONTROL_REG_OFFSET,
607  {{ENTROPY_SRC_FW_OV_CONTROL_FW_OV_ENTROPY_INSERT_OFFSET,
608  kMultiBitBool4False},
609  {ENTROPY_SRC_FW_OV_CONTROL_FW_OV_MODE_OFFSET, kMultiBitBool4False}});
610  EXPECT_EQ(dif_entropy_src_fw_ov_data_write(&entropy_src_, buf, 8, nullptr),
611  kDifError);
612 
613  // Entropy insert mode not set.
614  EXPECT_READ32(
615  ENTROPY_SRC_FW_OV_CONTROL_REG_OFFSET,
616  {{ENTROPY_SRC_FW_OV_CONTROL_FW_OV_ENTROPY_INSERT_OFFSET,
617  kMultiBitBool4False},
618  {ENTROPY_SRC_FW_OV_CONTROL_FW_OV_MODE_OFFSET, kMultiBitBool4True}});
619  EXPECT_EQ(dif_entropy_src_fw_ov_data_write(&entropy_src_, buf, 8, nullptr),
620  kDifError);
621 }
622 
623 TEST_F(ObserveFifoWriteTest, FifoFull) {
624  uint32_t buf[4];
625  size_t written = -1;
626  EXPECT_READ32(
627  ENTROPY_SRC_FW_OV_CONTROL_REG_OFFSET,
628  {{ENTROPY_SRC_FW_OV_CONTROL_FW_OV_ENTROPY_INSERT_OFFSET,
629  kMultiBitBool4True},
630  {ENTROPY_SRC_FW_OV_CONTROL_FW_OV_MODE_OFFSET, kMultiBitBool4True}});
631  EXPECT_READ32(ENTROPY_SRC_FW_OV_WR_FIFO_FULL_REG_OFFSET, 1);
632  EXPECT_EQ(dif_entropy_src_fw_ov_data_write(&entropy_src_, buf, 4, &written),
634  EXPECT_EQ(written, 0);
635 }
636 
637 TEST_F(ObserveFifoWriteTest, Success) {
638  uint32_t buf[4] = {1, 2, 3, 4};
639  size_t written = -1;
640  EXPECT_READ32(
641  ENTROPY_SRC_FW_OV_CONTROL_REG_OFFSET,
642  {{ENTROPY_SRC_FW_OV_CONTROL_FW_OV_ENTROPY_INSERT_OFFSET,
643  kMultiBitBool4True},
644  {ENTROPY_SRC_FW_OV_CONTROL_FW_OV_MODE_OFFSET, kMultiBitBool4True}});
645  for (size_t i = 0; i < 4; ++i) {
646  EXPECT_READ32(ENTROPY_SRC_FW_OV_WR_FIFO_FULL_REG_OFFSET, 0);
647  EXPECT_WRITE32(ENTROPY_SRC_FW_OV_WR_DATA_REG_OFFSET, i + 1);
648  }
650  dif_entropy_src_fw_ov_data_write(&entropy_src_, buf, 4, &written));
651  EXPECT_EQ(written, 4);
652 }
653 
655 
656 TEST_F(ConditionerStartTest, NullHandle) {
658 }
659 
660 TEST_F(ConditionerStartTest, ConditionerAlreadyStarted) {
661  EXPECT_READ32(ENTROPY_SRC_FW_OV_SHA3_START_REG_OFFSET, kMultiBitBool4True);
662  EXPECT_EQ(dif_entropy_src_conditioner_start(&entropy_src_), kDifUnavailable);
663 }
664 
665 TEST_F(ConditionerStartTest, Success) {
666  EXPECT_READ32(ENTROPY_SRC_FW_OV_SHA3_START_REG_OFFSET, kMultiBitBool4False);
667  EXPECT_WRITE32(ENTROPY_SRC_FW_OV_SHA3_START_REG_OFFSET, kMultiBitBool4True);
669 }
670 
672 
673 TEST_F(ConditionerStopTest, NullHandle) {
675 }
676 
677 TEST_F(ConditionerStopTest, Success) {
678  EXPECT_READ32(ENTROPY_SRC_FW_OV_WR_FIFO_FULL_REG_OFFSET, 0);
679  EXPECT_WRITE32(ENTROPY_SRC_FW_OV_SHA3_START_REG_OFFSET, kMultiBitBool4False);
681 }
682 
683 class IsFifoFullTest : public EntropySrcTest {};
684 
685 TEST_F(IsFifoFullTest, NullArgs) {
686  bool is_full;
688  EXPECT_DIF_BADARG(dif_entropy_src_is_fifo_full(&entropy_src_, nullptr));
690 }
691 
692 TEST_F(IsFifoFullTest, Success) {
693  bool is_full;
694 
695  EXPECT_READ32(ENTROPY_SRC_FW_OV_WR_FIFO_FULL_REG_OFFSET, 1);
696  EXPECT_DIF_OK(dif_entropy_src_is_fifo_full(&entropy_src_, &is_full));
697  EXPECT_TRUE(is_full);
698 
699  EXPECT_READ32(ENTROPY_SRC_FW_OV_WR_FIFO_FULL_REG_OFFSET, 0);
700  EXPECT_DIF_OK(dif_entropy_src_is_fifo_full(&entropy_src_, &is_full));
701  EXPECT_FALSE(is_full);
702 }
703 
705 
706 TEST_F(HasFifoOverflowedTest, NullArgs) {
707  bool has_overflowed;
709  dif_entropy_src_has_fifo_overflowed(nullptr, &has_overflowed));
711  dif_entropy_src_has_fifo_overflowed(&entropy_src_, nullptr));
713 }
714 
715 TEST_F(HasFifoOverflowedTest, Success) {
716  bool has_overflowed;
717 
718  EXPECT_READ32(ENTROPY_SRC_FW_OV_RD_FIFO_OVERFLOW_REG_OFFSET, 1);
720  dif_entropy_src_has_fifo_overflowed(&entropy_src_, &has_overflowed));
721  EXPECT_TRUE(has_overflowed);
722 
723  EXPECT_READ32(ENTROPY_SRC_FW_OV_RD_FIFO_OVERFLOW_REG_OFFSET, 0);
725  dif_entropy_src_has_fifo_overflowed(&entropy_src_, &has_overflowed));
726  EXPECT_FALSE(has_overflowed);
727 }
728 
730 
731 TEST_F(ReadFifoDepthTest, EntropyBadArg) {
732  uint32_t depth;
734 }
735 
736 TEST_F(ReadFifoDepthTest, DepthBadArg) {
737  EXPECT_DIF_BADARG(dif_entropy_src_get_fifo_depth(&entropy_src_, nullptr));
738 }
739 
740 TEST_F(ReadFifoDepthTest, ReadSuccess) {
741  EXPECT_READ32(ENTROPY_SRC_OBSERVE_FIFO_DEPTH_REG_OFFSET, 6);
742  uint32_t depth;
743  EXPECT_DIF_OK(dif_entropy_src_get_fifo_depth(&entropy_src_, &depth));
744  EXPECT_EQ(depth, 6);
745 }
746 
748 
749 TEST_F(GetDebugStateTest, NullArgs) {
750  dif_entropy_src_debug_state_t debug_state;
751  EXPECT_DIF_BADARG(dif_entropy_src_get_debug_state(nullptr, &debug_state));
752  EXPECT_DIF_BADARG(dif_entropy_src_get_debug_state(&entropy_src_, nullptr));
754 }
755 
756 TEST_F(GetDebugStateTest, Success) {
757  dif_entropy_src_debug_state_t debug_state;
758  EXPECT_READ32(
759  ENTROPY_SRC_DEBUG_STATUS_REG_OFFSET,
760  {{ENTROPY_SRC_DEBUG_STATUS_MAIN_SM_BOOT_DONE_BIT, 1},
761  {ENTROPY_SRC_DEBUG_STATUS_MAIN_SM_IDLE_BIT, 1},
762  {ENTROPY_SRC_DEBUG_STATUS_SHA3_ERR_BIT, 1},
763  {ENTROPY_SRC_DEBUG_STATUS_SHA3_ABSORBED_BIT, 1},
764  {ENTROPY_SRC_DEBUG_STATUS_SHA3_SQUEEZING_BIT, 1},
765  {ENTROPY_SRC_DEBUG_STATUS_SHA3_BLOCK_PR_BIT, 1},
766  {ENTROPY_SRC_DEBUG_STATUS_SHA3_FSM_OFFSET, kDifEntropySrcSha3StateFlush},
767  {ENTROPY_SRC_DEBUG_STATUS_ENTROPY_FIFO_DEPTH_OFFSET, 3}});
768  EXPECT_DIF_OK(dif_entropy_src_get_debug_state(&entropy_src_, &debug_state));
769  EXPECT_EQ(debug_state.entropy_fifo_depth, 3);
770  EXPECT_EQ(debug_state.sha3_fsm_state, kDifEntropySrcSha3StateFlush);
771  EXPECT_EQ(debug_state.sha3_block_processed, true);
772  EXPECT_EQ(debug_state.sha3_squeezing, true);
773  EXPECT_EQ(debug_state.sha3_absorbed, true);
774  EXPECT_EQ(debug_state.sha3_error, true);
775  EXPECT_EQ(debug_state.main_fsm_is_idle, true);
776  EXPECT_EQ(debug_state.main_fsm_boot_done, true);
777 }
778 
780 
781 TEST_F(GetRecoverableAlertsTest, NullArgs) {
782  uint32_t alerts;
785  dif_entropy_src_get_recoverable_alerts(&entropy_src_, nullptr));
787 }
788 
789 TEST_F(GetRecoverableAlertsTest, Success) {
790  uint32_t alerts;
791  EXPECT_READ32(ENTROPY_SRC_RECOV_ALERT_STS_REG_OFFSET,
794  EXPECT_DIF_OK(dif_entropy_src_get_recoverable_alerts(&entropy_src_, &alerts));
795  EXPECT_EQ(alerts, kDifEntropySrcAlertFwOvSha3StartField |
797 }
798 
800 
801 TEST_F(ClearRecoverableAlertsTest, NullHandle) {
802  uint32_t alerts = 0;
804 }
805 
806 TEST_F(ClearRecoverableAlertsTest, BadAlerts) {
807  uint32_t alerts = 1U << 19;
809  dif_entropy_src_clear_recoverable_alerts(&entropy_src_, alerts));
810 }
811 
812 TEST_F(ClearRecoverableAlertsTest, SuccessOneAlert) {
813  uint32_t alerts = kDifEntropySrcAlertRngBitEnableField;
814  EXPECT_READ32(ENTROPY_SRC_RECOV_ALERT_STS_REG_OFFSET, 0x2f);
815  EXPECT_WRITE32(ENTROPY_SRC_RECOV_ALERT_STS_REG_OFFSET, 0xf);
817  dif_entropy_src_clear_recoverable_alerts(&entropy_src_, alerts));
818 }
819 
820 TEST_F(ClearRecoverableAlertsTest, SuccessAllAlerts) {
821  uint32_t alerts = kDifEntropySrcAlertAllAlerts;
822  EXPECT_READ32(ENTROPY_SRC_RECOV_ALERT_STS_REG_OFFSET, 0x7faf);
823  EXPECT_WRITE32(ENTROPY_SRC_RECOV_ALERT_STS_REG_OFFSET, 0);
825  dif_entropy_src_clear_recoverable_alerts(&entropy_src_, alerts));
826 }
827 
828 class GetErrorsTest : public EntropySrcTest {};
829 
830 TEST_F(GetErrorsTest, NullArgs) {
831  uint32_t errors;
833  EXPECT_DIF_BADARG(dif_entropy_src_get_errors(&entropy_src_, nullptr));
835 }
836 
837 TEST_F(GetErrorsTest, Success) {
838  uint32_t errors;
839  EXPECT_READ32(ENTROPY_SRC_ERR_CODE_REG_OFFSET, 0x30000005);
840  EXPECT_DIF_OK(dif_entropy_src_get_errors(&entropy_src_, &errors));
841  EXPECT_EQ(errors, kDifEntropySrcErrorRngFifoWrite |
845 }
846 
847 class ForceErrorTest : public EntropySrcTest {};
848 
849 TEST_F(ForceErrorTest, NullHandle) {
852 }
853 
854 TEST_F(ForceErrorTest, BadError) {
856  &entropy_src_, static_cast<dif_entropy_src_error_t>(12)));
857 }
858 
859 TEST_F(ForceErrorTest, Success) {
860  EXPECT_WRITE32(ENTROPY_SRC_ERR_CODE_TEST_REG_OFFSET, 0);
863 
864  EXPECT_WRITE32(ENTROPY_SRC_ERR_CODE_TEST_REG_OFFSET,
865  ENTROPY_SRC_ERR_CODE_ES_CNTR_ERR_BIT);
867  &entropy_src_, kDifEntropySrcErrorHardenedCounter));
868 }
869 
871 
872 TEST_F(GetMainFsmStateTest, NullArgs) {
875  EXPECT_DIF_BADARG(dif_entropy_src_get_main_fsm_state(&entropy_src_, nullptr));
877 }
878 
879 TEST_F(GetMainFsmStateTest, Success) {
881 
882  EXPECT_READ32(ENTROPY_SRC_MAIN_SM_STATE_REG_OFFSET,
883  kDifEntropySrcMainFsmStateIdle);
884  EXPECT_DIF_OK(dif_entropy_src_get_main_fsm_state(&entropy_src_, &state));
885  EXPECT_EQ(state, kDifEntropySrcMainFsmStateIdle);
886 
887  EXPECT_READ32(ENTROPY_SRC_MAIN_SM_STATE_REG_OFFSET,
888  kDifEntropySrcMainFsmStateError);
889  EXPECT_DIF_OK(dif_entropy_src_get_main_fsm_state(&entropy_src_, &state));
890  EXPECT_EQ(state, kDifEntropySrcMainFsmStateError);
891 }
892 
893 } // namespace
894 } // namespace dif_entropy_src_unittest