7 #include "gtest/gtest.h"
9 #include "sw/device/lib/base/mock_mmio.h"
10 #include "sw/device/lib/base/multibits.h"
14 #include "entropy_src_regs.h"
16 namespace dif_entropy_src_unittest {
21 const dif_entropy_src_t entropy_src_ = {.base_addr = dev().region()};
30 .route_to_firmware =
false,
31 .bypass_conditioner =
false,
33 .health_test_window_size = 1};
41 TEST_F(ConfigTest, BadEnabled) {
46 TEST_F(ConfigTest, BadSingleBitMode) {
52 TEST_F(ConfigTest, Locked) {
53 EXPECT_READ32(ENTROPY_SRC_REGWEN_REG_OFFSET, 0);
63 bool route_to_firmware;
64 bool bypass_conditioner;
66 bool health_test_threshold_scope;
67 uint16_t health_test_window_size;
68 uint16_t alert_threshold;
73 public testing::WithParamInterface<ConfigParams> {};
77 config_.fips_enable = test_param.fips_enable;
78 config_.fips_flag = test_param.fips_flag;
79 config_.rng_fips = test_param.rng_fips;
80 config_.route_to_firmware = test_param.route_to_firmware;
81 config_.bypass_conditioner = test_param.bypass_conditioner;
82 config_.single_bit_mode = test_param.single_bit_mode;
83 config_.health_test_threshold_scope = test_param.health_test_threshold_scope;
84 config_.health_test_window_size = test_param.health_test_window_size;
85 config_.alert_threshold = test_param.alert_threshold;
87 EXPECT_READ32(ENTROPY_SRC_REGWEN_REG_OFFSET, 1);
89 multi_bit_bool_t route_to_firmware_mubi =
90 test_param.route_to_firmware ? kMultiBitBool4True : kMultiBitBool4False;
91 multi_bit_bool_t bypass_conditioner_mubi =
92 test_param.bypass_conditioner ? kMultiBitBool4True : kMultiBitBool4False;
95 ENTROPY_SRC_ENTROPY_CONTROL_REG_OFFSET,
97 {ENTROPY_SRC_ENTROPY_CONTROL_ES_ROUTE_OFFSET, route_to_firmware_mubi},
98 {ENTROPY_SRC_ENTROPY_CONTROL_ES_TYPE_OFFSET, bypass_conditioner_mubi},
101 multi_bit_bool_t fips_enable_mubi =
102 test_param.fips_enable ? kMultiBitBool4True : kMultiBitBool4False;
103 multi_bit_bool_t fips_flag_mubi =
104 test_param.fips_flag ? kMultiBitBool4True : kMultiBitBool4False;
105 multi_bit_bool_t rng_fips_mubi =
106 test_param.rng_fips ? kMultiBitBool4True : kMultiBitBool4False;
107 multi_bit_bool_t threshold_scope_mubi = test_param.health_test_threshold_scope
109 : kMultiBitBool4False;
110 multi_bit_bool_t rng_bit_enable_mubi =
112 ? kMultiBitBool4False
113 : kMultiBitBool4True;
114 uint8_t rng_bit_sel =
117 : test_param.single_bit_mode;
120 ENTROPY_SRC_CONF_REG_OFFSET,
122 {ENTROPY_SRC_CONF_FIPS_ENABLE_OFFSET, fips_enable_mubi},
123 {ENTROPY_SRC_CONF_ENTROPY_DATA_REG_ENABLE_OFFSET,
124 route_to_firmware_mubi},
125 {ENTROPY_SRC_CONF_FIPS_FLAG_OFFSET, fips_flag_mubi},
126 {ENTROPY_SRC_CONF_RNG_FIPS_OFFSET, rng_fips_mubi},
127 {ENTROPY_SRC_CONF_THRESHOLD_SCOPE_OFFSET, threshold_scope_mubi},
128 {ENTROPY_SRC_CONF_RNG_BIT_ENABLE_OFFSET, rng_bit_enable_mubi},
129 {ENTROPY_SRC_CONF_RNG_BIT_SEL_OFFSET, rng_bit_sel},
132 EXPECT_WRITE32(ENTROPY_SRC_HEALTH_TEST_WINDOWS_REG_OFFSET,
133 {{ENTROPY_SRC_HEALTH_TEST_WINDOWS_BYPASS_WINDOW_OFFSET,
134 ENTROPY_SRC_HEALTH_TEST_WINDOWS_REG_RESVAL >>
135 ENTROPY_SRC_HEALTH_TEST_WINDOWS_BYPASS_WINDOW_OFFSET},
136 {ENTROPY_SRC_HEALTH_TEST_WINDOWS_FIPS_WINDOW_OFFSET,
137 test_param.health_test_window_size}});
139 EXPECT_WRITE32(ENTROPY_SRC_ALERT_THRESHOLD_REG_OFFSET,
140 {{ENTROPY_SRC_ALERT_THRESHOLD_ALERT_THRESHOLD_INV_OFFSET,
141 static_cast<decltype(test_param.alert_threshold)
>(
142 ~test_param.alert_threshold)},
143 {ENTROPY_SRC_ALERT_THRESHOLD_ALERT_THRESHOLD_OFFSET,
144 test_param.alert_threshold}});
146 EXPECT_WRITE32(ENTROPY_SRC_MODULE_ENABLE_REG_OFFSET,
148 {ENTROPY_SRC_MODULE_ENABLE_MODULE_ENABLE_OFFSET,
156 INSTANTIATE_TEST_SUITE_P(ConfigTestAllParams, ConfigTestAllParams,
159 ConfigParams{
true,
true,
true,
false,
false,
163 ConfigParams{
false,
true,
true,
true,
false,
167 ConfigParams{
false,
false,
false,
false,
true,
171 ConfigParams{
false,
true,
true,
false,
false,
174 ConfigParams{
false,
true,
true,
false,
false,
177 ConfigParams{
false,
true,
true,
false,
false,
180 ConfigParams{
false,
true,
true,
false,
false,
184 ConfigParams{
false,
false,
false,
false,
false,
188 ConfigParams{
false,
false,
false,
false,
false,
192 ConfigParams{
true,
true,
true,
true,
false,
200 .buffer_threshold = ENTROPY_SRC_OBSERVE_FIFO_THRESH_REG_RESVAL,
209 TEST_F(FwOverrideConfigTest, BadBufferThreshold) {
210 config_.buffer_threshold =
211 ENTROPY_SRC_OBSERVE_FIFO_THRESH_OBSERVE_FIFO_THRESH_MASK + 1;
215 config_.buffer_threshold = 0;
220 TEST_F(FwOverrideConfigTest, BadEnabled) {
225 TEST_F(FwOverrideConfigTest, Locked) {
226 EXPECT_READ32(ENTROPY_SRC_REGWEN_REG_OFFSET, 0);
232 TEST_F(FwOverrideConfigTest, Success) {
233 EXPECT_READ32(ENTROPY_SRC_REGWEN_REG_OFFSET, 1);
234 EXPECT_WRITE32(ENTROPY_SRC_OBSERVE_FIFO_THRESH_REG_OFFSET,
235 config_.buffer_threshold);
236 EXPECT_WRITE32(ENTROPY_SRC_FW_OV_CONTROL_REG_OFFSET, 0x66);
240 EXPECT_READ32(ENTROPY_SRC_REGWEN_REG_OFFSET, 1);
241 EXPECT_WRITE32(ENTROPY_SRC_OBSERVE_FIFO_THRESH_REG_OFFSET,
242 config_.buffer_threshold);
243 EXPECT_WRITE32(ENTROPY_SRC_FW_OV_CONTROL_REG_OFFSET, 0x69);
252 .high_threshold = 0xFFFF,
261 TEST_F(HealthTestConfigTest, Locked) {
262 EXPECT_READ32(ENTROPY_SRC_REGWEN_REG_OFFSET, 0);
267 TEST_F(HealthTestConfigTest, BadTestType) {
268 config_.test_type = kDifEntropySrcTestNumVariants;
269 EXPECT_READ32(ENTROPY_SRC_REGWEN_REG_OFFSET, 1);
274 TEST_F(HealthTestConfigTest, BadLowThreshold) {
275 config_.low_threshold = 0x1;
276 EXPECT_READ32(ENTROPY_SRC_REGWEN_REG_OFFSET, 1);
281 TEST_F(HealthTestConfigTest, SuccessOneThreshold) {
282 EXPECT_READ32(ENTROPY_SRC_REGWEN_REG_OFFSET, 1);
283 EXPECT_WRITE32(ENTROPY_SRC_REPCNT_THRESHOLDS_REG_OFFSET,
284 config_.high_threshold);
288 TEST_F(HealthTestConfigTest, SuccessTwoThresholds) {
290 config_.low_threshold = 0xABAB;
291 EXPECT_READ32(ENTROPY_SRC_REGWEN_REG_OFFSET, 1);
292 EXPECT_WRITE32(ENTROPY_SRC_MARKOV_HI_THRESHOLDS_REG_OFFSET,
293 config_.high_threshold);
294 EXPECT_WRITE32(ENTROPY_SRC_MARKOV_LO_THRESHOLDS_REG_OFFSET,
295 config_.low_threshold);
305 TEST_F(SetEnabledTest, BadToggle) {
310 TEST_F(SetEnabledTest, Locked) {
311 EXPECT_READ32(ENTROPY_SRC_ME_REGWEN_REG_OFFSET, 0);
316 TEST_F(SetEnabledTest, Success) {
318 EXPECT_READ32(ENTROPY_SRC_ME_REGWEN_REG_OFFSET, 1);
319 EXPECT_WRITE32(ENTROPY_SRC_MODULE_ENABLE_REG_OFFSET, kMultiBitBool4True);
323 EXPECT_READ32(ENTROPY_SRC_ME_REGWEN_REG_OFFSET, 1);
324 EXPECT_WRITE32(ENTROPY_SRC_MODULE_ENABLE_REG_OFFSET, kMultiBitBool4False);
334 TEST_F(LockTest, Success) {
335 EXPECT_WRITE32(ENTROPY_SRC_ME_REGWEN_REG_OFFSET, 0);
336 EXPECT_WRITE32(ENTROPY_SRC_SW_REGUPD_REG_OFFSET, 0);
349 TEST_F(IsLockedTest, BadState) {
351 EXPECT_READ32(ENTROPY_SRC_ME_REGWEN_REG_OFFSET, 1);
352 EXPECT_READ32(ENTROPY_SRC_SW_REGUPD_REG_OFFSET, 0);
355 EXPECT_READ32(ENTROPY_SRC_ME_REGWEN_REG_OFFSET, 0);
356 EXPECT_READ32(ENTROPY_SRC_SW_REGUPD_REG_OFFSET, 1);
360 TEST_F(IsLockedTest, Success) {
362 EXPECT_READ32(ENTROPY_SRC_ME_REGWEN_REG_OFFSET, 0);
363 EXPECT_READ32(ENTROPY_SRC_SW_REGUPD_REG_OFFSET, 0);
365 EXPECT_TRUE(is_locked);
367 EXPECT_READ32(ENTROPY_SRC_ME_REGWEN_REG_OFFSET, 1);
368 EXPECT_READ32(ENTROPY_SRC_SW_REGUPD_REG_OFFSET, 1);
370 EXPECT_FALSE(is_locked);
383 TEST_F(HealthTestStatsGetTest, Success) {
386 EXPECT_READ32(ENTROPY_SRC_REPCNT_HI_WATERMARKS_REG_OFFSET, 10);
387 EXPECT_READ32(ENTROPY_SRC_REPCNT_TOTAL_FAILS_REG_OFFSET, 10);
389 EXPECT_READ32(ENTROPY_SRC_REPCNTS_HI_WATERMARKS_REG_OFFSET, 10);
390 EXPECT_READ32(ENTROPY_SRC_REPCNTS_TOTAL_FAILS_REG_OFFSET, 10);
392 EXPECT_READ32(ENTROPY_SRC_ADAPTP_HI_WATERMARKS_REG_OFFSET, 10);
393 EXPECT_READ32(ENTROPY_SRC_ADAPTP_LO_WATERMARKS_REG_OFFSET, 10);
394 EXPECT_READ32(ENTROPY_SRC_ADAPTP_HI_TOTAL_FAILS_REG_OFFSET, 10);
395 EXPECT_READ32(ENTROPY_SRC_ADAPTP_LO_TOTAL_FAILS_REG_OFFSET, 10);
397 EXPECT_READ32(ENTROPY_SRC_BUCKET_HI_WATERMARKS_REG_OFFSET, 10);
398 EXPECT_READ32(ENTROPY_SRC_BUCKET_TOTAL_FAILS_REG_OFFSET, 10);
400 EXPECT_READ32(ENTROPY_SRC_MARKOV_HI_WATERMARKS_REG_OFFSET, 10);
401 EXPECT_READ32(ENTROPY_SRC_MARKOV_LO_WATERMARKS_REG_OFFSET, 10);
402 EXPECT_READ32(ENTROPY_SRC_MARKOV_HI_TOTAL_FAILS_REG_OFFSET, 10);
403 EXPECT_READ32(ENTROPY_SRC_MARKOV_LO_TOTAL_FAILS_REG_OFFSET, 10);
405 EXPECT_READ32(ENTROPY_SRC_EXTHT_HI_WATERMARKS_REG_OFFSET, 10);
406 EXPECT_READ32(ENTROPY_SRC_EXTHT_LO_WATERMARKS_REG_OFFSET, 10);
407 EXPECT_READ32(ENTROPY_SRC_EXTHT_HI_TOTAL_FAILS_REG_OFFSET, 10);
408 EXPECT_READ32(ENTROPY_SRC_EXTHT_LO_TOTAL_FAILS_REG_OFFSET, 10);
411 for (uint32_t i = 0; i < kDifEntropySrcTestNumVariants; ++i) {
413 if (i == 2 || i == 4 || i == 5) {
420 if (i == 2 || i == 4 || i == 5) {
438 TEST_F(GetAlertFailCountsTest, Success) {
441 EXPECT_READ32(ENTROPY_SRC_ALERT_SUMMARY_FAIL_COUNTS_REG_OFFSET, 128);
443 ENTROPY_SRC_ALERT_FAIL_COUNTS_REG_OFFSET,
444 {{ENTROPY_SRC_ALERT_FAIL_COUNTS_REPCNT_FAIL_COUNT_OFFSET, 0xA},
445 {ENTROPY_SRC_ALERT_FAIL_COUNTS_ADAPTP_HI_FAIL_COUNT_OFFSET, 0xC},
446 {ENTROPY_SRC_ALERT_FAIL_COUNTS_ADAPTP_LO_FAIL_COUNT_OFFSET, 0xC},
447 {ENTROPY_SRC_ALERT_FAIL_COUNTS_BUCKET_FAIL_COUNT_OFFSET, 0xD},
448 {ENTROPY_SRC_ALERT_FAIL_COUNTS_MARKOV_HI_FAIL_COUNT_OFFSET, 0xE},
449 {ENTROPY_SRC_ALERT_FAIL_COUNTS_MARKOV_LO_FAIL_COUNT_OFFSET, 0xE},
450 {ENTROPY_SRC_ALERT_FAIL_COUNTS_REPCNTS_FAIL_COUNT_OFFSET, 0xB}});
452 ENTROPY_SRC_EXTHT_FAIL_COUNTS_REG_OFFSET,
453 {{ENTROPY_SRC_EXTHT_FAIL_COUNTS_EXTHT_HI_FAIL_COUNT_OFFSET, 0xF},
454 {ENTROPY_SRC_EXTHT_FAIL_COUNTS_EXTHT_LO_FAIL_COUNT_OFFSET, 0xF}});
457 uint8_t num_fails = 0xA;
458 for (uint32_t i = 0; i < kDifEntropySrcTestNumVariants; ++i) {
460 if (i == 2 || i == 4 || i == 5) {
461 EXPECT_EQ(counts.
low_fails[i], num_fails);
475 TEST_F(IsEntropyAvailableTest, Unavailable) {
476 EXPECT_READ32(ENTROPY_SRC_INTR_STATE_REG_OFFSET,
477 {{ENTROPY_SRC_INTR_STATE_ES_ENTROPY_VALID_BIT,
false}});
482 TEST_F(IsEntropyAvailableTest, Available) {
483 EXPECT_READ32(ENTROPY_SRC_INTR_STATE_REG_OFFSET,
484 {{ENTROPY_SRC_INTR_STATE_ES_ENTROPY_VALID_BIT,
true}});
497 TEST_F(NonBlockingReadTest, DataUnavailable) {
498 EXPECT_READ32(ENTROPY_SRC_INTR_STATE_REG_OFFSET, 0);
504 TEST_F(NonBlockingReadTest, Success) {
505 const uint32_t expected_word = 0x65585497;
506 EXPECT_READ32(ENTROPY_SRC_INTR_STATE_REG_OFFSET,
507 1 << ENTROPY_SRC_INTR_STATE_ES_ENTROPY_VALID_BIT);
508 EXPECT_READ32(ENTROPY_SRC_ENTROPY_DATA_REG_OFFSET, expected_word);
509 EXPECT_READ32(ENTROPY_SRC_INTR_STATE_REG_OFFSET,
510 1 << ENTROPY_SRC_INTR_STATE_ES_ENTROPY_VALID_BIT);
511 EXPECT_WRITE32(ENTROPY_SRC_INTR_STATE_REG_OFFSET,
512 {{ENTROPY_SRC_INTR_STATE_ES_ENTROPY_VALID_BIT,
true}});
516 EXPECT_EQ(word, expected_word);
527 TEST_F(ObserveFifoBlockingReadTest, BadLength) {
529 EXPECT_READ32(ENTROPY_SRC_OBSERVE_FIFO_THRESH_REG_OFFSET, 7);
534 TEST_F(ObserveFifoBlockingReadTest, BadConfig) {
536 EXPECT_READ32(ENTROPY_SRC_OBSERVE_FIFO_THRESH_REG_OFFSET, 8);
538 ENTROPY_SRC_FW_OV_CONTROL_REG_OFFSET,
539 {{ENTROPY_SRC_FW_OV_CONTROL_FW_OV_ENTROPY_INSERT_OFFSET,
540 kMultiBitBool4False},
541 {ENTROPY_SRC_FW_OV_CONTROL_FW_OV_MODE_OFFSET, kMultiBitBool4False}});
546 TEST_F(ObserveFifoBlockingReadTest, SuccessDataThroughAway) {
547 uint32_t buf[4] = {0};
548 EXPECT_READ32(ENTROPY_SRC_OBSERVE_FIFO_THRESH_REG_OFFSET, 4);
550 ENTROPY_SRC_FW_OV_CONTROL_REG_OFFSET,
551 {{ENTROPY_SRC_FW_OV_CONTROL_FW_OV_ENTROPY_INSERT_OFFSET,
552 kMultiBitBool4False},
553 {ENTROPY_SRC_FW_OV_CONTROL_FW_OV_MODE_OFFSET, kMultiBitBool4True}});
554 EXPECT_READ32(ENTROPY_SRC_INTR_STATE_REG_OFFSET,
555 {{ENTROPY_SRC_INTR_STATE_ES_OBSERVE_FIFO_READY_BIT, 1}});
556 for (
size_t i = 0; i < 4; ++i) {
557 EXPECT_READ32(ENTROPY_SRC_FW_OV_RD_DATA_REG_OFFSET, i);
559 EXPECT_WRITE32(ENTROPY_SRC_INTR_STATE_REG_OFFSET,
560 {{ENTROPY_SRC_INTR_STATE_ES_OBSERVE_FIFO_READY_BIT, 1}});
563 for (
size_t i = 0; i < 4; ++i) {
564 EXPECT_EQ(buf[i], 0);
568 TEST_F(ObserveFifoBlockingReadTest, SuccessDataSave) {
570 EXPECT_READ32(ENTROPY_SRC_OBSERVE_FIFO_THRESH_REG_OFFSET, 4);
572 ENTROPY_SRC_FW_OV_CONTROL_REG_OFFSET,
573 {{ENTROPY_SRC_FW_OV_CONTROL_FW_OV_ENTROPY_INSERT_OFFSET,
574 kMultiBitBool4False},
575 {ENTROPY_SRC_FW_OV_CONTROL_FW_OV_MODE_OFFSET, kMultiBitBool4True}});
576 EXPECT_READ32(ENTROPY_SRC_INTR_STATE_REG_OFFSET,
577 {{ENTROPY_SRC_INTR_STATE_ES_OBSERVE_FIFO_READY_BIT, 1}});
578 for (
size_t i = 0; i < 4; ++i) {
579 EXPECT_READ32(ENTROPY_SRC_FW_OV_RD_DATA_REG_OFFSET, i);
581 EXPECT_WRITE32(ENTROPY_SRC_INTR_STATE_REG_OFFSET,
582 {{ENTROPY_SRC_INTR_STATE_ES_OBSERVE_FIFO_READY_BIT, 1}});
585 for (
size_t i = 0; i < 4; ++i) {
586 EXPECT_EQ(buf[i], i);
593 uint32_t buf[8] = {0};
601 TEST_F(ObserveFifoWriteTest, BadConfig) {
606 ENTROPY_SRC_FW_OV_CONTROL_REG_OFFSET,
607 {{ENTROPY_SRC_FW_OV_CONTROL_FW_OV_ENTROPY_INSERT_OFFSET,
608 kMultiBitBool4False},
609 {ENTROPY_SRC_FW_OV_CONTROL_FW_OV_MODE_OFFSET, kMultiBitBool4False}});
615 ENTROPY_SRC_FW_OV_CONTROL_REG_OFFSET,
616 {{ENTROPY_SRC_FW_OV_CONTROL_FW_OV_ENTROPY_INSERT_OFFSET,
617 kMultiBitBool4False},
618 {ENTROPY_SRC_FW_OV_CONTROL_FW_OV_MODE_OFFSET, kMultiBitBool4True}});
623 TEST_F(ObserveFifoWriteTest, FifoFull) {
627 ENTROPY_SRC_FW_OV_CONTROL_REG_OFFSET,
628 {{ENTROPY_SRC_FW_OV_CONTROL_FW_OV_ENTROPY_INSERT_OFFSET,
630 {ENTROPY_SRC_FW_OV_CONTROL_FW_OV_MODE_OFFSET, kMultiBitBool4True}});
631 EXPECT_READ32(ENTROPY_SRC_FW_OV_WR_FIFO_FULL_REG_OFFSET, 1);
634 EXPECT_EQ(written, 0);
637 TEST_F(ObserveFifoWriteTest, Success) {
638 uint32_t buf[4] = {1, 2, 3, 4};
641 ENTROPY_SRC_FW_OV_CONTROL_REG_OFFSET,
642 {{ENTROPY_SRC_FW_OV_CONTROL_FW_OV_ENTROPY_INSERT_OFFSET,
644 {ENTROPY_SRC_FW_OV_CONTROL_FW_OV_MODE_OFFSET, kMultiBitBool4True}});
645 for (
size_t i = 0; i < 4; ++i) {
646 EXPECT_READ32(ENTROPY_SRC_FW_OV_WR_FIFO_FULL_REG_OFFSET, 0);
647 EXPECT_WRITE32(ENTROPY_SRC_FW_OV_WR_DATA_REG_OFFSET, i + 1);
651 EXPECT_EQ(written, 4);
660 TEST_F(ConditionerStartTest, ConditionerAlreadyStarted) {
661 EXPECT_READ32(ENTROPY_SRC_FW_OV_SHA3_START_REG_OFFSET, kMultiBitBool4True);
665 TEST_F(ConditionerStartTest, Success) {
666 EXPECT_READ32(ENTROPY_SRC_FW_OV_SHA3_START_REG_OFFSET, kMultiBitBool4False);
667 EXPECT_WRITE32(ENTROPY_SRC_FW_OV_SHA3_START_REG_OFFSET, kMultiBitBool4True);
677 TEST_F(ConditionerStopTest, Success) {
678 EXPECT_READ32(ENTROPY_SRC_FW_OV_WR_FIFO_FULL_REG_OFFSET, 0);
679 EXPECT_WRITE32(ENTROPY_SRC_FW_OV_SHA3_START_REG_OFFSET, kMultiBitBool4False);
692 TEST_F(IsFifoFullTest, Success) {
695 EXPECT_READ32(ENTROPY_SRC_FW_OV_WR_FIFO_FULL_REG_OFFSET, 1);
697 EXPECT_TRUE(is_full);
699 EXPECT_READ32(ENTROPY_SRC_FW_OV_WR_FIFO_FULL_REG_OFFSET, 0);
701 EXPECT_FALSE(is_full);
715 TEST_F(HasFifoOverflowedTest, Success) {
718 EXPECT_READ32(ENTROPY_SRC_FW_OV_RD_FIFO_OVERFLOW_REG_OFFSET, 1);
721 EXPECT_TRUE(has_overflowed);
723 EXPECT_READ32(ENTROPY_SRC_FW_OV_RD_FIFO_OVERFLOW_REG_OFFSET, 0);
726 EXPECT_FALSE(has_overflowed);
736 TEST_F(ReadFifoDepthTest, DepthBadArg) {
740 TEST_F(ReadFifoDepthTest, ReadSuccess) {
741 EXPECT_READ32(ENTROPY_SRC_OBSERVE_FIFO_DEPTH_REG_OFFSET, 6);
756 TEST_F(GetDebugStateTest, Success) {
759 ENTROPY_SRC_DEBUG_STATUS_REG_OFFSET,
760 {{ENTROPY_SRC_DEBUG_STATUS_MAIN_SM_BOOT_DONE_BIT, 1},
761 {ENTROPY_SRC_DEBUG_STATUS_MAIN_SM_IDLE_BIT, 1},
762 {ENTROPY_SRC_DEBUG_STATUS_SHA3_ERR_BIT, 1},
763 {ENTROPY_SRC_DEBUG_STATUS_SHA3_ABSORBED_BIT, 1},
764 {ENTROPY_SRC_DEBUG_STATUS_SHA3_SQUEEZING_BIT, 1},
765 {ENTROPY_SRC_DEBUG_STATUS_SHA3_BLOCK_PR_BIT, 1},
766 {ENTROPY_SRC_DEBUG_STATUS_SHA3_FSM_OFFSET, kDifEntropySrcSha3StateFlush},
767 {ENTROPY_SRC_DEBUG_STATUS_ENTROPY_FIFO_DEPTH_OFFSET, 3}});
770 EXPECT_EQ(debug_state.
sha3_fsm_state, kDifEntropySrcSha3StateFlush);
789 TEST_F(GetRecoverableAlertsTest, Success) {
791 EXPECT_READ32(ENTROPY_SRC_RECOV_ALERT_STS_REG_OFFSET,
806 TEST_F(ClearRecoverableAlertsTest, BadAlerts) {
807 uint32_t alerts = 1U << 19;
812 TEST_F(ClearRecoverableAlertsTest, SuccessOneAlert) {
814 EXPECT_READ32(ENTROPY_SRC_RECOV_ALERT_STS_REG_OFFSET, 0x2f);
815 EXPECT_WRITE32(ENTROPY_SRC_RECOV_ALERT_STS_REG_OFFSET, 0xf);
820 TEST_F(ClearRecoverableAlertsTest, SuccessAllAlerts) {
822 EXPECT_READ32(ENTROPY_SRC_RECOV_ALERT_STS_REG_OFFSET, 0x7faf);
823 EXPECT_WRITE32(ENTROPY_SRC_RECOV_ALERT_STS_REG_OFFSET, 0);
837 TEST_F(GetErrorsTest, Success) {
839 EXPECT_READ32(ENTROPY_SRC_ERR_CODE_REG_OFFSET, 0x30000005);
854 TEST_F(ForceErrorTest, BadError) {
859 TEST_F(ForceErrorTest, Success) {
860 EXPECT_WRITE32(ENTROPY_SRC_ERR_CODE_TEST_REG_OFFSET, 0);
864 EXPECT_WRITE32(ENTROPY_SRC_ERR_CODE_TEST_REG_OFFSET,
865 ENTROPY_SRC_ERR_CODE_ES_CNTR_ERR_BIT);
879 TEST_F(GetMainFsmStateTest, Success) {
882 EXPECT_READ32(ENTROPY_SRC_MAIN_SM_STATE_REG_OFFSET,
883 kDifEntropySrcMainFsmStateIdle);
885 EXPECT_EQ(state, kDifEntropySrcMainFsmStateIdle);
887 EXPECT_READ32(ENTROPY_SRC_MAIN_SM_STATE_REG_OFFSET,
888 kDifEntropySrcMainFsmStateError);
890 EXPECT_EQ(state, kDifEntropySrcMainFsmStateError);