182 dif_entropy_src_irq_t irq,
185 if (entropy_src == NULL || is_pending == NULL) {
190 if (!entropy_src_get_irq_bit_index(irq, &index)) {
194 uint32_t intr_state_reg = mmio_region_read32(
196 (ptrdiff_t)ENTROPY_SRC_INTR_STATE_REG_OFFSET);
199 *is_pending = bitfield_bit32_read(intr_state_reg, index);
226 dif_entropy_src_irq_t irq) {
228 if (entropy_src == NULL) {
233 if (!entropy_src_get_irq_bit_index(irq, &index)) {
238 uint32_t intr_state_reg = bitfield_bit32_write(0, index,
true);
241 (ptrdiff_t)ENTROPY_SRC_INTR_STATE_REG_OFFSET,
251 dif_entropy_src_irq_t irq,
254 if (entropy_src == NULL) {
259 if (!entropy_src_get_irq_bit_index(irq, &index)) {
263 uint32_t intr_test_reg = bitfield_bit32_write(0, index, val);
266 (ptrdiff_t)ENTROPY_SRC_INTR_TEST_REG_OFFSET,
276 dif_entropy_src_irq_t irq,
279 if (entropy_src == NULL || state == NULL) {
284 if (!entropy_src_get_irq_bit_index(irq, &index)) {
288 uint32_t intr_enable_reg = mmio_region_read32(
290 (ptrdiff_t)ENTROPY_SRC_INTR_ENABLE_REG_OFFSET);
293 bool is_enabled = bitfield_bit32_read(intr_enable_reg, index);
294 *state = is_enabled ?
303 dif_entropy_src_irq_t irq,
306 if (entropy_src == NULL) {
311 if (!entropy_src_get_irq_bit_index(irq, &index)) {
315 uint32_t intr_enable_reg = mmio_region_read32(
317 (ptrdiff_t)ENTROPY_SRC_INTR_ENABLE_REG_OFFSET);
321 intr_enable_reg = bitfield_bit32_write(intr_enable_reg, index, enable_bit);
324 (ptrdiff_t)ENTROPY_SRC_INTR_ENABLE_REG_OFFSET,