Software APIs
dif_edn_unittest.cc
1 // Copyright lowRISC contributors (OpenTitan project).
2 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3 // SPDX-License-Identifier: Apache-2.0
4 
5 #include "sw/device/lib/dif/dif_edn.h"
6 
7 #include <array>
8 #include <vector>
9 
10 #include "gtest/gtest.h"
11 #include "sw/device/lib/base/mmio.h"
12 #include "sw/device/lib/base/mock_mmio.h"
13 #include "sw/device/lib/dif/dif_test_base.h"
14 
15 #include "edn_regs.h" // Generated
16 
17 namespace dif_edn_unittest {
18 namespace {
19 
20 using ::testing::ElementsAreArray;
21 
22 class DifEdnTest : public testing::Test, public mock_mmio::MmioTest {
23  protected:
24  const dif_edn_t edn_ = {.base_addr = dev().region()};
25 };
26 
27 class ConfigTest : public DifEdnTest {};
28 
29 TEST_F(ConfigTest, BadArgs) { EXPECT_DIF_BADARG(dif_edn_configure(nullptr)); }
30 
31 TEST_F(ConfigTest, ConfigOk) {
32  EXPECT_READ32(EDN_REGWEN_REG_OFFSET, 1);
33  EXPECT_MASK32(EDN_CTRL_REG_OFFSET,
34  {
35  {EDN_CTRL_EDN_ENABLE_OFFSET, 0xf, kMultiBitBool4True},
36  });
37  EXPECT_DIF_OK(dif_edn_configure(&edn_));
38 }
39 
40 TEST_F(ConfigTest, Locked) {
41  EXPECT_READ32(EDN_REGWEN_REG_OFFSET, 0);
42  EXPECT_EQ(dif_edn_configure(&edn_), kDifLocked);
43 }
44 
45 class LockTest : public DifEdnTest {};
46 
47 TEST_F(LockTest, BadArgs) {
48  bool flag;
49  EXPECT_DIF_BADARG(dif_edn_lock(nullptr));
50  EXPECT_DIF_BADARG(dif_edn_is_locked(nullptr, &flag));
51  EXPECT_DIF_BADARG(dif_edn_is_locked(&edn_, nullptr));
52 }
53 
54 TEST_F(LockTest, Lock) {
55  EXPECT_WRITE32(EDN_REGWEN_REG_OFFSET, 0);
56  EXPECT_DIF_OK(dif_edn_lock(&edn_));
57 }
58 
59 TEST_F(LockTest, IsLocked) {
60  bool flag;
61 
62  EXPECT_READ32(EDN_REGWEN_REG_OFFSET, 1);
63  EXPECT_DIF_OK(dif_edn_is_locked(&edn_, &flag));
64  EXPECT_FALSE(flag);
65 
66  EXPECT_READ32(EDN_REGWEN_REG_OFFSET, 0);
67  EXPECT_DIF_OK(dif_edn_is_locked(&edn_, &flag));
68  EXPECT_TRUE(flag);
69 }
70 
71 class SetModeTest : public DifEdnTest {};
72 
73 TEST_F(SetModeTest, BadArgs) {
74  EXPECT_DIF_BADARG(dif_edn_set_boot_mode(nullptr));
75  EXPECT_DIF_BADARG(dif_edn_set_auto_mode(nullptr, {}));
76 }
77 
78 TEST_F(SetModeTest, Boot) {
79  EXPECT_READ32(EDN_REGWEN_REG_OFFSET, 1);
80  EXPECT_MASK32(EDN_CTRL_REG_OFFSET,
81  {
82  {EDN_CTRL_BOOT_REQ_MODE_OFFSET, 0xf, kMultiBitBool4True},
83  });
84  EXPECT_DIF_OK(dif_edn_set_boot_mode(&edn_));
85 }
86 
87 TEST_F(SetModeTest, Auto) {
88  EXPECT_READ32(EDN_REGWEN_REG_OFFSET, 1);
89 
90  EXPECT_READ32(EDN_CTRL_REG_OFFSET, EDN_CTRL_REG_RESVAL);
91  EXPECT_WRITE32(EDN_CTRL_REG_OFFSET,
92  {
93  {EDN_CTRL_EDN_ENABLE_OFFSET, kMultiBitBool4False},
94  {EDN_CTRL_BOOT_REQ_MODE_OFFSET, kMultiBitBool4False},
95  {EDN_CTRL_AUTO_REQ_MODE_OFFSET, kMultiBitBool4False},
96  {EDN_CTRL_CMD_FIFO_RST_OFFSET, kMultiBitBool4False},
97  });
98  EXPECT_WRITE32(EDN_CTRL_REG_OFFSET,
99  {
100  {EDN_CTRL_EDN_ENABLE_OFFSET, kMultiBitBool4False},
101  {EDN_CTRL_BOOT_REQ_MODE_OFFSET, kMultiBitBool4False},
102  {EDN_CTRL_AUTO_REQ_MODE_OFFSET, kMultiBitBool4False},
103  {EDN_CTRL_CMD_FIFO_RST_OFFSET, kMultiBitBool4True},
104  });
105  EXPECT_WRITE32(EDN_CTRL_REG_OFFSET,
106  {
107  {EDN_CTRL_EDN_ENABLE_OFFSET, kMultiBitBool4False},
108  {EDN_CTRL_BOOT_REQ_MODE_OFFSET, kMultiBitBool4False},
109  {EDN_CTRL_AUTO_REQ_MODE_OFFSET, kMultiBitBool4False},
110  {EDN_CTRL_CMD_FIFO_RST_OFFSET, kMultiBitBool4False},
111  });
112 
113  dif_edn_auto_params_t params = {
114  .instantiate_cmd = {.cmd = 1 | kMultiBitBool4False << 8,
115  .seed_material =
116  {
117  .len = 3,
118  .data = {1, 2, 3},
119  }},
120  .reseed_cmd = {.cmd = 11,
121  .seed_material =
122  {
123  .len = 4,
124  .data = {4, 5, 6, 7},
125  }},
126  .generate_cmd = {.cmd = 12,
127  .seed_material =
128  {
129  .len = 5,
130  .data = {8, 9, 10, 11, 12},
131  }},
132  .reseed_interval = 42,
133  };
134 
135  EXPECT_WRITE32(EDN_RESEED_CMD_REG_OFFSET, params.reseed_cmd.cmd);
136  for (size_t i = 0; i < params.reseed_cmd.seed_material.len; ++i) {
137  EXPECT_WRITE32(EDN_RESEED_CMD_REG_OFFSET,
138  params.reseed_cmd.seed_material.data[i]);
139  }
140  EXPECT_WRITE32(EDN_GENERATE_CMD_REG_OFFSET, params.generate_cmd.cmd);
141  for (size_t i = 0; i < params.generate_cmd.seed_material.len; ++i) {
142  EXPECT_WRITE32(EDN_GENERATE_CMD_REG_OFFSET,
143  params.generate_cmd.seed_material.data[i]);
144  }
145  EXPECT_WRITE32(EDN_MAX_NUM_REQS_BETWEEN_RESEEDS_REG_OFFSET,
146  params.reseed_interval);
147 
148  EXPECT_WRITE32(EDN_CTRL_REG_OFFSET,
149  {
150  {EDN_CTRL_EDN_ENABLE_OFFSET, kMultiBitBool4True},
151  {EDN_CTRL_BOOT_REQ_MODE_OFFSET, kMultiBitBool4False},
152  {EDN_CTRL_AUTO_REQ_MODE_OFFSET, kMultiBitBool4True},
153  {EDN_CTRL_CMD_FIFO_RST_OFFSET, kMultiBitBool4False},
154  });
155 
156  EXPECT_READ32(EDN_SW_CMD_STS_REG_OFFSET,
157  {{EDN_SW_CMD_STS_CMD_RDY_BIT, true}});
158  EXPECT_READ32(EDN_SW_CMD_STS_REG_OFFSET,
159  {{EDN_SW_CMD_STS_CMD_RDY_BIT, true}});
160 
161  EXPECT_WRITE32(EDN_SW_CMD_REQ_REG_OFFSET,
162  1 | params.instantiate_cmd.seed_material.len << 4 |
163  kMultiBitBool4False << 8);
164  for (size_t i = 0; i < params.instantiate_cmd.seed_material.len; ++i) {
165  EXPECT_READ32(EDN_SW_CMD_STS_REG_OFFSET,
166  {{EDN_SW_CMD_STS_CMD_REG_RDY_BIT, true}});
167  EXPECT_WRITE32(EDN_SW_CMD_REQ_REG_OFFSET,
168  params.instantiate_cmd.seed_material.data[i]);
169  }
170 
171  EXPECT_READ32(EDN_SW_CMD_STS_REG_OFFSET,
172  {{EDN_SW_CMD_STS_CMD_ACK_BIT, true}});
173 
174  uint32_t ctrl_reg = 0;
175  ctrl_reg = bitfield_bit32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_RDY_BIT, 1);
176  ctrl_reg = bitfield_bit32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_REG_RDY_BIT, 1);
177  ctrl_reg =
178  bitfield_field32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_STS_FIELD, 0x0);
179  ctrl_reg = bitfield_bit32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_ACK_BIT, 1);
180  EXPECT_READ32(EDN_SW_CMD_STS_REG_OFFSET, ctrl_reg);
181 
182  EXPECT_DIF_OK(dif_edn_set_auto_mode(&edn_, params));
183 }
184 
185 TEST_F(SetModeTest, Locked) {
186  EXPECT_READ32(EDN_REGWEN_REG_OFFSET, 0);
187  EXPECT_READ32(EDN_REGWEN_REG_OFFSET, 0);
188  EXPECT_EQ(dif_edn_set_boot_mode(&edn_), kDifLocked);
189  EXPECT_EQ(dif_edn_set_auto_mode(&edn_, {}), kDifLocked);
190 }
191 
192 class GetStatusTest : public DifEdnTest {};
193 
194 TEST_F(GetStatusTest, BadArgs) {
195  bool flag;
196  uint32_t ctrl_reg = 0;
197  EXPECT_DIF_BADARG(dif_edn_get_status(nullptr, kDifEdnStatusReady, &flag));
198 
199  ctrl_reg = bitfield_bit32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_RDY_BIT, 1);
200  ctrl_reg = bitfield_bit32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_REG_RDY_BIT, 1);
201  ctrl_reg =
202  bitfield_field32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_STS_FIELD, 0x0);
203  ctrl_reg = bitfield_bit32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_ACK_BIT, 0);
204  EXPECT_READ32(EDN_SW_CMD_STS_REG_OFFSET, ctrl_reg);
205  EXPECT_DIF_BADARG(
206  dif_edn_get_status(&edn_, static_cast<dif_edn_status_t>(-1), &flag));
207 
208  EXPECT_DIF_BADARG(dif_edn_get_status(&edn_, kDifEdnStatusReady, nullptr));
209 }
210 
211 TEST_F(GetStatusTest, Ok) {
212  bool flag;
213  uint32_t ctrl_reg = 0;
214 
215  ctrl_reg = bitfield_bit32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_RDY_BIT, 1);
216  ctrl_reg = bitfield_bit32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_REG_RDY_BIT, 1);
217  ctrl_reg =
218  bitfield_field32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_STS_FIELD, 0x0);
219  ctrl_reg = bitfield_bit32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_ACK_BIT, 0);
220  EXPECT_READ32(EDN_SW_CMD_STS_REG_OFFSET, ctrl_reg);
221  EXPECT_DIF_OK(dif_edn_get_status(&edn_, kDifEdnStatusRegReady, &flag));
222  EXPECT_TRUE(flag);
223 
224  ctrl_reg = 0;
225  ctrl_reg = bitfield_bit32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_RDY_BIT, 1);
226  ctrl_reg = bitfield_bit32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_REG_RDY_BIT, 1);
227  ctrl_reg =
228  bitfield_field32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_STS_FIELD, 0x0);
229  ctrl_reg = bitfield_bit32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_ACK_BIT, 0);
230  EXPECT_READ32(EDN_SW_CMD_STS_REG_OFFSET, ctrl_reg);
231  EXPECT_DIF_OK(dif_edn_get_status(&edn_, kDifEdnStatusReady, &flag));
232  EXPECT_TRUE(flag);
233 
234  ctrl_reg = 0;
235  ctrl_reg = bitfield_bit32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_RDY_BIT, 1);
236  ctrl_reg = bitfield_bit32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_REG_RDY_BIT, 1);
237  ctrl_reg =
238  bitfield_field32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_STS_FIELD, 0x0);
239  ctrl_reg = bitfield_bit32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_ACK_BIT, 0);
240  EXPECT_READ32(EDN_SW_CMD_STS_REG_OFFSET, ctrl_reg);
241  EXPECT_DIF_OK(dif_edn_get_status(&edn_, kDifEdnStatusCsrngStatus, &flag));
242  EXPECT_FALSE(flag);
243 
244  ctrl_reg = 0;
245  ctrl_reg = bitfield_bit32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_RDY_BIT, 1);
246  ctrl_reg = bitfield_bit32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_REG_RDY_BIT, 1);
247  ctrl_reg =
248  bitfield_field32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_STS_FIELD, 0x0);
249  ctrl_reg = bitfield_bit32_write(ctrl_reg, EDN_SW_CMD_STS_CMD_ACK_BIT, 0);
250  EXPECT_READ32(EDN_SW_CMD_STS_REG_OFFSET, ctrl_reg);
251  EXPECT_DIF_OK(dif_edn_get_status(&edn_, kDifEdnStatusCsrngAck, &flag));
252  EXPECT_FALSE(flag);
253 }
254 
255 class ErrorTest : public DifEdnTest {};
256 
257 TEST_F(ErrorTest, BadArgs) {
258  uint32_t set;
259  EXPECT_DIF_BADARG(dif_edn_get_errors(nullptr, &set, &set));
260  EXPECT_DIF_BADARG(dif_edn_get_errors(&edn_, nullptr, &set));
261  EXPECT_DIF_BADARG(dif_edn_get_errors(&edn_, &set, nullptr));
262  EXPECT_DIF_BADARG(dif_edn_get_cmd_unhealthy_fifo_force(
263  &edn_, static_cast<dif_edn_fifo_t>(-1)));
264  EXPECT_DIF_BADARG(
265  dif_edn_get_cmd_unhealthy_fifo_force(nullptr, kDifEdnFifoReseedCmd));
266  EXPECT_DIF_BADARG(
267  dif_edn_get_cmd_error_force(&edn_, static_cast<dif_edn_error_t>(-1)));
268  EXPECT_DIF_BADARG(dif_edn_get_cmd_error_force(nullptr, kDifEdnErrorMainSm));
269 }
270 
271 TEST_F(ErrorTest, Ok) {
272  EXPECT_READ32(EDN_ERR_CODE_REG_OFFSET,
273  {
274  {EDN_ERR_CODE_SFIFO_RESCMD_ERR_BIT, true},
275  {EDN_ERR_CODE_EDN_MAIN_SM_ERR_BIT, true},
276  {EDN_ERR_CODE_FIFO_STATE_ERR_BIT, true},
277  });
278 
279  uint32_t fifos, errors;
280  EXPECT_DIF_OK(dif_edn_get_errors(&edn_, &fifos, &errors));
281  EXPECT_EQ(fifos, 1 << kDifEdnFifoReseedCmd);
282  EXPECT_EQ(errors,
283  1 << kDifEdnErrorMainSm | 1 << kDifEdnErrorFifoFullAndEmpty);
284 }
285 
286 TEST_F(ErrorTest, ForceFifo) {
287  EXPECT_READ32(EDN_REGWEN_REG_OFFSET, 1);
288  EXPECT_WRITE32(EDN_ERR_CODE_TEST_REG_OFFSET,
289  EDN_ERR_CODE_SFIFO_RESCMD_ERR_BIT);
290  EXPECT_DIF_OK(
291  dif_edn_get_cmd_unhealthy_fifo_force(&edn_, kDifEdnFifoReseedCmd));
292 }
293 
294 TEST_F(ErrorTest, ForceError) {
295  EXPECT_READ32(EDN_REGWEN_REG_OFFSET, 1);
296  EXPECT_WRITE32(EDN_ERR_CODE_TEST_REG_OFFSET,
297  EDN_ERR_CODE_EDN_MAIN_SM_ERR_BIT);
298  EXPECT_DIF_OK(dif_edn_get_cmd_error_force(&edn_, kDifEdnErrorMainSm));
299 }
300 
301 TEST_F(ErrorTest, Locked) {
302  EXPECT_READ32(EDN_REGWEN_REG_OFFSET, 0);
303  EXPECT_READ32(EDN_REGWEN_REG_OFFSET, 0);
304  EXPECT_EQ(dif_edn_get_cmd_unhealthy_fifo_force(&edn_, kDifEdnFifoReseedCmd),
305  kDifLocked);
306  EXPECT_EQ(dif_edn_get_cmd_error_force(&edn_, kDifEdnErrorMainSm), kDifLocked);
307 }
308 
309 class MiscStatusTest : public DifEdnTest {};
310 
311 TEST_F(MiscStatusTest, BadArgs) {
312  uint32_t out;
313  EXPECT_DIF_BADARG(dif_edn_get_main_state_machine(nullptr, &out));
314  EXPECT_DIF_BADARG(dif_edn_get_main_state_machine(&edn_, nullptr));
315 }
316 
317 TEST_F(MiscStatusTest, GetMainSm) {
318  EXPECT_READ32(EDN_MAIN_SM_STATE_REG_OFFSET, 42);
319 
320  uint32_t out;
321  EXPECT_DIF_OK(dif_edn_get_main_state_machine(&edn_, &out));
322  EXPECT_EQ(out, 42);
323 }
324 
325 /**
326  * DRBG commands are tested using this test group as the underlying
327  * command interface is shared across API functions.
328  */
329 class CommandTest : public DifEdnTest {
330  protected:
331  dif_edn_seed_material_t seed_material_{};
332 };
333 
334 TEST_F(CommandTest, InstantiateOk) {
335  EXPECT_READ32(EDN_SW_CMD_STS_REG_OFFSET,
336  {{EDN_SW_CMD_STS_CMD_RDY_BIT, true}});
337  EXPECT_WRITE32(EDN_SW_CMD_REQ_REG_OFFSET,
338  0x00000001 | kMultiBitBool4True << 8);
339  EXPECT_DIF_OK(dif_edn_instantiate(&edn_, kDifEdnEntropySrcToggleDisable,
340  &seed_material_));
341 
342  EXPECT_READ32(EDN_SW_CMD_STS_REG_OFFSET,
343  {{EDN_SW_CMD_STS_CMD_RDY_BIT, true}});
344  EXPECT_WRITE32(EDN_SW_CMD_REQ_REG_OFFSET,
345  0x00000001 | kMultiBitBool4False << 8);
346  EXPECT_DIF_OK(dif_edn_instantiate(&edn_, kDifEdnEntropySrcToggleEnable,
347  &seed_material_));
348 
349  seed_material_.data[0] = 0x5a5a5a5a;
350  seed_material_.len = 1;
351  EXPECT_READ32(EDN_SW_CMD_STS_REG_OFFSET,
352  {{EDN_SW_CMD_STS_CMD_RDY_BIT, true}});
353  EXPECT_WRITE32(EDN_SW_CMD_REQ_REG_OFFSET,
354  0x00000011 | kMultiBitBool4False << 8);
355  EXPECT_READ32(EDN_SW_CMD_STS_REG_OFFSET,
356  {{EDN_SW_CMD_STS_CMD_REG_RDY_BIT, true}});
357  EXPECT_WRITE32(EDN_SW_CMD_REQ_REG_OFFSET, 0x5a5a5a5a);
358  EXPECT_DIF_OK(dif_edn_instantiate(&edn_, kDifEdnEntropySrcToggleEnable,
359  &seed_material_));
360 }
361 
362 TEST_F(CommandTest, InstantiateBadArgs) {
363  EXPECT_DIF_BADARG(dif_edn_instantiate(nullptr, kDifEdnEntropySrcToggleDisable,
364  &seed_material_));
365 
366  // Unaligned `seed_material` pointer.
367  dif_edn_seed_material_t *corrupt_seed_material_ptr =
368  reinterpret_cast<dif_edn_seed_material_t *>(
369  reinterpret_cast<uintptr_t>(&seed_material_) + 3);
370  EXPECT_DIF_BADARG(dif_edn_instantiate(&edn_, kDifEdnEntropySrcToggleDisable,
371  corrupt_seed_material_ptr));
372 
373  // Failed overflow check.
374  seed_material_.len = 16;
375  EXPECT_DIF_BADARG(dif_edn_instantiate(&edn_, kDifEdnEntropySrcToggleDisable,
376  &seed_material_));
377 }
378 
379 TEST_F(CommandTest, ReseedOk) {
380  EXPECT_READ32(EDN_SW_CMD_STS_REG_OFFSET,
381  {{EDN_SW_CMD_STS_CMD_RDY_BIT, true}});
382  EXPECT_WRITE32(EDN_SW_CMD_REQ_REG_OFFSET,
383  0x00000002 | kMultiBitBool4False << 8);
384  EXPECT_DIF_OK(dif_edn_reseed(&edn_, &seed_material_));
385 
386  seed_material_.data[0] = 0x5a5a5a5a;
387  seed_material_.len = 1;
388  EXPECT_READ32(EDN_SW_CMD_STS_REG_OFFSET,
389  {{EDN_SW_CMD_STS_CMD_RDY_BIT, true}});
390  EXPECT_WRITE32(EDN_SW_CMD_REQ_REG_OFFSET,
391  0x00000012 | kMultiBitBool4False << 8);
392  EXPECT_READ32(EDN_SW_CMD_STS_REG_OFFSET,
393  {{EDN_SW_CMD_STS_CMD_REG_RDY_BIT, true}});
394  EXPECT_WRITE32(EDN_SW_CMD_REQ_REG_OFFSET, 0x5a5a5a5a);
395  EXPECT_DIF_OK(dif_edn_reseed(&edn_, &seed_material_));
396 }
397 
398 TEST_F(CommandTest, ReseedBadArgs) {
399  EXPECT_DIF_BADARG(dif_edn_reseed(nullptr, &seed_material_));
400 
401  // Failed overflow check.
402  seed_material_.len = 16;
403  EXPECT_DIF_BADARG(dif_edn_reseed(&edn_, &seed_material_));
404 }
405 
406 TEST_F(CommandTest, UpdateOk) {
407  EXPECT_READ32(EDN_SW_CMD_STS_REG_OFFSET,
408  {{EDN_SW_CMD_STS_CMD_RDY_BIT, true}});
409  EXPECT_WRITE32(EDN_SW_CMD_REQ_REG_OFFSET,
410  0x00000004 | kMultiBitBool4False << 8);
411  EXPECT_DIF_OK(dif_edn_update(&edn_, &seed_material_));
412  seed_material_.data[0] = 0x5a5a5a5a;
413  seed_material_.len = 1;
414  EXPECT_READ32(EDN_SW_CMD_STS_REG_OFFSET,
415  {{EDN_SW_CMD_STS_CMD_RDY_BIT, true}});
416  EXPECT_WRITE32(EDN_SW_CMD_REQ_REG_OFFSET,
417  0x00000014 | kMultiBitBool4False << 8);
418  EXPECT_READ32(EDN_SW_CMD_STS_REG_OFFSET,
419  {{EDN_SW_CMD_STS_CMD_REG_RDY_BIT, true}});
420  EXPECT_WRITE32(EDN_SW_CMD_REQ_REG_OFFSET, 0x5a5a5a5a);
421  EXPECT_DIF_OK(dif_edn_update(&edn_, &seed_material_));
422 }
423 
424 TEST_F(CommandTest, UpdateBadArgs) {
425  EXPECT_DIF_BADARG(dif_edn_update(nullptr, &seed_material_));
426 }
427 
428 TEST_F(CommandTest, GenerateOk) {
429  // 512bits = 16 x 32bit = 4 x 128bit blocks
430  EXPECT_READ32(EDN_SW_CMD_STS_REG_OFFSET,
431  {{EDN_SW_CMD_STS_CMD_RDY_BIT, true}});
432  EXPECT_WRITE32(EDN_SW_CMD_REQ_REG_OFFSET,
433  0x00004003 | kMultiBitBool4False << 8);
434  EXPECT_DIF_OK(dif_edn_generate_start(&edn_, /*len=*/16));
435 
436  // 576bits = 18 x 32bit = 5 x 128bit blocks (rounded up)
437  EXPECT_READ32(EDN_SW_CMD_STS_REG_OFFSET,
438  {{EDN_SW_CMD_STS_CMD_RDY_BIT, true}});
439  EXPECT_WRITE32(EDN_SW_CMD_REQ_REG_OFFSET,
440  0x00005003 | kMultiBitBool4False << 8);
441  EXPECT_DIF_OK(dif_edn_generate_start(&edn_, /*len=*/18));
442 }
443 
444 TEST_F(CommandTest, GenerateBadArgs) {
445  EXPECT_DIF_BADARG(dif_edn_generate_start(nullptr, /*len=*/1));
446  EXPECT_DIF_BADARG(dif_edn_generate_start(&edn_, /*len=*/0));
447 }
448 
449 TEST_F(CommandTest, GenerateOutOfRange) {
450  enum {
451  // The maximum allowed is 0x800 128-bit blocks. Multiply by 4 to get the
452  // number of uint32 words and add one to trigger the error.
453  kGenerateLenOutOfRange = 0x800 * 4 + 1,
454  };
455  EXPECT_DIF_OUTOFRANGE(dif_edn_generate_start(&edn_, kGenerateLenOutOfRange));
456 }
457 
458 TEST_F(CommandTest, UninstantiateOk) {
459  EXPECT_READ32(EDN_SW_CMD_STS_REG_OFFSET,
460  {{EDN_SW_CMD_STS_CMD_RDY_BIT, true}});
461  EXPECT_WRITE32(EDN_SW_CMD_REQ_REG_OFFSET,
462  0x00000005 | kMultiBitBool4False << 8);
463  EXPECT_DIF_OK(dif_edn_uninstantiate(&edn_));
464 }
465 
466 class StopTest : public DifEdnTest {};
467 
468 TEST_F(StopTest, BadArgs) { EXPECT_DIF_BADARG(dif_edn_stop(nullptr)); }
469 
470 TEST_F(StopTest, Stop) {
471  EXPECT_READ32(EDN_REGWEN_REG_OFFSET, 1);
472  EXPECT_READ32(EDN_CTRL_REG_OFFSET, 0x3);
473  uint32_t ctrl_reg = bitfield_field32_write(0x3, EDN_CTRL_CMD_FIFO_RST_FIELD,
474  kMultiBitBool4True);
475  EXPECT_WRITE32(EDN_CTRL_REG_OFFSET, ctrl_reg);
476  EXPECT_WRITE32(EDN_CTRL_REG_OFFSET, EDN_CTRL_REG_RESVAL);
477  EXPECT_DIF_OK(dif_edn_stop(&edn_));
478 }
479 
480 TEST_F(StopTest, Locked) {
481  EXPECT_READ32(EDN_REGWEN_REG_OFFSET, 0);
482  EXPECT_EQ(dif_edn_stop(&edn_), kDifLocked);
483 }
484 
485 class AlertTest : public DifEdnTest {};
486 
487 TEST_F(AlertTest, BadArgs) {
488  uint32_t out;
489  EXPECT_DIF_BADARG(dif_edn_get_recoverable_alerts(nullptr, &out));
490  EXPECT_DIF_BADARG(dif_edn_get_recoverable_alerts(&edn_, nullptr));
491  EXPECT_DIF_BADARG(dif_edn_clear_recoverable_alerts(nullptr));
492 }
493 
494 TEST_F(AlertTest, Get) {
495  uint32_t out;
496  EXPECT_READ32(EDN_RECOV_ALERT_STS_REG_OFFSET,
497  {
498  {EDN_RECOV_ALERT_STS_BOOT_REQ_MODE_FIELD_ALERT_BIT, true},
499  {EDN_RECOV_ALERT_STS_EDN_BUS_CMP_ALERT_BIT, true},
500  });
501  EXPECT_DIF_OK(dif_edn_get_recoverable_alerts(&edn_, &out));
502  EXPECT_EQ(out, 1 << kDifEdnRecoverableAlertBadBootReqMode |
503  1 << kDifEdnRecoverableAlertRepeatedGenBits);
504 }
505 
506 TEST_F(AlertTest, Clear) {
507  EXPECT_WRITE32(EDN_RECOV_ALERT_STS_REG_OFFSET, 0);
508  EXPECT_DIF_OK(dif_edn_clear_recoverable_alerts(&edn_));
509 }
510 
511 } // namespace
512 } // namespace dif_edn_unittest
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