73 uint32_t ctrl_reg = mmio_region_read32(edn->
base_addr, EDN_CTRL_REG_OFFSET);
74 const uint32_t edn_en =
75 bitfield_field32_read(ctrl_reg, EDN_CTRL_EDN_ENABLE_FIELD);
81 ctrl_reg = bitfield_field32_write(ctrl_reg, EDN_CTRL_AUTO_REQ_MODE_FIELD,
83 ctrl_reg = bitfield_field32_write(ctrl_reg, EDN_CTRL_BOOT_REQ_MODE_FIELD,
85 mmio_region_write32(edn->
base_addr, EDN_CTRL_REG_OFFSET, ctrl_reg);
88 ctrl_reg = bitfield_field32_write(ctrl_reg, EDN_CTRL_CMD_FIFO_RST_FIELD,
90 mmio_region_write32(edn->
base_addr, EDN_CTRL_REG_OFFSET, ctrl_reg);
94 ctrl_reg = bitfield_field32_write(ctrl_reg, EDN_CTRL_CMD_FIFO_RST_FIELD,
96 mmio_region_write32(edn->
base_addr, EDN_CTRL_REG_OFFSET, ctrl_reg);
99 mmio_region_write32(edn->
base_addr, EDN_RESEED_CMD_REG_OFFSET,
102 mmio_region_write32(edn->
base_addr, EDN_RESEED_CMD_REG_OFFSET,
107 mmio_region_write32(edn->
base_addr, EDN_GENERATE_CMD_REG_OFFSET,
110 mmio_region_write32(edn->
base_addr, EDN_GENERATE_CMD_REG_OFFSET,
116 EDN_MAX_NUM_REQS_BETWEEN_RESEEDS_REG_OFFSET,
120 ctrl_reg = bitfield_field32_write(ctrl_reg, EDN_CTRL_EDN_ENABLE_FIELD,
122 ctrl_reg = bitfield_field32_write(ctrl_reg, EDN_CTRL_AUTO_REQ_MODE_FIELD,
124 mmio_region_write32(edn->
base_addr, EDN_CTRL_REG_OFFSET, ctrl_reg);
156 if (edn == NULL || set == NULL) {
160 uint32_t reg = mmio_region_read32(edn->
base_addr, EDN_SW_CMD_STS_REG_OFFSET);
164 *set = bitfield_bit32_read(reg, EDN_SW_CMD_STS_CMD_REG_RDY_BIT);
167 *set = bitfield_bit32_read(reg, EDN_SW_CMD_STS_CMD_RDY_BIT);
170 field_val = bitfield_field32_read(reg, EDN_SW_CMD_STS_CMD_STS_FIELD);
171 *set = field_val ? true :
false;
174 *set = bitfield_bit32_read(reg, EDN_SW_CMD_STS_CMD_ACK_BIT);
185 if (edn == NULL || unhealthy_fifos == NULL || errors == NULL) {
188 *unhealthy_fifos = 0;
191 uint32_t reg = mmio_region_read32(edn->
base_addr, EDN_ERR_CODE_REG_OFFSET);
193 bitfield_bit32_copy(*unhealthy_fifos, kDifEdnFifoReseedCmd, reg,
194 EDN_ERR_CODE_SFIFO_RESCMD_ERR_BIT);
196 bitfield_bit32_copy(*unhealthy_fifos, kDifEdnFifoGenerateCmd, reg,
197 EDN_ERR_CODE_SFIFO_GENCMD_ERR_BIT);
200 EDN_ERR_CODE_EDN_ACK_SM_ERR_BIT);
202 EDN_ERR_CODE_EDN_MAIN_SM_ERR_BIT);
204 EDN_ERR_CODE_EDN_CNTR_ERR_BIT);
206 EDN_ERR_CODE_FIFO_WRITE_ERR_BIT);
208 EDN_ERR_CODE_FIFO_READ_ERR_BIT);
210 EDN_ERR_CODE_FIFO_STATE_ERR_BIT);
223 case kDifEdnFifoReseedCmd:
224 fifo_bit = EDN_ERR_CODE_SFIFO_RESCMD_ERR_BIT;
226 case kDifEdnFifoGenerateCmd:
227 fifo_bit = EDN_ERR_CODE_SFIFO_GENCMD_ERR_BIT;
234 mmio_region_write32(edn->
base_addr, EDN_ERR_CODE_TEST_REG_OFFSET, fifo_bit);
247 error_bit = EDN_ERR_CODE_EDN_ACK_SM_ERR_BIT;
250 error_bit = EDN_ERR_CODE_EDN_MAIN_SM_ERR_BIT;
253 error_bit = EDN_ERR_CODE_EDN_CNTR_ERR_BIT;
256 error_bit = EDN_ERR_CODE_FIFO_WRITE_ERR_BIT;
259 error_bit = EDN_ERR_CODE_FIFO_READ_ERR_BIT;
262 error_bit = EDN_ERR_CODE_FIFO_STATE_ERR_BIT;
269 mmio_region_write32(edn->
base_addr, EDN_ERR_CODE_TEST_REG_OFFSET, error_bit);
359 uint32_t reg = mmio_region_read32(edn->
base_addr, EDN_CTRL_REG_OFFSET);
360 reg = bitfield_field32_write(reg, EDN_CTRL_CMD_FIFO_RST_FIELD,
362 mmio_region_write32(edn->
base_addr, EDN_CTRL_REG_OFFSET, reg);
366 mmio_region_write32(edn->
base_addr, EDN_CTRL_REG_OFFSET, EDN_CTRL_REG_RESVAL);
373 if (edn == NULL || alerts == NULL) {
379 mmio_region_read32(edn->
base_addr, EDN_RECOV_ALERT_STS_REG_OFFSET);
381 EDN_RECOV_ALERT_STS_EDN_ENABLE_FIELD_ALERT_BIT);
384 EDN_RECOV_ALERT_STS_BOOT_REQ_MODE_FIELD_ALERT_BIT);
387 EDN_RECOV_ALERT_STS_AUTO_REQ_MODE_FIELD_ALERT_BIT);
390 EDN_RECOV_ALERT_STS_CMD_FIFO_RST_FIELD_ALERT_BIT);
392 reg, EDN_RECOV_ALERT_STS_EDN_BUS_CMP_ALERT_BIT);