Software APIs
dif_csrng_autogen.c
1 // Copyright lowRISC contributors (OpenTitan project).
2 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3 // SPDX-License-Identifier: Apache-2.0
4 
5 // THIS FILE HAS BEEN GENERATED, DO NOT EDIT MANUALLY. COMMAND:
6 // util/make_new_dif.py --mode=regen --only=autogen
7 
8 #include "sw/device/lib/dif/autogen/dif_csrng_autogen.h"
9 
10 #include <stdint.h>
11 
12 #include "sw/device/lib/dif/dif_base.h"
13 
14 #include "csrng_regs.h" // Generated.
15 
16 OT_WARN_UNUSED_RESULT
17 dif_result_t dif_csrng_init(mmio_region_t base_addr, dif_csrng_t *csrng) {
18  if (csrng == NULL) {
19  return kDifBadArg;
20  }
21 
22  csrng->base_addr = base_addr;
23 
24  return kDifOk;
25 }
26 
27 dif_result_t dif_csrng_alert_force(const dif_csrng_t *csrng,
28  dif_csrng_alert_t alert) {
29  if (csrng == NULL) {
30  return kDifBadArg;
31  }
32 
33  bitfield_bit32_index_t alert_idx;
34  switch (alert) {
35  case kDifCsrngAlertRecovAlert:
36  alert_idx = CSRNG_ALERT_TEST_RECOV_ALERT_BIT;
37  break;
38  case kDifCsrngAlertFatalAlert:
39  alert_idx = CSRNG_ALERT_TEST_FATAL_ALERT_BIT;
40  break;
41  default:
42  return kDifBadArg;
43  }
44 
45  uint32_t alert_test_reg = bitfield_bit32_write(0, alert_idx, true);
46  mmio_region_write32(csrng->base_addr, (ptrdiff_t)CSRNG_ALERT_TEST_REG_OFFSET,
47  alert_test_reg);
48 
49  return kDifOk;
50 }
51 
52 /**
53  * Get the corresponding interrupt register bit offset of the IRQ.
54  */
55 static bool csrng_get_irq_bit_index(dif_csrng_irq_t irq,
56  bitfield_bit32_index_t *index_out) {
57  switch (irq) {
58  case kDifCsrngIrqCsCmdReqDone:
59  *index_out = CSRNG_INTR_COMMON_CS_CMD_REQ_DONE_BIT;
60  break;
61  case kDifCsrngIrqCsEntropyReq:
62  *index_out = CSRNG_INTR_COMMON_CS_ENTROPY_REQ_BIT;
63  break;
64  case kDifCsrngIrqCsHwInstExc:
65  *index_out = CSRNG_INTR_COMMON_CS_HW_INST_EXC_BIT;
66  break;
67  case kDifCsrngIrqCsFatalErr:
68  *index_out = CSRNG_INTR_COMMON_CS_FATAL_ERR_BIT;
69  break;
70  default:
71  return false;
72  }
73 
74  return true;
75 }
76 
77 static dif_irq_type_t irq_types[] = {
78  kDifIrqTypeEvent,
79  kDifIrqTypeEvent,
80  kDifIrqTypeEvent,
81  kDifIrqTypeEvent,
82 };
83 
84 OT_WARN_UNUSED_RESULT
85 dif_result_t dif_csrng_irq_get_type(const dif_csrng_t *csrng,
86  dif_csrng_irq_t irq, dif_irq_type_t *type) {
87  if (csrng == NULL || type == NULL || irq < 0 ||
88  irq > kDifCsrngIrqCsFatalErr) {
89  return kDifBadArg;
90  }
91 
92  *type = irq_types[irq];
93 
94  return kDifOk;
95 }
96 
97 OT_WARN_UNUSED_RESULT
98 dif_result_t dif_csrng_irq_get_state(const dif_csrng_t *csrng,
99  dif_csrng_irq_state_snapshot_t *snapshot) {
100  if (csrng == NULL || snapshot == NULL) {
101  return kDifBadArg;
102  }
103 
104  *snapshot = mmio_region_read32(csrng->base_addr,
105  (ptrdiff_t)CSRNG_INTR_STATE_REG_OFFSET);
106 
107  return kDifOk;
108 }
109 
110 OT_WARN_UNUSED_RESULT
111 dif_result_t dif_csrng_irq_acknowledge_state(
112  const dif_csrng_t *csrng, dif_csrng_irq_state_snapshot_t snapshot) {
113  if (csrng == NULL) {
114  return kDifBadArg;
115  }
116 
117  mmio_region_write32(csrng->base_addr, (ptrdiff_t)CSRNG_INTR_STATE_REG_OFFSET,
118  snapshot);
119 
120  return kDifOk;
121 }
122 
123 OT_WARN_UNUSED_RESULT
124 dif_result_t dif_csrng_irq_is_pending(const dif_csrng_t *csrng,
125  dif_csrng_irq_t irq, bool *is_pending) {
126  if (csrng == NULL || is_pending == NULL) {
127  return kDifBadArg;
128  }
129 
130  bitfield_bit32_index_t index;
131  if (!csrng_get_irq_bit_index(irq, &index)) {
132  return kDifBadArg;
133  }
134 
135  uint32_t intr_state_reg = mmio_region_read32(
136  csrng->base_addr, (ptrdiff_t)CSRNG_INTR_STATE_REG_OFFSET);
137 
138  *is_pending = bitfield_bit32_read(intr_state_reg, index);
139 
140  return kDifOk;
141 }
142 
143 OT_WARN_UNUSED_RESULT
144 dif_result_t dif_csrng_irq_acknowledge_all(const dif_csrng_t *csrng) {
145  if (csrng == NULL) {
146  return kDifBadArg;
147  }
148 
149  // Writing to the register clears the corresponding bits (Write-one clear).
150  mmio_region_write32(csrng->base_addr, (ptrdiff_t)CSRNG_INTR_STATE_REG_OFFSET,
151  UINT32_MAX);
152 
153  return kDifOk;
154 }
155 
156 OT_WARN_UNUSED_RESULT
157 dif_result_t dif_csrng_irq_acknowledge(const dif_csrng_t *csrng,
158  dif_csrng_irq_t irq) {
159  if (csrng == NULL) {
160  return kDifBadArg;
161  }
162 
163  bitfield_bit32_index_t index;
164  if (!csrng_get_irq_bit_index(irq, &index)) {
165  return kDifBadArg;
166  }
167 
168  // Writing to the register clears the corresponding bits (Write-one clear).
169  uint32_t intr_state_reg = bitfield_bit32_write(0, index, true);
170  mmio_region_write32(csrng->base_addr, (ptrdiff_t)CSRNG_INTR_STATE_REG_OFFSET,
171  intr_state_reg);
172 
173  return kDifOk;
174 }
175 
176 OT_WARN_UNUSED_RESULT
177 dif_result_t dif_csrng_irq_force(const dif_csrng_t *csrng, dif_csrng_irq_t irq,
178  const bool val) {
179  if (csrng == NULL) {
180  return kDifBadArg;
181  }
182 
183  bitfield_bit32_index_t index;
184  if (!csrng_get_irq_bit_index(irq, &index)) {
185  return kDifBadArg;
186  }
187 
188  uint32_t intr_test_reg = bitfield_bit32_write(0, index, val);
189  mmio_region_write32(csrng->base_addr, (ptrdiff_t)CSRNG_INTR_TEST_REG_OFFSET,
190  intr_test_reg);
191 
192  return kDifOk;
193 }
194 
195 OT_WARN_UNUSED_RESULT
196 dif_result_t dif_csrng_irq_get_enabled(const dif_csrng_t *csrng,
197  dif_csrng_irq_t irq,
198  dif_toggle_t *state) {
199  if (csrng == NULL || state == NULL) {
200  return kDifBadArg;
201  }
202 
203  bitfield_bit32_index_t index;
204  if (!csrng_get_irq_bit_index(irq, &index)) {
205  return kDifBadArg;
206  }
207 
208  uint32_t intr_enable_reg = mmio_region_read32(
209  csrng->base_addr, (ptrdiff_t)CSRNG_INTR_ENABLE_REG_OFFSET);
210 
211  bool is_enabled = bitfield_bit32_read(intr_enable_reg, index);
212  *state = is_enabled ? kDifToggleEnabled : kDifToggleDisabled;
213 
214  return kDifOk;
215 }
216 
217 OT_WARN_UNUSED_RESULT
218 dif_result_t dif_csrng_irq_set_enabled(const dif_csrng_t *csrng,
219  dif_csrng_irq_t irq,
220  dif_toggle_t state) {
221  if (csrng == NULL) {
222  return kDifBadArg;
223  }
224 
225  bitfield_bit32_index_t index;
226  if (!csrng_get_irq_bit_index(irq, &index)) {
227  return kDifBadArg;
228  }
229 
230  uint32_t intr_enable_reg = mmio_region_read32(
231  csrng->base_addr, (ptrdiff_t)CSRNG_INTR_ENABLE_REG_OFFSET);
232 
233  bool enable_bit = (state == kDifToggleEnabled) ? true : false;
234  intr_enable_reg = bitfield_bit32_write(intr_enable_reg, index, enable_bit);
235  mmio_region_write32(csrng->base_addr, (ptrdiff_t)CSRNG_INTR_ENABLE_REG_OFFSET,
236  intr_enable_reg);
237 
238  return kDifOk;
239 }
240 
241 OT_WARN_UNUSED_RESULT
242 dif_result_t dif_csrng_irq_disable_all(
243  const dif_csrng_t *csrng, dif_csrng_irq_enable_snapshot_t *snapshot) {
244  if (csrng == NULL) {
245  return kDifBadArg;
246  }
247 
248  // Pass the current interrupt state to the caller, if requested.
249  if (snapshot != NULL) {
250  *snapshot = mmio_region_read32(csrng->base_addr,
251  (ptrdiff_t)CSRNG_INTR_ENABLE_REG_OFFSET);
252  }
253 
254  // Disable all interrupts.
255  mmio_region_write32(csrng->base_addr, (ptrdiff_t)CSRNG_INTR_ENABLE_REG_OFFSET,
256  0u);
257 
258  return kDifOk;
259 }
260 
261 OT_WARN_UNUSED_RESULT
262 dif_result_t dif_csrng_irq_restore_all(
263  const dif_csrng_t *csrng, const dif_csrng_irq_enable_snapshot_t *snapshot) {
264  if (csrng == NULL || snapshot == NULL) {
265  return kDifBadArg;
266  }
267 
268  mmio_region_write32(csrng->base_addr, (ptrdiff_t)CSRNG_INTR_ENABLE_REG_OFFSET,
269  *snapshot);
270 
271  return kDifOk;
272 }
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