Software APIs
dif_csrng_autogen.c
1 // Copyright lowRISC contributors (OpenTitan project).
2 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3 // SPDX-License-Identifier: Apache-2.0
4 
5 // THIS FILE HAS BEEN GENERATED, DO NOT EDIT MANUALLY. COMMAND:
6 // util/make_new_dif.py --mode=regen --only=autogen
7 
8 #include "sw/device/lib/dif/autogen/dif_csrng_autogen.h"
9 
10 #include <stdint.h>
11 
12 #include "sw/device/lib/dif/dif_base.h"
13 
14 #include "csrng_regs.h" // Generated.
15 
16 OT_WARN_UNUSED_RESULT
17 dif_result_t dif_csrng_init(mmio_region_t base_addr, dif_csrng_t *csrng) {
18  if (csrng == NULL) {
19  return kDifBadArg;
20  }
21 
22  csrng->base_addr = base_addr;
23 
24  return kDifOk;
25 }
26 
27 dif_result_t dif_csrng_alert_force(const dif_csrng_t *csrng,
28  dif_csrng_alert_t alert) {
29  if (csrng == NULL) {
30  return kDifBadArg;
31  }
32 
33  bitfield_bit32_index_t alert_idx;
34  switch (alert) {
35  case kDifCsrngAlertRecovAlert:
36  alert_idx = CSRNG_ALERT_TEST_RECOV_ALERT_BIT;
37  break;
38  case kDifCsrngAlertFatalAlert:
39  alert_idx = CSRNG_ALERT_TEST_FATAL_ALERT_BIT;
40  break;
41  default:
42  return kDifBadArg;
43  }
44 
45  uint32_t alert_test_reg = bitfield_bit32_write(0, alert_idx, true);
46  mmio_region_write32(csrng->base_addr, (ptrdiff_t)CSRNG_ALERT_TEST_REG_OFFSET,
47  alert_test_reg);
48 
49  return kDifOk;
50 }
51 
52 /**
53  * Get the corresponding interrupt register bit offset of the IRQ.
54  */
55 static bool csrng_get_irq_bit_index(dif_csrng_irq_t irq,
56  bitfield_bit32_index_t *index_out) {
57  switch (irq) {
58  case kDifCsrngIrqCsCmdReqDone:
59  *index_out = CSRNG_INTR_COMMON_CS_CMD_REQ_DONE_BIT;
60  break;
61  case kDifCsrngIrqCsEntropyReq:
62  *index_out = CSRNG_INTR_COMMON_CS_ENTROPY_REQ_BIT;
63  break;
64  case kDifCsrngIrqCsHwInstExc:
65  *index_out = CSRNG_INTR_COMMON_CS_HW_INST_EXC_BIT;
66  break;
67  case kDifCsrngIrqCsFatalErr:
68  *index_out = CSRNG_INTR_COMMON_CS_FATAL_ERR_BIT;
69  break;
70  default:
71  return false;
72  }
73 
74  return true;
75 }
76 
77 static dif_irq_type_t irq_types[] = {
78  kDifIrqTypeEvent,
79  kDifIrqTypeEvent,
80  kDifIrqTypeEvent,
81  kDifIrqTypeEvent,
82 };
83 
84 OT_WARN_UNUSED_RESULT
85 dif_result_t dif_csrng_irq_get_type(const dif_csrng_t *csrng,
86  dif_csrng_irq_t irq, dif_irq_type_t *type) {
87  if (csrng == NULL || type == NULL || irq == kDifCsrngIrqCsFatalErr + 1) {
88  return kDifBadArg;
89  }
90 
91  *type = irq_types[irq];
92 
93  return kDifOk;
94 }
95 
96 OT_WARN_UNUSED_RESULT
97 dif_result_t dif_csrng_irq_get_state(const dif_csrng_t *csrng,
98  dif_csrng_irq_state_snapshot_t *snapshot) {
99  if (csrng == NULL || snapshot == NULL) {
100  return kDifBadArg;
101  }
102 
103  *snapshot = mmio_region_read32(csrng->base_addr,
104  (ptrdiff_t)CSRNG_INTR_STATE_REG_OFFSET);
105 
106  return kDifOk;
107 }
108 
109 OT_WARN_UNUSED_RESULT
110 dif_result_t dif_csrng_irq_acknowledge_state(
111  const dif_csrng_t *csrng, dif_csrng_irq_state_snapshot_t snapshot) {
112  if (csrng == NULL) {
113  return kDifBadArg;
114  }
115 
116  mmio_region_write32(csrng->base_addr, (ptrdiff_t)CSRNG_INTR_STATE_REG_OFFSET,
117  snapshot);
118 
119  return kDifOk;
120 }
121 
122 OT_WARN_UNUSED_RESULT
123 dif_result_t dif_csrng_irq_is_pending(const dif_csrng_t *csrng,
124  dif_csrng_irq_t irq, bool *is_pending) {
125  if (csrng == NULL || is_pending == NULL) {
126  return kDifBadArg;
127  }
128 
129  bitfield_bit32_index_t index;
130  if (!csrng_get_irq_bit_index(irq, &index)) {
131  return kDifBadArg;
132  }
133 
134  uint32_t intr_state_reg = mmio_region_read32(
135  csrng->base_addr, (ptrdiff_t)CSRNG_INTR_STATE_REG_OFFSET);
136 
137  *is_pending = bitfield_bit32_read(intr_state_reg, index);
138 
139  return kDifOk;
140 }
141 
142 OT_WARN_UNUSED_RESULT
143 dif_result_t dif_csrng_irq_acknowledge_all(const dif_csrng_t *csrng) {
144  if (csrng == NULL) {
145  return kDifBadArg;
146  }
147 
148  // Writing to the register clears the corresponding bits (Write-one clear).
149  mmio_region_write32(csrng->base_addr, (ptrdiff_t)CSRNG_INTR_STATE_REG_OFFSET,
150  UINT32_MAX);
151 
152  return kDifOk;
153 }
154 
155 OT_WARN_UNUSED_RESULT
156 dif_result_t dif_csrng_irq_acknowledge(const dif_csrng_t *csrng,
157  dif_csrng_irq_t irq) {
158  if (csrng == NULL) {
159  return kDifBadArg;
160  }
161 
162  bitfield_bit32_index_t index;
163  if (!csrng_get_irq_bit_index(irq, &index)) {
164  return kDifBadArg;
165  }
166 
167  // Writing to the register clears the corresponding bits (Write-one clear).
168  uint32_t intr_state_reg = bitfield_bit32_write(0, index, true);
169  mmio_region_write32(csrng->base_addr, (ptrdiff_t)CSRNG_INTR_STATE_REG_OFFSET,
170  intr_state_reg);
171 
172  return kDifOk;
173 }
174 
175 OT_WARN_UNUSED_RESULT
176 dif_result_t dif_csrng_irq_force(const dif_csrng_t *csrng, dif_csrng_irq_t irq,
177  const bool val) {
178  if (csrng == NULL) {
179  return kDifBadArg;
180  }
181 
182  bitfield_bit32_index_t index;
183  if (!csrng_get_irq_bit_index(irq, &index)) {
184  return kDifBadArg;
185  }
186 
187  uint32_t intr_test_reg = bitfield_bit32_write(0, index, val);
188  mmio_region_write32(csrng->base_addr, (ptrdiff_t)CSRNG_INTR_TEST_REG_OFFSET,
189  intr_test_reg);
190 
191  return kDifOk;
192 }
193 
194 OT_WARN_UNUSED_RESULT
195 dif_result_t dif_csrng_irq_get_enabled(const dif_csrng_t *csrng,
196  dif_csrng_irq_t irq,
197  dif_toggle_t *state) {
198  if (csrng == NULL || state == NULL) {
199  return kDifBadArg;
200  }
201 
202  bitfield_bit32_index_t index;
203  if (!csrng_get_irq_bit_index(irq, &index)) {
204  return kDifBadArg;
205  }
206 
207  uint32_t intr_enable_reg = mmio_region_read32(
208  csrng->base_addr, (ptrdiff_t)CSRNG_INTR_ENABLE_REG_OFFSET);
209 
210  bool is_enabled = bitfield_bit32_read(intr_enable_reg, index);
211  *state = is_enabled ? kDifToggleEnabled : kDifToggleDisabled;
212 
213  return kDifOk;
214 }
215 
216 OT_WARN_UNUSED_RESULT
217 dif_result_t dif_csrng_irq_set_enabled(const dif_csrng_t *csrng,
218  dif_csrng_irq_t irq,
219  dif_toggle_t state) {
220  if (csrng == NULL) {
221  return kDifBadArg;
222  }
223 
224  bitfield_bit32_index_t index;
225  if (!csrng_get_irq_bit_index(irq, &index)) {
226  return kDifBadArg;
227  }
228 
229  uint32_t intr_enable_reg = mmio_region_read32(
230  csrng->base_addr, (ptrdiff_t)CSRNG_INTR_ENABLE_REG_OFFSET);
231 
232  bool enable_bit = (state == kDifToggleEnabled) ? true : false;
233  intr_enable_reg = bitfield_bit32_write(intr_enable_reg, index, enable_bit);
234  mmio_region_write32(csrng->base_addr, (ptrdiff_t)CSRNG_INTR_ENABLE_REG_OFFSET,
235  intr_enable_reg);
236 
237  return kDifOk;
238 }
239 
240 OT_WARN_UNUSED_RESULT
241 dif_result_t dif_csrng_irq_disable_all(
242  const dif_csrng_t *csrng, dif_csrng_irq_enable_snapshot_t *snapshot) {
243  if (csrng == NULL) {
244  return kDifBadArg;
245  }
246 
247  // Pass the current interrupt state to the caller, if requested.
248  if (snapshot != NULL) {
249  *snapshot = mmio_region_read32(csrng->base_addr,
250  (ptrdiff_t)CSRNG_INTR_ENABLE_REG_OFFSET);
251  }
252 
253  // Disable all interrupts.
254  mmio_region_write32(csrng->base_addr, (ptrdiff_t)CSRNG_INTR_ENABLE_REG_OFFSET,
255  0u);
256 
257  return kDifOk;
258 }
259 
260 OT_WARN_UNUSED_RESULT
261 dif_result_t dif_csrng_irq_restore_all(
262  const dif_csrng_t *csrng, const dif_csrng_irq_enable_snapshot_t *snapshot) {
263  if (csrng == NULL || snapshot == NULL) {
264  return kDifBadArg;
265  }
266 
267  mmio_region_write32(csrng->base_addr, (ptrdiff_t)CSRNG_INTR_ENABLE_REG_OFFSET,
268  *snapshot);
269 
270  return kDifOk;
271 }
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