55 mmio_region_read32(clkmgr->
base_addr, CLKMGR_JITTER_REGWEN_REG_OFFSET),
76 if (clkmgr == NULL ||
status == NULL) {
79 uint32_t extclk_status_val =
80 mmio_region_read32(clkmgr->
base_addr, CLKMGR_EXTCLK_STATUS_REG_OFFSET);
81 *
status = bitfield_field32_read(extclk_status_val,
82 CLKMGR_EXTCLK_STATUS_ACK_FIELD) ==
125 multi_bit_bool_t new_jitter_enable_val;
126 if (clkmgr == NULL) {
129 if (jitter_enable_register_is_locked(clkmgr)) {
135 new_jitter_enable_val = kMultiBitBool4True;
138 new_jitter_enable_val = kMultiBitBool4False;
143 mmio_region_write32(clkmgr->
base_addr, CLKMGR_JITTER_ENABLE_REG_OFFSET,
144 new_jitter_enable_val);
173 if (clkmgr == NULL || state == NULL || !clkmgr_valid_gateable_clock(clock)) {
177 uint32_t clk_enables_val =
178 mmio_region_read32(clkmgr->
base_addr, CLKMGR_CLK_ENABLES_REG_OFFSET);
179 *state = dif_bool_to_toggle(bitfield_bit32_read(clk_enables_val, clock));
187 if (clkmgr == NULL || !clkmgr_valid_gateable_clock(clock) ||
188 !dif_is_valid_toggle(new_state)) {
192 bool new_clk_enables_bit = dif_toggle_to_bool(new_state);
193 uint32_t clk_enables_val =
194 mmio_region_read32(clkmgr->
base_addr, CLKMGR_CLK_ENABLES_REG_OFFSET);
196 bitfield_bit32_write(clk_enables_val, clock, new_clk_enables_bit);
197 mmio_region_write32(clkmgr->
base_addr, CLKMGR_CLK_ENABLES_REG_OFFSET,
242 if (clkmgr == NULL || !clkmgr_valid_hintable_clock(clock) ||
243 !dif_is_valid_toggle(new_state)) {
247 bool new_clk_hints_bit = dif_toggle_to_bool(new_state);
248 uint32_t clk_hints_val =
249 mmio_region_read32(clkmgr->
base_addr, CLKMGR_CLK_HINTS_REG_OFFSET);
250 clk_hints_val = bitfield_bit32_write(clk_hints_val, clock, new_clk_hints_bit);
251 mmio_region_write32(clkmgr->
base_addr, CLKMGR_CLK_HINTS_REG_OFFSET,
294 uint32_t extclk_ctrl_reg = 0;
296 if (clkmgr == NULL) {
300 if (extclk_control_register_is_locked(clkmgr)) {
304 extclk_ctrl_reg = bitfield_field32_write(
305 extclk_ctrl_reg, CLKMGR_EXTCLK_CTRL_SEL_FIELD, kMultiBitBool4True);
306 extclk_ctrl_reg = bitfield_field32_write(
307 extclk_ctrl_reg, CLKMGR_EXTCLK_CTRL_HI_SPEED_SEL_FIELD,
308 is_low_speed ? kMultiBitBool4False : kMultiBitBool4True);
309 mmio_region_write32(clkmgr->
base_addr, CLKMGR_EXTCLK_CTRL_REG_OFFSET,
316 uint32_t extclk_ctrl_reg = 0;
318 if (clkmgr == NULL) {
322 if (extclk_control_register_is_locked(clkmgr)) {
326 extclk_ctrl_reg = bitfield_field32_write(
327 extclk_ctrl_reg, CLKMGR_EXTCLK_CTRL_SEL_FIELD, kMultiBitBool4False);
329 extclk_ctrl_reg = bitfield_field32_write(
330 extclk_ctrl_reg, CLKMGR_EXTCLK_CTRL_HI_SPEED_SEL_FIELD,
332 mmio_region_write32(clkmgr->
base_addr, CLKMGR_EXTCLK_CTRL_REG_OFFSET,
395 dif_clkmgr_measure_clock_t clock,
396 uint32_t lo_threshold,
397 uint32_t hi_threshold) {
398 if (clkmgr == NULL) {
401 if (!clkmgr_measure_ctrl_regwen(clkmgr)) {
405 uint32_t en_offset = 0;
406 uint32_t reg_offset = 0;
411#define PICK_COUNT_CTRL_FIELDS(kind_) \
412 IIF(IS_KIND_DEFINED(kind_), \
413 en_offset = CLKMGR_##kind_##_MEAS_CTRL_EN_REG_OFFSET; \
414 reg_offset = CLKMGR_##kind_##_MEAS_CTRL_SHADOWED_REG_OFFSET; \
415 en_field = CLKMGR_##kind_##_MEAS_CTRL_EN_EN_FIELD; \
416 lo_field = CLKMGR_##kind_##_MEAS_CTRL_SHADOWED_LO_FIELD; \
417 hi_field = CLKMGR_##kind_##_MEAS_CTRL_SHADOWED_HI_FIELD; break, break)
419#if defined(OPENTITAN_IS_EARLGREY)
420 case kDifClkmgrMeasureClockIo:
421 PICK_COUNT_CTRL_FIELDS(IO);
422 case kDifClkmgrMeasureClockIoDiv2:
423 PICK_COUNT_CTRL_FIELDS(IO_DIV2);
424#elif defined(OPENTITAN_IS_DARJEELING)
427#error "dif_clkmgr does not support this top"
430 PICK_COUNT_CTRL_FIELDS(IO_DIV4);
432 PICK_COUNT_CTRL_FIELDS(MAIN);
434 PICK_COUNT_CTRL_FIELDS(USB);
437#undef PICK_COUNT_CTRL_FIELDS
440 uint32_t measure_ctrl_reg = 0;
442 bitfield_field32_write(measure_ctrl_reg, lo_field, lo_threshold);
444 bitfield_field32_write(measure_ctrl_reg, hi_field, hi_threshold);
446 mmio_region_write32(clkmgr->
base_addr, (ptrdiff_t)reg_offset,
448 mmio_region_write32(clkmgr->
base_addr, (ptrdiff_t)reg_offset,
451 uint32_t measure_en_reg = 0;
453 bitfield_field32_write(measure_en_reg, en_field, kMultiBitBool4True);
454 mmio_region_write32(clkmgr->
base_addr, (ptrdiff_t)en_offset, measure_en_reg);
460 const dif_clkmgr_t *clkmgr, dif_clkmgr_measure_clock_t clock) {
461 if (clkmgr == NULL) {
464 if (!clkmgr_measure_ctrl_regwen(clkmgr)) {
468 uint32_t en_offset = 0;
470#define PICK_EN_OFFSET(kind_) \
471 IIF(IS_KIND_DEFINED(kind_), \
472 en_offset = CLKMGR_##kind_##_MEAS_CTRL_EN_REG_OFFSET; \
475#if defined(OPENTITAN_IS_EARLGREY)
476 case kDifClkmgrMeasureClockIo:
479 case kDifClkmgrMeasureClockIoDiv2:
480 PICK_EN_OFFSET(IO_DIV2);
482#elif defined(OPENTITAN_IS_DARJEELING)
485#error "dif_clkmgr does not support this top"
488 PICK_EN_OFFSET(IO_DIV4);
491 PICK_EN_OFFSET(MAIN);
500 mmio_region_write32(clkmgr->
base_addr, (ptrdiff_t)en_offset,
501 kMultiBitBool4False);
506 const dif_clkmgr_t *clkmgr, dif_clkmgr_measure_clock_t clock,
508 if (clkmgr == NULL || state == NULL) {
512 uint32_t en_offset = 0;
514#define PICK_EN_OFFSET(kind_) \
515 IIF(IS_KIND_DEFINED(kind_), \
516 en_offset = CLKMGR_##kind_##_MEAS_CTRL_EN_REG_OFFSET; \
519#if defined(OPENTITAN_IS_EARLGREY)
520 case kDifClkmgrMeasureClockIo:
522 case kDifClkmgrMeasureClockIoDiv2:
523 PICK_EN_OFFSET(IO_DIV2);
524#elif defined(OPENTITAN_IS_DARJEELING)
527#error "dif_clkmgr does not support this top"
530 PICK_EN_OFFSET(IO_DIV4);
532 PICK_EN_OFFSET(MAIN);
539 multi_bit_bool_t en_val =
540 mmio_region_read32(clkmgr->
base_addr, (ptrdiff_t)en_offset);
541 *state = dif_multi_bit_bool_to_toggle(en_val);
547 const dif_clkmgr_t *clkmgr, dif_clkmgr_measure_clock_t clock,
548 uint32_t *min_threshold, uint32_t *max_threshold) {
549 if (clkmgr == NULL || min_threshold == NULL || max_threshold == NULL) {
553 uint32_t reg_offset = 0;
557#define PICK_THRESHOLD_FIELDS(kind_) \
558 IIF(IS_KIND_DEFINED(kind_), \
559 reg_offset = CLKMGR_##kind_##_MEAS_CTRL_SHADOWED_REG_OFFSET; \
560 lo_field = CLKMGR_##kind_##_MEAS_CTRL_SHADOWED_LO_FIELD; \
561 hi_field = CLKMGR_##kind_##_MEAS_CTRL_SHADOWED_HI_FIELD; break, break)
562#if defined(OPENTITAN_IS_EARLGREY)
563 case kDifClkmgrMeasureClockIo:
564 PICK_THRESHOLD_FIELDS(IO);
565 case kDifClkmgrMeasureClockIoDiv2:
566 PICK_THRESHOLD_FIELDS(IO_DIV2);
567#elif defined(OPENTITAN_IS_DARJEELING)
570#error "dif_clkmgr does not support this top"
573 PICK_THRESHOLD_FIELDS(IO_DIV4);
575 PICK_THRESHOLD_FIELDS(MAIN);
577 PICK_THRESHOLD_FIELDS(USB);
580#undef PICK_THRESHOLD_FIELDS
582 uint32_t thresholds_val =
583 mmio_region_read32(clkmgr->
base_addr, (ptrdiff_t)reg_offset);
584 *min_threshold = bitfield_field32_read(thresholds_val, lo_field);
585 *max_threshold = bitfield_field32_read(thresholds_val, hi_field);