11#include "sw/device/lib/base/multibits.h"
14#include "hw/top/clkmgr_regs.h"
20 CLKMGR_PARAM_NUM_SW_GATEABLE_CLOCKS <= CLKMGR_PARAM_REG_WIDTH,
21 "Expected the number of gateable clocks to be <= the width of a CSR.");
27 CLKMGR_PARAM_NUM_HINTABLE_CLOCKS <= CLKMGR_PARAM_REG_WIDTH,
28 "Expected the number of hintable clocks to be <= the width of a CSR.");
31 return clock < CLKMGR_PARAM_NUM_SW_GATEABLE_CLOCKS;
35 return clock < CLKMGR_PARAM_NUM_HINTABLE_CLOCKS;
38static bool clkmgr_measure_ctrl_regwen(
const dif_clkmgr_t *clkmgr) {
39 uint32_t measure_ctrl_regwen_val = mmio_region_read32(
40 clkmgr->
base_addr, CLKMGR_MEASURE_CTRL_REGWEN_REG_OFFSET);
41 return bitfield_bit32_read(measure_ctrl_regwen_val,
42 CLKMGR_MEASURE_CTRL_REGWEN_EN_BIT);
51static bool jitter_enable_register_is_locked(
const dif_clkmgr_t *clkmgr) {
54 return !bitfield_bit32_read(
55 mmio_region_read32(clkmgr->
base_addr, CLKMGR_JITTER_REGWEN_REG_OFFSET),
56 CLKMGR_JITTER_REGWEN_EN_BIT);
65static bool extclk_control_register_is_locked(
const dif_clkmgr_t *clkmgr) {
68 return !bitfield_bit32_read(
70 CLKMGR_EXTCLK_CTRL_REGWEN_REG_OFFSET),
71 CLKMGR_EXTCLK_CTRL_REGWEN_EN_BIT);
76 if (clkmgr == NULL ||
status == NULL) {
79 uint32_t extclk_status_val =
80 mmio_region_read32(clkmgr->
base_addr, CLKMGR_EXTCLK_STATUS_REG_OFFSET);
81 *
status = bitfield_field32_read(extclk_status_val,
82 CLKMGR_EXTCLK_STATUS_ACK_FIELD) ==
90 if (clkmgr == NULL || is_locked == NULL) {
94 *is_locked = jitter_enable_register_is_locked(clkmgr);
100 if (clkmgr == NULL) {
103 mmio_region_write32(clkmgr->
base_addr, CLKMGR_JITTER_REGWEN_REG_OFFSET, 0);
109 if (clkmgr == NULL || state == NULL) {
113 multi_bit_bool_t clk_jitter_val =
114 mmio_region_read32(clkmgr->
base_addr, CLKMGR_JITTER_ENABLE_REG_OFFSET);
125 multi_bit_bool_t new_jitter_enable_val;
126 if (clkmgr == NULL) {
129 if (jitter_enable_register_is_locked(clkmgr)) {
135 new_jitter_enable_val = kMultiBitBool4True;
138 new_jitter_enable_val = kMultiBitBool4False;
143 mmio_region_write32(clkmgr->
base_addr, CLKMGR_JITTER_ENABLE_REG_OFFSET,
144 new_jitter_enable_val);
152 if (clkmgr == NULL || clock == NULL) {
170 if (clkmgr == NULL || state == NULL || !clkmgr_valid_gateable_clock(clock)) {
174 uint32_t clk_enables_val =
175 mmio_region_read32(clkmgr->
base_addr, CLKMGR_CLK_ENABLES_REG_OFFSET);
176 *state = dif_bool_to_toggle(bitfield_bit32_read(clk_enables_val, clock));
184 if (clkmgr == NULL || !clkmgr_valid_gateable_clock(clock) ||
185 !dif_is_valid_toggle(new_state)) {
189 bool new_clk_enables_bit = dif_toggle_to_bool(new_state);
190 uint32_t clk_enables_val =
191 mmio_region_read32(clkmgr->
base_addr, CLKMGR_CLK_ENABLES_REG_OFFSET);
193 bitfield_bit32_write(clk_enables_val, clock, new_clk_enables_bit);
194 mmio_region_write32(clkmgr->
base_addr, CLKMGR_CLK_ENABLES_REG_OFFSET,
204 if (clkmgr == NULL || clock == NULL) {
222 if (clkmgr == NULL || state == NULL || !clkmgr_valid_hintable_clock(clock)) {
226 uint32_t clk_hints_val =
227 mmio_region_read32(clkmgr->
base_addr, CLKMGR_CLK_HINTS_STATUS_REG_OFFSET);
228 *state = dif_bool_to_toggle(bitfield_bit32_read(clk_hints_val, clock));
236 if (clkmgr == NULL || !clkmgr_valid_hintable_clock(clock) ||
237 !dif_is_valid_toggle(new_state)) {
241 bool new_clk_hints_bit = dif_toggle_to_bool(new_state);
242 uint32_t clk_hints_val =
243 mmio_region_read32(clkmgr->
base_addr, CLKMGR_CLK_HINTS_REG_OFFSET);
244 clk_hints_val = bitfield_bit32_write(clk_hints_val, clock, new_clk_hints_bit);
245 mmio_region_write32(clkmgr->
base_addr, CLKMGR_CLK_HINTS_REG_OFFSET,
254 if (clkmgr == NULL || state == NULL || !clkmgr_valid_hintable_clock(clock)) {
258 uint32_t clk_hints_val =
259 mmio_region_read32(clkmgr->
base_addr, CLKMGR_CLK_HINTS_REG_OFFSET);
260 *state = dif_bool_to_toggle(bitfield_bit32_read(clk_hints_val, clock));
267 if (clkmgr == NULL || is_locked == NULL) {
271 *is_locked = extclk_control_register_is_locked(clkmgr);
278 if (clkmgr == NULL) {
281 mmio_region_write32(clkmgr->
base_addr, CLKMGR_EXTCLK_CTRL_REGWEN_REG_OFFSET,
288 uint32_t extclk_ctrl_reg = 0;
290 if (clkmgr == NULL) {
294 if (extclk_control_register_is_locked(clkmgr)) {
298 extclk_ctrl_reg = bitfield_field32_write(
299 extclk_ctrl_reg, CLKMGR_EXTCLK_CTRL_SEL_FIELD, kMultiBitBool4True);
300 extclk_ctrl_reg = bitfield_field32_write(
301 extclk_ctrl_reg, CLKMGR_EXTCLK_CTRL_HI_SPEED_SEL_FIELD,
302 is_low_speed ? kMultiBitBool4False : kMultiBitBool4True);
303 mmio_region_write32(clkmgr->
base_addr, CLKMGR_EXTCLK_CTRL_REG_OFFSET,
310 uint32_t extclk_ctrl_reg = 0;
312 if (clkmgr == NULL) {
316 if (extclk_control_register_is_locked(clkmgr)) {
320 extclk_ctrl_reg = bitfield_field32_write(
321 extclk_ctrl_reg, CLKMGR_EXTCLK_CTRL_SEL_FIELD, kMultiBitBool4False);
323 extclk_ctrl_reg = bitfield_field32_write(
324 extclk_ctrl_reg, CLKMGR_EXTCLK_CTRL_HI_SPEED_SEL_FIELD,
326 mmio_region_write32(clkmgr->
base_addr, CLKMGR_EXTCLK_CTRL_REG_OFFSET,
332 if (clkmgr == NULL) {
335 mmio_region_write32(clkmgr->
base_addr, CLKMGR_MEASURE_CTRL_REGWEN_REG_OFFSET,
342 if (clkmgr == NULL || state == NULL) {
345 *state = dif_bool_to_toggle(clkmgr_measure_ctrl_regwen(clkmgr));
351 dif_clkmgr_measure_clock_t *clock) {
352 if (clkmgr == NULL || clock == NULL) {
368 dif_clkmgr_measure_clock_t clock,
369 uint32_t lo_threshold,
370 uint32_t hi_threshold) {
371 if (clkmgr == NULL) {
374 if (!clkmgr_measure_ctrl_regwen(clkmgr)) {
385 uint32_t measure_ctrl_reg = 0;
386 measure_ctrl_reg = bitfield_field32_write(
388 measure_ctrl_reg = bitfield_field32_write(
396 uint32_t measure_en_reg =
405 const dif_clkmgr_t *clkmgr, dif_clkmgr_measure_clock_t clock) {
406 if (clkmgr == NULL) {
409 if (!clkmgr_measure_ctrl_regwen(clkmgr)) {
420 uint32_t measure_en_reg = bitfield_field32_write(
428 const dif_clkmgr_t *clkmgr, dif_clkmgr_measure_clock_t clock,
430 if (clkmgr == NULL || state == NULL) {
443 *state = dif_multi_bit_bool_to_toggle(
450 const dif_clkmgr_t *clkmgr, dif_clkmgr_measure_clock_t clock,
451 uint32_t *min_threshold, uint32_t *max_threshold) {
452 if (clkmgr == NULL || min_threshold == NULL || max_threshold == NULL) {
463 uint32_t thresholds_val = mmio_region_read32(
475 if (clkmgr == NULL || codes == NULL) {
479 mmio_region_read32(clkmgr->
base_addr, CLKMGR_RECOV_ERR_CODE_REG_OFFSET);
485 if (clkmgr == NULL) {
488 mmio_region_write32(clkmgr->
base_addr, CLKMGR_RECOV_ERR_CODE_REG_OFFSET,
495 if (clkmgr == NULL || codes == NULL) {
499 mmio_region_read32(clkmgr->
base_addr, CLKMGR_FATAL_ERR_CODE_REG_OFFSET);
504 if (clkmgr == NULL) {
510 mmio_region_read32(clkmgr->
base_addr, CLKMGR_EXTCLK_STATUS_REG_OFFSET);
511 }
while (ext_status != kMultiBitBool4True);