Software APIs
dif_aon_timer_unittest.cc
1 // Copyright lowRISC contributors (OpenTitan project).
2 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3 // SPDX-License-Identifier: Apache-2.0
4 
5 #include "sw/device/lib/dif/dif_aon_timer.h"
6 
7 #include "gtest/gtest.h"
8 #include "sw/device/lib/base/bitfield.h"
9 #include "sw/device/lib/base/mmio.h"
10 #include "sw/device/lib/base/mock_mmio.h"
11 #include "sw/device/lib/dif/dif_base.h"
12 #include "sw/device/lib/dif/dif_test_base.h"
13 
14 #include "aon_timer_regs.h" // Generated.
15 
16 namespace dif_aon_timer_unittest {
17 namespace {
18 using mock_mmio::MmioTest;
19 using mock_mmio::MockDevice;
20 using testing::Each;
21 using testing::Eq;
22 using testing::Test;
23 
24 class AonTimerTest : public Test, public MmioTest {
25  protected:
26  dif_aon_timer_t aon_ = {.base_addr = dev().region()};
27 };
28 
29 class WakeupStatusTest : public AonTimerTest {};
30 
31 TEST_F(WakeupStatusTest, GetNullArgs) {
32  bool cause;
33  EXPECT_DIF_BADARG(dif_aon_timer_get_wakeup_cause(nullptr, &cause));
34  EXPECT_DIF_BADARG(dif_aon_timer_get_wakeup_cause(&aon_, nullptr));
35 }
36 
37 TEST_F(WakeupStatusTest, GetSuccess) {
38  bool cause = false;
39  EXPECT_READ32(AON_TIMER_WKUP_CAUSE_REG_OFFSET, 1);
40  EXPECT_DIF_OK(dif_aon_timer_get_wakeup_cause(&aon_, &cause));
41  EXPECT_EQ(cause, true);
42 }
43 
44 TEST_F(WakeupStatusTest, ClearNullArgs) {
45  EXPECT_DIF_BADARG(dif_aon_timer_clear_wakeup_cause(nullptr));
46 }
47 
48 TEST_F(WakeupStatusTest, ClearSuccess) {
49  EXPECT_WRITE32(AON_TIMER_WKUP_CAUSE_REG_OFFSET, 0);
50  EXPECT_DIF_OK(dif_aon_timer_clear_wakeup_cause(&aon_));
51 }
52 
53 class WakeupStartTest : public AonTimerTest {};
54 
55 TEST_F(WakeupStartTest, NullArgs) {
56  EXPECT_DIF_BADARG(dif_aon_timer_wakeup_start(nullptr, 1, 1));
57 }
58 
59 TEST_F(WakeupStartTest, BadPrescaler) {
60  EXPECT_DIF_BADARG(dif_aon_timer_wakeup_start(
61  &aon_, 1, AON_TIMER_WKUP_CTRL_PRESCALER_MASK + 1));
62 }
63 
64 TEST_F(WakeupStartTest, Success) {
65  EXPECT_READ32(AON_TIMER_WKUP_CTRL_REG_OFFSET, 0);
66  EXPECT_WRITE32(AON_TIMER_WKUP_CTRL_REG_OFFSET,
67  {
68  {AON_TIMER_WKUP_CTRL_ENABLE_BIT, false},
69  });
70  EXPECT_WRITE32(AON_TIMER_WKUP_COUNT_LO_REG_OFFSET, 0);
71  EXPECT_WRITE32(AON_TIMER_WKUP_COUNT_HI_REG_OFFSET, 0);
72  EXPECT_WRITE32(AON_TIMER_WKUP_THOLD_LO_REG_OFFSET, 0);
73  EXPECT_WRITE32(AON_TIMER_WKUP_THOLD_HI_REG_OFFSET, 0);
74  EXPECT_WRITE32(AON_TIMER_WKUP_CTRL_REG_OFFSET,
75  {
76  {
77  AON_TIMER_WKUP_CTRL_PRESCALER_OFFSET,
78  AON_TIMER_WKUP_CTRL_PRESCALER_MASK,
79  },
80  {AON_TIMER_WKUP_CTRL_ENABLE_BIT, true},
81  });
82 
83  EXPECT_DIF_OK(
84  dif_aon_timer_wakeup_start(&aon_, 1, AON_TIMER_WKUP_CTRL_PRESCALER_MASK));
85 }
86 
87 class WakeupStopTest : public AonTimerTest {};
88 
89 TEST_F(WakeupStopTest, NullArgs) {
90  EXPECT_DIF_BADARG(dif_aon_timer_wakeup_stop(nullptr));
91 }
92 
93 TEST_F(WakeupStopTest, Success) {
94  EXPECT_READ32(AON_TIMER_WKUP_CTRL_REG_OFFSET,
95  {
96  {AON_TIMER_WKUP_CTRL_ENABLE_BIT, true},
97  });
98  EXPECT_WRITE32(AON_TIMER_WKUP_CTRL_REG_OFFSET,
99  {
100  {AON_TIMER_WKUP_CTRL_ENABLE_BIT, false},
101  });
102 
103  EXPECT_DIF_OK(dif_aon_timer_wakeup_stop(&aon_));
104 }
105 
106 class WakeupRestartTest : public AonTimerTest {};
107 
108 TEST_F(WakeupRestartTest, NullArgs) {
109  EXPECT_DIF_BADARG(dif_aon_timer_wakeup_restart(nullptr));
110 }
111 
112 TEST_F(WakeupRestartTest, Success) {
113  EXPECT_READ32(AON_TIMER_WKUP_CTRL_REG_OFFSET, 0);
114  EXPECT_WRITE32(AON_TIMER_WKUP_CTRL_REG_OFFSET,
115  {
116  {AON_TIMER_WKUP_CTRL_ENABLE_BIT, false},
117  });
118  EXPECT_WRITE32(AON_TIMER_WKUP_COUNT_LO_REG_OFFSET, 0);
119  EXPECT_WRITE32(AON_TIMER_WKUP_COUNT_HI_REG_OFFSET, 0);
120  EXPECT_READ32(AON_TIMER_WKUP_CTRL_REG_OFFSET, 0);
121  EXPECT_WRITE32(AON_TIMER_WKUP_CTRL_REG_OFFSET,
122  {
123  {AON_TIMER_WKUP_CTRL_ENABLE_BIT, true},
124  });
125 
126  EXPECT_DIF_OK(dif_aon_timer_wakeup_restart(&aon_));
127 }
128 
129 class WakeupGetCountTest : public AonTimerTest {};
130 
131 TEST_F(WakeupGetCountTest, NullArgs) {
132  EXPECT_DIF_BADARG(dif_aon_timer_wakeup_get_count(nullptr, nullptr));
133  EXPECT_DIF_BADARG(dif_aon_timer_wakeup_get_count(&aon_, nullptr));
134  uint64_t count;
135  EXPECT_DIF_BADARG(dif_aon_timer_wakeup_get_count(nullptr, &count));
136 }
137 
138 TEST_F(WakeupGetCountTest, Success) {
139  EXPECT_READ32(AON_TIMER_WKUP_COUNT_HI_REG_OFFSET, 0xA5A5A5A5);
140  EXPECT_READ32(AON_TIMER_WKUP_COUNT_LO_REG_OFFSET, 0xA5A5A5A5);
141  EXPECT_READ32(AON_TIMER_WKUP_COUNT_HI_REG_OFFSET, 0xA5A5A5A5);
142 
143  uint64_t count;
144  EXPECT_DIF_OK(dif_aon_timer_wakeup_get_count(&aon_, &count));
145  EXPECT_EQ(count, 0xA5A5A5A5A5A5A5A5);
146 }
147 
148 TEST_F(WakeupGetCountTest, OverflowSuccess) {
149  EXPECT_READ32(AON_TIMER_WKUP_COUNT_HI_REG_OFFSET, 0xA5A5A5A5);
150  EXPECT_READ32(AON_TIMER_WKUP_COUNT_LO_REG_OFFSET, 0xA5A5A5A5);
151  EXPECT_READ32(AON_TIMER_WKUP_COUNT_HI_REG_OFFSET, 0xA5A5A5A6);
152  EXPECT_READ32(AON_TIMER_WKUP_COUNT_LO_REG_OFFSET, 0x5A5A5A5A);
153 
154  uint64_t count;
155  EXPECT_DIF_OK(dif_aon_timer_wakeup_get_count(&aon_, &count));
156  EXPECT_EQ(count, 0xA5A5A5A65A5A5A5A);
157 }
158 
159 class WatchdogStartTest : public AonTimerTest {
160  protected:
161  void SuccessCommon() {
162  EXPECT_READ32(AON_TIMER_WDOG_REGWEN_REG_OFFSET, 1);
163  EXPECT_READ32(AON_TIMER_WDOG_CTRL_REG_OFFSET, 0);
164  EXPECT_WRITE32(AON_TIMER_WDOG_CTRL_REG_OFFSET,
165  {
166  {AON_TIMER_WDOG_CTRL_ENABLE_BIT, false},
167  });
168  EXPECT_WRITE32(AON_TIMER_WDOG_COUNT_REG_OFFSET, 0);
169  // below BARK/BITE are the call value - 1 to accomodate the AON_TIMER IP
170  // characteristic
171  EXPECT_WRITE32(AON_TIMER_WDOG_BARK_THOLD_REG_OFFSET, 0xA5A5A5A4);
172  EXPECT_WRITE32(AON_TIMER_WDOG_BITE_THOLD_REG_OFFSET, 0x5A5A5A59);
173  }
174 };
175 
176 TEST_F(WatchdogStartTest, NullArgs) {
177  EXPECT_DIF_BADARG(dif_aon_timer_watchdog_start(nullptr, 1, 1, false, false));
178 }
179 
180 TEST_F(WatchdogStartTest, Locked) {
181  EXPECT_READ32(AON_TIMER_WDOG_REGWEN_REG_OFFSET, 0);
182  EXPECT_EQ(dif_aon_timer_watchdog_start(&aon_, 1, 1, false, false),
183  kDifLocked);
184 }
185 
186 TEST_F(WatchdogStartTest, Success) {
187  SuccessCommon();
188 
189  EXPECT_WRITE32(AON_TIMER_WDOG_CTRL_REG_OFFSET,
190  {
191  {
192  AON_TIMER_WDOG_CTRL_PAUSE_IN_SLEEP_BIT,
193  false,
194  },
195  {AON_TIMER_WDOG_CTRL_ENABLE_BIT, true},
196  });
197 
198  EXPECT_DIF_OK(dif_aon_timer_watchdog_start(&aon_, 0xA5A5A5A5, 0x5A5A5A5A,
199  false, false));
200 }
201 
202 TEST_F(WatchdogStartTest, SuccessPauseInSleep) {
203  SuccessCommon();
204 
205  EXPECT_WRITE32(AON_TIMER_WDOG_CTRL_REG_OFFSET,
206  {
207  {
208  AON_TIMER_WDOG_CTRL_PAUSE_IN_SLEEP_BIT,
209  true,
210  },
211  {AON_TIMER_WDOG_CTRL_ENABLE_BIT, true},
212  });
213 
214  EXPECT_DIF_OK(
215  dif_aon_timer_watchdog_start(&aon_, 0xA5A5A5A5, 0x5A5A5A5A, true, false));
216 }
217 
218 TEST_F(WatchdogStartTest, SuccessLock) {
219  SuccessCommon();
220 
221  EXPECT_WRITE32(AON_TIMER_WDOG_CTRL_REG_OFFSET,
222  {
223  {
224  AON_TIMER_WDOG_CTRL_PAUSE_IN_SLEEP_BIT,
225  false,
226  },
227  {AON_TIMER_WDOG_CTRL_ENABLE_BIT, true},
228  });
229 
230  EXPECT_WRITE32(AON_TIMER_WDOG_REGWEN_REG_OFFSET, 1);
231 
232  EXPECT_DIF_OK(
233  dif_aon_timer_watchdog_start(&aon_, 0xA5A5A5A5, 0x5A5A5A5A, false, true));
234 }
235 
236 TEST_F(WatchdogStartTest, SuccessPauseInSleepAndLock) {
237  SuccessCommon();
238 
239  EXPECT_WRITE32(AON_TIMER_WDOG_CTRL_REG_OFFSET,
240  {
241  {
242  AON_TIMER_WDOG_CTRL_PAUSE_IN_SLEEP_BIT,
243  true,
244  },
245  {AON_TIMER_WDOG_CTRL_ENABLE_BIT, true},
246  });
247 
248  EXPECT_WRITE32(AON_TIMER_WDOG_REGWEN_REG_OFFSET, 1);
249 
250  EXPECT_DIF_OK(
251  dif_aon_timer_watchdog_start(&aon_, 0xA5A5A5A5, 0x5A5A5A5A, true, true));
252 }
253 
254 class WatchdogStopTest : public AonTimerTest {};
255 
256 TEST_F(WatchdogStopTest, NullArgs) {
257  EXPECT_DIF_BADARG(dif_aon_timer_watchdog_stop(nullptr));
258 }
259 
260 TEST_F(WatchdogStopTest, Locked) {
261  EXPECT_READ32(AON_TIMER_WDOG_REGWEN_REG_OFFSET, 0);
262 
263  EXPECT_EQ(dif_aon_timer_watchdog_stop(&aon_), kDifLocked);
264 }
265 
266 TEST_F(WatchdogStopTest, Success) {
267  EXPECT_READ32(AON_TIMER_WDOG_REGWEN_REG_OFFSET, 1);
268  EXPECT_READ32(AON_TIMER_WDOG_CTRL_REG_OFFSET,
269  {
270  {AON_TIMER_WDOG_CTRL_ENABLE_BIT, true},
271  });
272  EXPECT_WRITE32(AON_TIMER_WDOG_CTRL_REG_OFFSET,
273  {
274  {AON_TIMER_WDOG_CTRL_ENABLE_BIT, false},
275  });
276 
277  EXPECT_DIF_OK(dif_aon_timer_watchdog_stop(&aon_));
278 }
279 
280 class WatchdogRestartTest : public AonTimerTest {};
281 
282 TEST_F(WatchdogRestartTest, NullArgs) {
283  EXPECT_DIF_BADARG(dif_aon_timer_watchdog_restart(nullptr));
284 }
285 
286 TEST_F(WatchdogRestartTest, Locked) {
287  EXPECT_READ32(AON_TIMER_WDOG_REGWEN_REG_OFFSET, 0);
288  EXPECT_EQ(dif_aon_timer_watchdog_restart(&aon_), kDifLocked);
289 }
290 
291 TEST_F(WatchdogRestartTest, Success) {
292  EXPECT_READ32(AON_TIMER_WDOG_REGWEN_REG_OFFSET, 1);
293  EXPECT_WRITE32(AON_TIMER_WDOG_COUNT_REG_OFFSET, 0);
294  EXPECT_READ32(AON_TIMER_WDOG_CTRL_REG_OFFSET, 0);
295  EXPECT_WRITE32(AON_TIMER_WDOG_CTRL_REG_OFFSET,
296  {
297  {AON_TIMER_WDOG_CTRL_ENABLE_BIT, true},
298  });
299 
300  EXPECT_DIF_OK(dif_aon_timer_watchdog_restart(&aon_));
301 }
302 
303 class WatchdogGetCountTest : public AonTimerTest {};
304 
305 TEST_F(WatchdogGetCountTest, NullArgs) {
306  EXPECT_DIF_BADARG(dif_aon_timer_watchdog_get_count(nullptr, nullptr));
307  EXPECT_DIF_BADARG(dif_aon_timer_watchdog_get_count(&aon_, nullptr));
308  uint32_t count;
309  EXPECT_DIF_BADARG(dif_aon_timer_watchdog_get_count(nullptr, &count));
310 }
311 
312 TEST_F(WatchdogGetCountTest, Success) {
313  EXPECT_READ32(AON_TIMER_WDOG_COUNT_REG_OFFSET, 0xA5A5A5A5);
314 
315  uint32_t count;
316  EXPECT_DIF_OK(dif_aon_timer_watchdog_get_count(&aon_, &count));
317  EXPECT_EQ(count, 0xA5A5A5A5);
318 }
319 
320 class WatchdogPetTest : public AonTimerTest {};
321 
322 TEST_F(WatchdogPetTest, NullArgs) {
323  EXPECT_DIF_BADARG(dif_aon_timer_watchdog_pet(nullptr));
324 }
325 
326 TEST_F(WatchdogPetTest, Success) {
327  EXPECT_WRITE32(AON_TIMER_WDOG_COUNT_REG_OFFSET, 0);
328 
329  EXPECT_DIF_OK(dif_aon_timer_watchdog_pet(&aon_));
330 }
331 
332 class WatchdogLockTest : public AonTimerTest {};
333 
334 TEST_F(WatchdogLockTest, NullArgs) {
335  EXPECT_DIF_BADARG(dif_aon_timer_watchdog_lock(nullptr));
336 }
337 
338 TEST_F(WatchdogLockTest, Success) {
339  EXPECT_WRITE32(AON_TIMER_WDOG_REGWEN_REG_OFFSET, 1);
340 
341  EXPECT_DIF_OK(dif_aon_timer_watchdog_lock(&aon_));
342 }
343 
344 class WatchdogIsLockedTest : public AonTimerTest {};
345 
346 TEST_F(WatchdogIsLockedTest, NullArgs) {
347  EXPECT_DIF_BADARG(dif_aon_timer_watchdog_is_locked(nullptr, nullptr));
348  EXPECT_DIF_BADARG(dif_aon_timer_watchdog_is_locked(&aon_, nullptr));
349  bool is_locked;
350  EXPECT_DIF_BADARG(dif_aon_timer_watchdog_is_locked(nullptr, &is_locked));
351 }
352 
353 TEST_F(WatchdogIsLockedTest, Success) {
354  EXPECT_READ32(AON_TIMER_WDOG_REGWEN_REG_OFFSET, 1);
355 
356  bool is_locked;
357  EXPECT_DIF_OK(dif_aon_timer_watchdog_is_locked(&aon_, &is_locked));
358  EXPECT_EQ(is_locked, false);
359 }
360 
361 TEST_F(WatchdogIsLockedTest, SuccessLocked) {
362  EXPECT_READ32(AON_TIMER_WDOG_REGWEN_REG_OFFSET, 0);
363 
364  bool is_locked;
365  EXPECT_DIF_OK(dif_aon_timer_watchdog_is_locked(&aon_, &is_locked));
366  EXPECT_EQ(is_locked, true);
367 }
368 
369 } // namespace
370 } // namespace dif_aon_timer_unittest
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