Software APIs
dif_alert_handler_autogen.c
1 // Copyright lowRISC contributors (OpenTitan project).
2 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3 // SPDX-License-Identifier: Apache-2.0
4 
5 // THIS FILE HAS BEEN GENERATED, DO NOT EDIT MANUALLY. COMMAND:
6 // util/make_new_dif.py --mode=regen --only=autogen
7 
8 #include "sw/device/lib/dif/autogen/dif_alert_handler_autogen.h"
9 
10 #include <stdint.h>
11 
12 #include "sw/device/lib/dif/dif_base.h"
13 
14 #include "alert_handler_regs.h" // Generated.
15 
16 OT_WARN_UNUSED_RESULT
17 dif_result_t dif_alert_handler_init(mmio_region_t base_addr,
18  dif_alert_handler_t *alert_handler) {
19  if (alert_handler == NULL) {
20  return kDifBadArg;
21  }
22 
23  alert_handler->base_addr = base_addr;
24 
25  return kDifOk;
26 }
27 
28 /**
29  * Get the corresponding interrupt register bit offset of the IRQ.
30  */
31 static bool alert_handler_get_irq_bit_index(dif_alert_handler_irq_t irq,
32  bitfield_bit32_index_t *index_out) {
33  switch (irq) {
34  case kDifAlertHandlerIrqClassa:
35  *index_out = ALERT_HANDLER_INTR_COMMON_CLASSA_BIT;
36  break;
37  case kDifAlertHandlerIrqClassb:
38  *index_out = ALERT_HANDLER_INTR_COMMON_CLASSB_BIT;
39  break;
40  case kDifAlertHandlerIrqClassc:
41  *index_out = ALERT_HANDLER_INTR_COMMON_CLASSC_BIT;
42  break;
43  case kDifAlertHandlerIrqClassd:
44  *index_out = ALERT_HANDLER_INTR_COMMON_CLASSD_BIT;
45  break;
46  default:
47  return false;
48  }
49 
50  return true;
51 }
52 
53 static dif_irq_type_t irq_types[] = {
54  kDifIrqTypeEvent,
55  kDifIrqTypeEvent,
56  kDifIrqTypeEvent,
57  kDifIrqTypeEvent,
58 };
59 
60 OT_WARN_UNUSED_RESULT
61 dif_result_t dif_alert_handler_irq_get_type(
62  const dif_alert_handler_t *alert_handler, dif_alert_handler_irq_t irq,
63  dif_irq_type_t *type) {
64  if (alert_handler == NULL || type == NULL ||
65  irq == kDifAlertHandlerIrqClassd + 1) {
66  return kDifBadArg;
67  }
68 
69  *type = irq_types[irq];
70 
71  return kDifOk;
72 }
73 
74 OT_WARN_UNUSED_RESULT
75 dif_result_t dif_alert_handler_irq_get_state(
76  const dif_alert_handler_t *alert_handler,
77  dif_alert_handler_irq_state_snapshot_t *snapshot) {
78  if (alert_handler == NULL || snapshot == NULL) {
79  return kDifBadArg;
80  }
81 
82  *snapshot = mmio_region_read32(
83  alert_handler->base_addr, (ptrdiff_t)ALERT_HANDLER_INTR_STATE_REG_OFFSET);
84 
85  return kDifOk;
86 }
87 
88 OT_WARN_UNUSED_RESULT
89 dif_result_t dif_alert_handler_irq_acknowledge_state(
90  const dif_alert_handler_t *alert_handler,
91  dif_alert_handler_irq_state_snapshot_t snapshot) {
92  if (alert_handler == NULL) {
93  return kDifBadArg;
94  }
95 
96  mmio_region_write32(alert_handler->base_addr,
97  (ptrdiff_t)ALERT_HANDLER_INTR_STATE_REG_OFFSET, snapshot);
98 
99  return kDifOk;
100 }
101 
102 OT_WARN_UNUSED_RESULT
103 dif_result_t dif_alert_handler_irq_is_pending(
104  const dif_alert_handler_t *alert_handler, dif_alert_handler_irq_t irq,
105  bool *is_pending) {
106  if (alert_handler == NULL || is_pending == NULL) {
107  return kDifBadArg;
108  }
109 
110  bitfield_bit32_index_t index;
111  if (!alert_handler_get_irq_bit_index(irq, &index)) {
112  return kDifBadArg;
113  }
114 
115  uint32_t intr_state_reg = mmio_region_read32(
116  alert_handler->base_addr, (ptrdiff_t)ALERT_HANDLER_INTR_STATE_REG_OFFSET);
117 
118  *is_pending = bitfield_bit32_read(intr_state_reg, index);
119 
120  return kDifOk;
121 }
122 
123 OT_WARN_UNUSED_RESULT
124 dif_result_t dif_alert_handler_irq_acknowledge_all(
125  const dif_alert_handler_t *alert_handler) {
126  if (alert_handler == NULL) {
127  return kDifBadArg;
128  }
129 
130  // Writing to the register clears the corresponding bits (Write-one clear).
131  mmio_region_write32(alert_handler->base_addr,
132  (ptrdiff_t)ALERT_HANDLER_INTR_STATE_REG_OFFSET,
133  UINT32_MAX);
134 
135  return kDifOk;
136 }
137 
138 OT_WARN_UNUSED_RESULT
139 dif_result_t dif_alert_handler_irq_acknowledge(
140  const dif_alert_handler_t *alert_handler, dif_alert_handler_irq_t irq) {
141  if (alert_handler == NULL) {
142  return kDifBadArg;
143  }
144 
145  bitfield_bit32_index_t index;
146  if (!alert_handler_get_irq_bit_index(irq, &index)) {
147  return kDifBadArg;
148  }
149 
150  // Writing to the register clears the corresponding bits (Write-one clear).
151  uint32_t intr_state_reg = bitfield_bit32_write(0, index, true);
152  mmio_region_write32(alert_handler->base_addr,
153  (ptrdiff_t)ALERT_HANDLER_INTR_STATE_REG_OFFSET,
154  intr_state_reg);
155 
156  return kDifOk;
157 }
158 
159 OT_WARN_UNUSED_RESULT
160 dif_result_t dif_alert_handler_irq_force(
161  const dif_alert_handler_t *alert_handler, dif_alert_handler_irq_t irq,
162  const bool val) {
163  if (alert_handler == NULL) {
164  return kDifBadArg;
165  }
166 
167  bitfield_bit32_index_t index;
168  if (!alert_handler_get_irq_bit_index(irq, &index)) {
169  return kDifBadArg;
170  }
171 
172  uint32_t intr_test_reg = bitfield_bit32_write(0, index, val);
173  mmio_region_write32(alert_handler->base_addr,
174  (ptrdiff_t)ALERT_HANDLER_INTR_TEST_REG_OFFSET,
175  intr_test_reg);
176 
177  return kDifOk;
178 }
179 
180 OT_WARN_UNUSED_RESULT
181 dif_result_t dif_alert_handler_irq_get_enabled(
182  const dif_alert_handler_t *alert_handler, dif_alert_handler_irq_t irq,
183  dif_toggle_t *state) {
184  if (alert_handler == NULL || state == NULL) {
185  return kDifBadArg;
186  }
187 
188  bitfield_bit32_index_t index;
189  if (!alert_handler_get_irq_bit_index(irq, &index)) {
190  return kDifBadArg;
191  }
192 
193  uint32_t intr_enable_reg =
194  mmio_region_read32(alert_handler->base_addr,
195  (ptrdiff_t)ALERT_HANDLER_INTR_ENABLE_REG_OFFSET);
196 
197  bool is_enabled = bitfield_bit32_read(intr_enable_reg, index);
198  *state = is_enabled ? kDifToggleEnabled : kDifToggleDisabled;
199 
200  return kDifOk;
201 }
202 
203 OT_WARN_UNUSED_RESULT
204 dif_result_t dif_alert_handler_irq_set_enabled(
205  const dif_alert_handler_t *alert_handler, dif_alert_handler_irq_t irq,
206  dif_toggle_t state) {
207  if (alert_handler == NULL) {
208  return kDifBadArg;
209  }
210 
211  bitfield_bit32_index_t index;
212  if (!alert_handler_get_irq_bit_index(irq, &index)) {
213  return kDifBadArg;
214  }
215 
216  uint32_t intr_enable_reg =
217  mmio_region_read32(alert_handler->base_addr,
218  (ptrdiff_t)ALERT_HANDLER_INTR_ENABLE_REG_OFFSET);
219 
220  bool enable_bit = (state == kDifToggleEnabled) ? true : false;
221  intr_enable_reg = bitfield_bit32_write(intr_enable_reg, index, enable_bit);
222  mmio_region_write32(alert_handler->base_addr,
223  (ptrdiff_t)ALERT_HANDLER_INTR_ENABLE_REG_OFFSET,
224  intr_enable_reg);
225 
226  return kDifOk;
227 }
228 
229 OT_WARN_UNUSED_RESULT
230 dif_result_t dif_alert_handler_irq_disable_all(
231  const dif_alert_handler_t *alert_handler,
232  dif_alert_handler_irq_enable_snapshot_t *snapshot) {
233  if (alert_handler == NULL) {
234  return kDifBadArg;
235  }
236 
237  // Pass the current interrupt state to the caller, if requested.
238  if (snapshot != NULL) {
239  *snapshot =
240  mmio_region_read32(alert_handler->base_addr,
241  (ptrdiff_t)ALERT_HANDLER_INTR_ENABLE_REG_OFFSET);
242  }
243 
244  // Disable all interrupts.
245  mmio_region_write32(alert_handler->base_addr,
246  (ptrdiff_t)ALERT_HANDLER_INTR_ENABLE_REG_OFFSET, 0u);
247 
248  return kDifOk;
249 }
250 
251 OT_WARN_UNUSED_RESULT
252 dif_result_t dif_alert_handler_irq_restore_all(
253  const dif_alert_handler_t *alert_handler,
254  const dif_alert_handler_irq_enable_snapshot_t *snapshot) {
255  if (alert_handler == NULL || snapshot == NULL) {
256  return kDifBadArg;
257  }
258 
259  mmio_region_write32(alert_handler->base_addr,
260  (ptrdiff_t)ALERT_HANDLER_INTR_ENABLE_REG_OFFSET,
261  *snapshot);
262 
263  return kDifOk;
264 }
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