155 if (alert_handler == NULL || alert >= ALERT_HANDLER_PARAM_N_ALERTS ||
156 !dif_is_valid_toggle(enabled) || !dif_is_valid_toggle(locked)) {
159 uint32_t classification;
160 if (!class_to_uint32(alert_class, &classification)) {
165 ptrdiff_t regwen_offset = ALERT_HANDLER_ALERT_REGWEN_0_REG_OFFSET +
166 (ptrdiff_t)alert * (ptrdiff_t)
sizeof(uint32_t);
167 if (!mmio_region_read32(alert_handler->
base_addr, regwen_offset)) {
172 ptrdiff_t class_reg_offset = ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_OFFSET +
173 (ptrdiff_t)alert * (ptrdiff_t)
sizeof(uint32_t);
174 mmio_region_write32_shadowed(alert_handler->
base_addr, class_reg_offset,
178 ptrdiff_t enable_reg_offset = ALERT_HANDLER_ALERT_EN_SHADOWED_0_REG_OFFSET +
179 (ptrdiff_t)alert * (ptrdiff_t)
sizeof(uint32_t);
180 mmio_region_write32_shadowed(alert_handler->
base_addr, enable_reg_offset,
185 mmio_region_write32(alert_handler->
base_addr, regwen_offset, 0);
254 if (alert_handler == NULL ||
259 !dif_is_valid_toggle(enabled) || !dif_is_valid_toggle(locked)) {
275#define ALERT_CLASS_CONFIG_REGS_CASE_(class_, value_) \
276 case kDifAlertHandlerClass##class_: \
277 class_regwen_offset = ALERT_HANDLER_CLASS##class_##_REGWEN_REG_OFFSET; \
278 ctrl_reg_offset = ALERT_HANDLER_CLASS##class_##_CTRL_SHADOWED_REG_OFFSET; \
279 accum_thresh_reg_offset = \
280 ALERT_HANDLER_CLASS##class_##_ACCUM_THRESH_SHADOWED_REG_OFFSET; \
281 irq_deadline_reg_offset = \
282 ALERT_HANDLER_CLASS##class_##_TIMEOUT_CYC_SHADOWED_REG_OFFSET; \
283 phase0_cycles_reg_offset = \
284 ALERT_HANDLER_CLASS##class_##_PHASE0_CYC_SHADOWED_REG_OFFSET; \
285 phase1_cycles_reg_offset = \
286 ALERT_HANDLER_CLASS##class_##_PHASE1_CYC_SHADOWED_REG_OFFSET; \
287 phase2_cycles_reg_offset = \
288 ALERT_HANDLER_CLASS##class_##_PHASE2_CYC_SHADOWED_REG_OFFSET; \
289 phase3_cycles_reg_offset = \
290 ALERT_HANDLER_CLASS##class_##_PHASE3_CYC_SHADOWED_REG_OFFSET; \
291 crashdump_phase_reg_offset = \
292 ALERT_HANDLER_CLASS##class_##_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET; \
295 ptrdiff_t class_regwen_offset;
296 ptrdiff_t ctrl_reg_offset;
297 ptrdiff_t accum_thresh_reg_offset;
298 ptrdiff_t irq_deadline_reg_offset;
299 ptrdiff_t phase0_cycles_reg_offset;
300 ptrdiff_t phase1_cycles_reg_offset;
301 ptrdiff_t phase2_cycles_reg_offset;
302 ptrdiff_t phase3_cycles_reg_offset;
303 ptrdiff_t crashdump_phase_reg_offset;
304 switch (alert_class) {
310#undef ALERT_CLASS_CONFIG_REGS_CASE_
313 if (!mmio_region_read32(alert_handler->
base_addr, class_regwen_offset)) {
322 uint32_t ctrl_reg = 0;
324 bitfield_bit32_write(ctrl_reg, ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_BIT,
325 dif_toggle_to_bool(enabled));
326 ctrl_reg = bitfield_bit32_write(
327 ctrl_reg, ALERT_HANDLER_CLASSA_CTRL_SHADOWED_LOCK_BIT,
338 if (!is_valid_escalation_phase(phase)) {
353 signal_enable_bit = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E0_BIT;
354 signal_map_field = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E0_FIELD;
357 signal_enable_bit = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E1_BIT;
358 signal_map_field = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E1_FIELD;
361 signal_enable_bit = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E2_BIT;
362 signal_map_field = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_FIELD;
365 signal_enable_bit = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E3_BIT;
366 signal_map_field = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_FIELD;
377 if (signal == 0xFFFFFFFF) {
378 ctrl_reg = bitfield_bit32_write(
379 ctrl_reg, ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E0_BIT,
false);
380 ctrl_reg = bitfield_field32_write(
381 ctrl_reg, ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E0_FIELD,
383 ctrl_reg = bitfield_bit32_write(
384 ctrl_reg, ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E1_BIT,
false);
385 ctrl_reg = bitfield_field32_write(
386 ctrl_reg, ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E1_FIELD,
388 ctrl_reg = bitfield_bit32_write(
389 ctrl_reg, ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E2_BIT,
false);
390 ctrl_reg = bitfield_field32_write(
391 ctrl_reg, ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_FIELD,
393 ctrl_reg = bitfield_bit32_write(
394 ctrl_reg, ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E3_BIT,
false);
395 ctrl_reg = bitfield_field32_write(
396 ctrl_reg, ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_FIELD,
399 ctrl_reg = bitfield_bit32_write(ctrl_reg, signal_enable_bit,
true);
400 ctrl_reg = bitfield_field32_write(
401 ctrl_reg, signal_map_field,
407 mmio_region_write32_shadowed(
408 alert_handler->
base_addr, phase0_cycles_reg_offset,
412 mmio_region_write32_shadowed(
413 alert_handler->
base_addr, phase1_cycles_reg_offset,
417 mmio_region_write32_shadowed(
418 alert_handler->
base_addr, phase2_cycles_reg_offset,
422 mmio_region_write32_shadowed(
423 alert_handler->
base_addr, phase3_cycles_reg_offset,
432 mmio_region_write32_shadowed(alert_handler->
base_addr,
433 accum_thresh_reg_offset,
437 mmio_region_write32_shadowed(alert_handler->
base_addr,
438 irq_deadline_reg_offset,
442 mmio_region_write32_shadowed(alert_handler->
base_addr,
443 crashdump_phase_reg_offset,
448 mmio_region_write32_shadowed(alert_handler->
base_addr, ctrl_reg_offset,
453 mmio_region_write32(alert_handler->
base_addr, class_regwen_offset, 0);
462 if (alert_handler == NULL ||
464 ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_PING_TIMEOUT_CYC_SHADOWED_MASK ||
465 !dif_is_valid_toggle(enabled) || !dif_is_valid_toggle(locked)) {
470 if (!mmio_region_read32(alert_handler->
base_addr,
471 ALERT_HANDLER_PING_TIMER_REGWEN_REG_OFFSET)) {
476 mmio_region_write32_shadowed(
478 ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_REG_OFFSET, ping_timeout);
484 mmio_region_write32_shadowed(
486 ALERT_HANDLER_PING_TIMER_EN_SHADOWED_REG_OFFSET, 1);
491 mmio_region_write32(alert_handler->
base_addr,
492 ALERT_HANDLER_PING_TIMER_REGWEN_REG_OFFSET, 0);
842 if (alert_handler == NULL || state == NULL) {
846#define ALERT_CLASS_STATE_CASE_(class_, value_) \
847 case kDifAlertHandlerClass##class_: \
848 reg_offset = ALERT_HANDLER_CLASS##class_##_STATE_REG_OFFSET; \
849 field = ALERT_HANDLER_CLASS##class_##_STATE_CLASS##class_##_STATE_FIELD; \
852 ptrdiff_t reg_offset;
854 switch (alert_class) {
860#undef ALERT_CLASS_STATE_CASE_
862 uint32_t reg = mmio_region_read32(alert_handler->
base_addr, reg_offset);
863 switch (bitfield_field32_read(reg, field)) {
864 case ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_IDLE:
867 case ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_TIMEOUT:
870 case ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_FSMERROR:
873 case ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_TERMINAL:
876 case ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE0:
879 case ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE1:
882 case ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE2:
885 case ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE3: