Software APIs
dif_adc_ctrl_unittest.cc
1 // Copyright lowRISC contributors (OpenTitan project).
2 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3 // SPDX-License-Identifier: Apache-2.0
4 
5 #include "sw/device/lib/dif/dif_adc_ctrl.h"
6 
7 #include "gtest/gtest.h"
8 #include "sw/device/lib/base/bitfield.h"
9 #include "sw/device/lib/base/mock_mmio.h"
10 #include "sw/device/lib/dif/dif_base.h"
11 #include "sw/device/lib/dif/dif_test_base.h"
12 
13 #include "adc_ctrl_regs.h" // Generated.
14 
15 namespace dif_adc_ctrl_unittest {
16 namespace {
17 using ::mock_mmio::LeInt;
18 using ::mock_mmio::MmioTest;
19 using ::mock_mmio::MockDevice;
20 
21 class AdcCtrlTest : public testing::Test, public MmioTest {
22  protected:
23  dif_adc_ctrl_t adc_ctrl_ = {.base_addr = dev().region()};
24  dif_adc_ctrl_config_t config_ = {
25  .mode = kDifAdcCtrlLowPowerScanMode,
26  .power_up_time_aon_cycles = 8,
27  .wake_up_time_aon_cycles = 128,
28  .num_low_power_samples = 4,
29  .num_normal_power_samples = 32,
30  };
31  dif_adc_ctrl_filter_config_t filter_config_ = {
32  .filter = kDifAdcCtrlFilter2,
33  .min_voltage = 512,
34  .max_voltage = 768,
35  .in_range = true,
36  .generate_wakeup_on_match = true,
37  .generate_irq_on_match = true,
38  };
39 };
40 
41 class ConfigTest : public AdcCtrlTest {};
42 
43 TEST_F(ConfigTest, NullHandle) {
44  EXPECT_DIF_BADARG(dif_adc_ctrl_configure(nullptr, config_));
45 }
46 
47 TEST_F(ConfigTest, BadMode) {
48  config_.mode = static_cast<dif_adc_ctrl_mode_t>(3);
49  EXPECT_DIF_BADARG(dif_adc_ctrl_configure(&adc_ctrl_, config_));
50 }
51 
52 TEST_F(ConfigTest, BadPowerUpTime) {
53  config_.power_up_time_aon_cycles = ADC_CTRL_ADC_PD_CTL_PWRUP_TIME_MASK + 1;
54  EXPECT_DIF_BADARG(dif_adc_ctrl_configure(&adc_ctrl_, config_));
55 }
56 
57 TEST_F(ConfigTest, BadWakeUpTime) {
58  config_.wake_up_time_aon_cycles = ADC_CTRL_ADC_PD_CTL_WAKEUP_TIME_MASK + 1;
59  EXPECT_DIF_BADARG(dif_adc_ctrl_configure(&adc_ctrl_, config_));
60 }
61 
62 TEST_F(ConfigTest, BadNumLowPowerSamples) {
63  config_.num_low_power_samples = 0;
64  EXPECT_DIF_BADARG(dif_adc_ctrl_configure(&adc_ctrl_, config_));
65 }
66 
67 TEST_F(ConfigTest, BadNumNormalPowerSamples) {
68  config_.num_normal_power_samples = 0;
69  EXPECT_DIF_BADARG(dif_adc_ctrl_configure(&adc_ctrl_, config_));
70 }
71 
72 TEST_F(ConfigTest, LowPowerModeSuccess) {
73  EXPECT_WRITE32(ADC_CTRL_ADC_EN_CTL_REG_OFFSET, 0);
74  EXPECT_WRITE32(ADC_CTRL_ADC_PD_CTL_REG_OFFSET,
75  {{ADC_CTRL_ADC_PD_CTL_WAKEUP_TIME_OFFSET,
76  config_.wake_up_time_aon_cycles},
77  {ADC_CTRL_ADC_PD_CTL_PWRUP_TIME_OFFSET,
78  config_.power_up_time_aon_cycles},
79  {ADC_CTRL_ADC_PD_CTL_LP_MODE_BIT, 1}});
80  EXPECT_WRITE32(ADC_CTRL_ADC_LP_SAMPLE_CTL_REG_OFFSET,
81  {{ADC_CTRL_ADC_LP_SAMPLE_CTL_LP_SAMPLE_CNT_OFFSET,
82  config_.num_low_power_samples}});
83  EXPECT_WRITE32(ADC_CTRL_ADC_SAMPLE_CTL_REG_OFFSET,
84  {{ADC_CTRL_ADC_SAMPLE_CTL_NP_SAMPLE_CNT_OFFSET,
85  config_.num_normal_power_samples}});
86  EXPECT_DIF_OK(dif_adc_ctrl_configure(&adc_ctrl_, config_));
87 }
88 
89 TEST_F(ConfigTest, NormalPowerModeSuccess) {
90  config_.mode = kDifAdcCtrlNormalPowerScanMode;
91  EXPECT_WRITE32(ADC_CTRL_ADC_EN_CTL_REG_OFFSET, 0);
92  EXPECT_WRITE32(ADC_CTRL_ADC_PD_CTL_REG_OFFSET,
93  {{ADC_CTRL_ADC_PD_CTL_PWRUP_TIME_OFFSET,
94  config_.power_up_time_aon_cycles},
95  {ADC_CTRL_ADC_PD_CTL_WAKEUP_TIME_OFFSET, 0x640}});
96  EXPECT_WRITE32(ADC_CTRL_ADC_LP_SAMPLE_CTL_REG_OFFSET,
97  ADC_CTRL_ADC_LP_SAMPLE_CTL_REG_RESVAL);
98  EXPECT_WRITE32(ADC_CTRL_ADC_SAMPLE_CTL_REG_OFFSET,
99  {{ADC_CTRL_ADC_SAMPLE_CTL_NP_SAMPLE_CNT_OFFSET,
100  config_.num_normal_power_samples}});
101  EXPECT_DIF_OK(dif_adc_ctrl_configure(&adc_ctrl_, config_));
102 }
103 
104 TEST_F(ConfigTest, OneshotModeSuccess) {
105  config_.mode = kDifAdcCtrlOneshotMode;
106  EXPECT_WRITE32(ADC_CTRL_ADC_EN_CTL_REG_OFFSET,
107  {{ADC_CTRL_ADC_EN_CTL_ONESHOT_MODE_BIT, true}});
108  EXPECT_WRITE32(ADC_CTRL_ADC_PD_CTL_REG_OFFSET,
109  {{ADC_CTRL_ADC_PD_CTL_PWRUP_TIME_OFFSET,
110  config_.power_up_time_aon_cycles},
111  {ADC_CTRL_ADC_PD_CTL_WAKEUP_TIME_OFFSET, 0x640}});
112  EXPECT_WRITE32(ADC_CTRL_ADC_LP_SAMPLE_CTL_REG_OFFSET,
113  ADC_CTRL_ADC_LP_SAMPLE_CTL_REG_RESVAL);
114  EXPECT_WRITE32(ADC_CTRL_ADC_SAMPLE_CTL_REG_OFFSET,
115  ADC_CTRL_ADC_SAMPLE_CTL_REG_RESVAL);
116  EXPECT_DIF_OK(dif_adc_ctrl_configure(&adc_ctrl_, config_));
117 }
118 
119 class FilterConfigTest : public AdcCtrlTest {};
120 
121 TEST_F(FilterConfigTest, NullHandle) {
122  EXPECT_DIF_BADARG(dif_adc_ctrl_configure_filter(
123  nullptr, kDifAdcCtrlChannel0, filter_config_, kDifToggleEnabled));
124 }
125 
126 TEST_F(FilterConfigTest, BadMinVoltage) {
127  filter_config_.min_voltage = 1024;
128  EXPECT_DIF_BADARG(dif_adc_ctrl_configure_filter(
129  &adc_ctrl_, kDifAdcCtrlChannel0, filter_config_, kDifToggleEnabled));
130 }
131 
132 TEST_F(FilterConfigTest, BadMaxVoltage) {
133  filter_config_.max_voltage = 1024;
134  EXPECT_DIF_BADARG(dif_adc_ctrl_configure_filter(
135  &adc_ctrl_, kDifAdcCtrlChannel0, filter_config_, kDifToggleEnabled));
136 }
137 
138 TEST_F(FilterConfigTest, BadChannel) {
139  EXPECT_DIF_BADARG(dif_adc_ctrl_configure_filter(
140  &adc_ctrl_,
141  static_cast<dif_adc_ctrl_channel_t>(ADC_CTRL_PARAM_NUM_ADC_CHANNEL),
142  filter_config_, kDifToggleEnabled));
143 }
144 
145 TEST_F(FilterConfigTest, BadFilter) {
146  filter_config_.filter =
147  static_cast<dif_adc_ctrl_filter_t>(ADC_CTRL_PARAM_NUM_ADC_FILTER);
148  EXPECT_DIF_BADARG(dif_adc_ctrl_configure_filter(
149  &adc_ctrl_, kDifAdcCtrlChannel0, filter_config_, kDifToggleEnabled));
150  EXPECT_DIF_BADARG(dif_adc_ctrl_configure_filter(
151  &adc_ctrl_, kDifAdcCtrlChannel1, filter_config_, kDifToggleEnabled));
152 }
153 
154 TEST_F(FilterConfigTest, Success) {
155  EXPECT_WRITE32(ADC_CTRL_ADC_CHN1_FILTER_CTL_2_REG_OFFSET,
156  {{ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MIN_V_2_OFFSET,
157  filter_config_.min_voltage},
158  {ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MAX_V_2_OFFSET,
159  filter_config_.max_voltage},
160  {ADC_CTRL_ADC_CHN1_FILTER_CTL_2_COND_2_BIT, false},
161  {ADC_CTRL_ADC_CHN1_FILTER_CTL_2_EN_2_BIT, true}});
162  EXPECT_READ32(ADC_CTRL_ADC_WAKEUP_CTL_REG_OFFSET, 0);
163  EXPECT_WRITE32(ADC_CTRL_ADC_WAKEUP_CTL_REG_OFFSET,
164  {{filter_config_.filter, true}});
165  EXPECT_READ32(ADC_CTRL_ADC_INTR_CTL_REG_OFFSET, 0);
166  EXPECT_WRITE32(ADC_CTRL_ADC_INTR_CTL_REG_OFFSET,
167  {{filter_config_.filter, true}});
168  EXPECT_DIF_OK(dif_adc_ctrl_configure_filter(
169  &adc_ctrl_, kDifAdcCtrlChannel1, filter_config_, kDifToggleEnabled));
170 
171  EXPECT_WRITE32(ADC_CTRL_ADC_CHN0_FILTER_CTL_6_REG_OFFSET,
172  {{ADC_CTRL_ADC_CHN0_FILTER_CTL_6_MIN_V_6_OFFSET,
173  filter_config_.min_voltage},
174  {ADC_CTRL_ADC_CHN0_FILTER_CTL_6_MAX_V_6_OFFSET,
175  filter_config_.max_voltage},
176  {ADC_CTRL_ADC_CHN0_FILTER_CTL_6_COND_6_BIT, false},
177  {ADC_CTRL_ADC_CHN0_FILTER_CTL_6_EN_6_BIT, true}});
178  EXPECT_READ32(ADC_CTRL_ADC_WAKEUP_CTL_REG_OFFSET, 0x4);
179  EXPECT_WRITE32(ADC_CTRL_ADC_WAKEUP_CTL_REG_OFFSET, 0x44);
180  EXPECT_READ32(ADC_CTRL_ADC_INTR_CTL_REG_OFFSET, 0x4);
181  EXPECT_WRITE32(ADC_CTRL_ADC_INTR_CTL_REG_OFFSET, 0x44);
182  filter_config_.filter = kDifAdcCtrlFilter6;
183  EXPECT_DIF_OK(dif_adc_ctrl_configure_filter(
184  &adc_ctrl_, kDifAdcCtrlChannel0, filter_config_, kDifToggleEnabled));
185 }
186 
187 class SetEnabledTest : public AdcCtrlTest {};
188 
189 TEST_F(SetEnabledTest, NullHandle) {
190  EXPECT_DIF_BADARG(dif_adc_ctrl_set_enabled(nullptr, kDifToggleEnabled));
191 }
192 
193 TEST_F(SetEnabledTest, BadArgs) {
194  EXPECT_DIF_BADARG(
195  dif_adc_ctrl_set_enabled(&adc_ctrl_, static_cast<dif_toggle_t>(2)));
196 }
197 
198 TEST_F(SetEnabledTest, Success) {
199  EXPECT_READ32(ADC_CTRL_ADC_EN_CTL_REG_OFFSET, 0);
200  EXPECT_WRITE32(ADC_CTRL_ADC_EN_CTL_REG_OFFSET,
201  {{ADC_CTRL_ADC_EN_CTL_ADC_ENABLE_BIT, true}});
202  EXPECT_DIF_OK(dif_adc_ctrl_set_enabled(&adc_ctrl_, kDifToggleEnabled));
203 
204  EXPECT_READ32(ADC_CTRL_ADC_EN_CTL_REG_OFFSET,
205  {{ADC_CTRL_ADC_EN_CTL_ONESHOT_MODE_BIT, true},
206  {ADC_CTRL_ADC_EN_CTL_ADC_ENABLE_BIT, true}});
207  EXPECT_WRITE32(ADC_CTRL_ADC_EN_CTL_REG_OFFSET,
208  {{ADC_CTRL_ADC_EN_CTL_ONESHOT_MODE_BIT, true},
209  {ADC_CTRL_ADC_EN_CTL_ADC_ENABLE_BIT, false}});
210  EXPECT_DIF_OK(dif_adc_ctrl_set_enabled(&adc_ctrl_, kDifToggleDisabled));
211 }
212 
213 class GetEnabledTest : public AdcCtrlTest {};
214 
215 TEST_F(GetEnabledTest, NullArgs) {
216  dif_toggle_t is_enabled;
217  EXPECT_DIF_BADARG(dif_adc_ctrl_get_enabled(nullptr, &is_enabled));
218  EXPECT_DIF_BADARG(dif_adc_ctrl_get_enabled(&adc_ctrl_, nullptr));
219 }
220 
221 TEST_F(GetEnabledTest, Success) {
222  dif_toggle_t is_enabled;
223 
224  EXPECT_READ32(ADC_CTRL_ADC_EN_CTL_REG_OFFSET,
225  {{ADC_CTRL_ADC_EN_CTL_ADC_ENABLE_BIT, true}});
226  EXPECT_DIF_OK(dif_adc_ctrl_get_enabled(&adc_ctrl_, &is_enabled));
227  EXPECT_EQ(is_enabled, kDifToggleEnabled);
228 
229  EXPECT_READ32(ADC_CTRL_ADC_EN_CTL_REG_OFFSET, 0);
230  EXPECT_DIF_OK(dif_adc_ctrl_get_enabled(&adc_ctrl_, &is_enabled));
231  EXPECT_EQ(is_enabled, kDifToggleDisabled);
232 }
233 
234 class SetFilterEnabledTest : public AdcCtrlTest {};
235 
236 TEST_F(SetFilterEnabledTest, NullHandle) {
237  EXPECT_DIF_BADARG(dif_adc_ctrl_filter_set_enabled(
238  nullptr, kDifAdcCtrlChannel0, kDifAdcCtrlFilter3, kDifToggleEnabled));
239 }
240 
241 TEST_F(SetFilterEnabledTest, BadChannel) {
242  EXPECT_DIF_BADARG(dif_adc_ctrl_filter_set_enabled(
243  &adc_ctrl_, static_cast<dif_adc_ctrl_channel_t>(2), kDifAdcCtrlFilter3,
244  kDifToggleEnabled));
245 }
246 
247 TEST_F(SetFilterEnabledTest, BadFilter) {
248  EXPECT_DIF_BADARG(dif_adc_ctrl_filter_set_enabled(
249  &adc_ctrl_, kDifAdcCtrlChannel0,
250  static_cast<dif_adc_ctrl_filter_t>(ADC_CTRL_PARAM_NUM_ADC_FILTER),
251  kDifToggleEnabled));
252  EXPECT_DIF_BADARG(dif_adc_ctrl_filter_set_enabled(
253  &adc_ctrl_, kDifAdcCtrlChannel1,
254  static_cast<dif_adc_ctrl_filter_t>(ADC_CTRL_PARAM_NUM_ADC_FILTER),
255  kDifToggleEnabled));
256 }
257 
258 TEST_F(SetFilterEnabledTest, BadEnabled) {
259  EXPECT_DIF_BADARG(dif_adc_ctrl_filter_set_enabled(
260  &adc_ctrl_, kDifAdcCtrlChannel0, kDifAdcCtrlFilter3,
261  static_cast<dif_toggle_t>(2)));
262 }
263 
264 TEST_F(SetFilterEnabledTest, Success) {
265  EXPECT_READ32(ADC_CTRL_ADC_CHN1_FILTER_CTL_2_REG_OFFSET,
266  {{ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MIN_V_2_OFFSET,
267  filter_config_.min_voltage},
268  {ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MAX_V_2_OFFSET,
269  filter_config_.max_voltage},
270  {ADC_CTRL_ADC_CHN1_FILTER_CTL_2_COND_2_BIT, true},
271  {ADC_CTRL_ADC_CHN1_FILTER_CTL_2_EN_2_BIT, false}});
272  EXPECT_WRITE32(ADC_CTRL_ADC_CHN1_FILTER_CTL_2_REG_OFFSET,
273  {{ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MIN_V_2_OFFSET,
274  filter_config_.min_voltage},
275  {ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MAX_V_2_OFFSET,
276  filter_config_.max_voltage},
277  {ADC_CTRL_ADC_CHN1_FILTER_CTL_2_COND_2_BIT, true},
278  {ADC_CTRL_ADC_CHN1_FILTER_CTL_2_EN_2_BIT, true}});
279  EXPECT_DIF_OK(dif_adc_ctrl_filter_set_enabled(
280  &adc_ctrl_, kDifAdcCtrlChannel1, kDifAdcCtrlFilter2, kDifToggleEnabled));
281 
282  EXPECT_READ32(ADC_CTRL_ADC_CHN0_FILTER_CTL_7_REG_OFFSET,
283  {{ADC_CTRL_ADC_CHN0_FILTER_CTL_7_MIN_V_7_OFFSET,
284  filter_config_.min_voltage},
285  {ADC_CTRL_ADC_CHN0_FILTER_CTL_7_MAX_V_7_OFFSET,
286  filter_config_.max_voltage},
287  {ADC_CTRL_ADC_CHN0_FILTER_CTL_7_COND_7_BIT, true},
288  {ADC_CTRL_ADC_CHN0_FILTER_CTL_7_EN_7_BIT, true}});
289  EXPECT_WRITE32(ADC_CTRL_ADC_CHN0_FILTER_CTL_7_REG_OFFSET,
290  {{ADC_CTRL_ADC_CHN0_FILTER_CTL_7_MIN_V_7_OFFSET,
291  filter_config_.min_voltage},
292  {ADC_CTRL_ADC_CHN0_FILTER_CTL_7_MAX_V_7_OFFSET,
293  filter_config_.max_voltage},
294  {ADC_CTRL_ADC_CHN0_FILTER_CTL_7_COND_7_BIT, true},
295  {ADC_CTRL_ADC_CHN0_FILTER_CTL_7_EN_7_BIT, false}});
296  EXPECT_DIF_OK(dif_adc_ctrl_filter_set_enabled(
297  &adc_ctrl_, kDifAdcCtrlChannel0, kDifAdcCtrlFilter7, kDifToggleDisabled));
298 }
299 
300 class GetFilterEnabledTest : public AdcCtrlTest {};
301 
302 TEST_F(GetFilterEnabledTest, NullArgs) {
303  dif_toggle_t is_enabled;
304  EXPECT_DIF_BADARG(dif_adc_ctrl_filter_get_enabled(
305  nullptr, kDifAdcCtrlChannel0, kDifAdcCtrlFilter3, &is_enabled));
306  EXPECT_DIF_BADARG(dif_adc_ctrl_filter_get_enabled(
307  &adc_ctrl_, kDifAdcCtrlChannel0, kDifAdcCtrlFilter3, nullptr));
308 }
309 
310 TEST_F(GetFilterEnabledTest, BadChannel) {
311  dif_toggle_t is_enabled;
312  EXPECT_DIF_BADARG(dif_adc_ctrl_filter_get_enabled(
313  &adc_ctrl_, static_cast<dif_adc_ctrl_channel_t>(2), kDifAdcCtrlFilter3,
314  &is_enabled));
315 }
316 
317 TEST_F(GetFilterEnabledTest, BadFilter) {
318  dif_toggle_t is_enabled;
319  EXPECT_DIF_BADARG(dif_adc_ctrl_filter_get_enabled(
320  &adc_ctrl_, kDifAdcCtrlChannel0,
321  static_cast<dif_adc_ctrl_filter_t>(ADC_CTRL_PARAM_NUM_ADC_FILTER),
322  &is_enabled));
323  EXPECT_DIF_BADARG(dif_adc_ctrl_filter_get_enabled(
324  &adc_ctrl_, kDifAdcCtrlChannel1,
325  static_cast<dif_adc_ctrl_filter_t>(ADC_CTRL_PARAM_NUM_ADC_FILTER),
326  &is_enabled));
327 }
328 
329 TEST_F(GetFilterEnabledTest, Success) {
330  dif_toggle_t is_enabled;
331 
332  EXPECT_READ32(ADC_CTRL_ADC_CHN0_FILTER_CTL_7_REG_OFFSET,
333  {{ADC_CTRL_ADC_CHN0_FILTER_CTL_7_EN_7_BIT, true}});
334  EXPECT_DIF_OK(dif_adc_ctrl_filter_get_enabled(
335  &adc_ctrl_, kDifAdcCtrlChannel0, kDifAdcCtrlFilter7, &is_enabled));
336  EXPECT_EQ(is_enabled, kDifToggleEnabled);
337 
338  EXPECT_READ32(ADC_CTRL_ADC_CHN1_FILTER_CTL_4_REG_OFFSET, 0);
339  EXPECT_DIF_OK(dif_adc_ctrl_filter_get_enabled(
340  &adc_ctrl_, kDifAdcCtrlChannel1, kDifAdcCtrlFilter4, &is_enabled));
341  EXPECT_EQ(is_enabled, kDifToggleDisabled);
342 }
343 
344 class GetTriggeredValueTest : public AdcCtrlTest {};
345 
346 TEST_F(GetTriggeredValueTest, NullArgs) {
347  uint16_t value;
348  EXPECT_DIF_BADARG(
349  dif_adc_ctrl_get_triggered_value(nullptr, kDifAdcCtrlChannel0, &value));
350  EXPECT_DIF_BADARG(dif_adc_ctrl_get_triggered_value(
351  &adc_ctrl_, kDifAdcCtrlChannel0, nullptr));
352 }
353 
354 TEST_F(GetTriggeredValueTest, BadChannel) {
355  uint16_t value;
356  EXPECT_DIF_BADARG(dif_adc_ctrl_get_triggered_value(
357  &adc_ctrl_,
358  static_cast<dif_adc_ctrl_channel_t>(ADC_CTRL_PARAM_NUM_ADC_CHANNEL),
359  &value));
360 }
361 
362 TEST_F(GetTriggeredValueTest, Success) {
363  uint16_t value;
364  EXPECT_READ32(ADC_CTRL_ADC_CHN_VAL_0_REG_OFFSET,
365  {{ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_INTR_0_OFFSET, 1023}});
366  EXPECT_DIF_OK(dif_adc_ctrl_get_triggered_value(&adc_ctrl_,
367  kDifAdcCtrlChannel0, &value));
368  EXPECT_EQ(value, 1023);
369 }
370 
371 class GetLatestValueTest : public AdcCtrlTest {};
372 
373 TEST_F(GetLatestValueTest, NullArgs) {
374  uint16_t value;
375  EXPECT_DIF_BADARG(
376  dif_adc_ctrl_get_latest_value(nullptr, kDifAdcCtrlChannel0, &value));
377  EXPECT_DIF_BADARG(
378  dif_adc_ctrl_get_latest_value(&adc_ctrl_, kDifAdcCtrlChannel0, nullptr));
379 }
380 
381 TEST_F(GetLatestValueTest, BadChannel) {
382  uint16_t value;
383  EXPECT_DIF_BADARG(dif_adc_ctrl_get_latest_value(
384  &adc_ctrl_,
385  static_cast<dif_adc_ctrl_channel_t>(ADC_CTRL_PARAM_NUM_ADC_CHANNEL),
386  &value));
387 }
388 
389 TEST_F(GetLatestValueTest, Success) {
390  uint16_t value;
391  EXPECT_READ32(ADC_CTRL_ADC_CHN_VAL_0_REG_OFFSET,
392  {{ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_0_OFFSET, 1023}});
393  EXPECT_DIF_OK(
394  dif_adc_ctrl_get_latest_value(&adc_ctrl_, kDifAdcCtrlChannel0, &value));
395  EXPECT_EQ(value, 1023);
396 }
397 
398 class ResetFsmTest : public AdcCtrlTest {};
399 
400 TEST_F(ResetFsmTest, NullHandle) {
401  EXPECT_DIF_BADARG(dif_adc_ctrl_reset(nullptr));
402 }
403 
404 TEST_F(ResetFsmTest, Success) {
405  EXPECT_WRITE32(ADC_CTRL_ADC_FSM_RST_REG_OFFSET, 1);
406  EXPECT_WRITE32(ADC_CTRL_ADC_FSM_RST_REG_OFFSET, 0);
407  EXPECT_DIF_OK(dif_adc_ctrl_reset(&adc_ctrl_));
408 }
409 
410 class FilterStatusTest : public AdcCtrlTest {};
411 
412 TEST_F(FilterStatusTest, NullArgs) {
413  uint32_t status;
414  EXPECT_DIF_BADARG(dif_adc_ctrl_get_filter_status(nullptr, &status));
415  EXPECT_DIF_BADARG(dif_adc_ctrl_get_filter_status(&adc_ctrl_, nullptr));
416 }
417 
418 TEST_F(FilterStatusTest, Success) {
419  uint32_t status;
420  EXPECT_READ32(ADC_CTRL_FILTER_STATUS_REG_OFFSET, 0x1FF);
421  EXPECT_DIF_OK(dif_adc_ctrl_get_filter_status(&adc_ctrl_, &status));
422  EXPECT_EQ(status, 0x1FF);
423 }
424 
425 class IrqGetCausesTest : public AdcCtrlTest {};
426 
427 TEST_F(IrqGetCausesTest, NullArgs) {
428  uint32_t causes;
429  EXPECT_DIF_BADARG(dif_adc_ctrl_irq_get_causes(nullptr, &causes));
430  EXPECT_DIF_BADARG(dif_adc_ctrl_irq_get_causes(&adc_ctrl_, nullptr));
431 }
432 
433 TEST_F(IrqGetCausesTest, Success) {
434  uint32_t causes;
435  EXPECT_READ32(ADC_CTRL_ADC_INTR_STATUS_REG_OFFSET, 0x1FF);
436  EXPECT_DIF_OK(dif_adc_ctrl_irq_get_causes(&adc_ctrl_, &causes));
437  EXPECT_EQ(causes, 0x1FF);
438 }
439 
440 class IrqClearCausesTest : public AdcCtrlTest {};
441 
442 TEST_F(IrqClearCausesTest, NullHandle) {
443  EXPECT_DIF_BADARG(
444  dif_adc_ctrl_irq_clear_causes(nullptr, kDifAdcCtrlIrqCauseOneshot));
445 }
446 
447 TEST_F(IrqClearCausesTest, BadCauses) {
448  EXPECT_DIF_BADARG(dif_adc_ctrl_irq_clear_causes(
449  &adc_ctrl_, 1U << (ADC_CTRL_PARAM_NUM_ADC_FILTER + 2)));
450 }
451 
452 TEST_F(IrqClearCausesTest, Success) {
453  EXPECT_WRITE32(ADC_CTRL_FILTER_STATUS_REG_OFFSET, 0x9);
454  EXPECT_WRITE32(ADC_CTRL_ADC_INTR_STATUS_REG_OFFSET, 0x9);
455  EXPECT_DIF_OK(dif_adc_ctrl_irq_clear_causes(
456  &adc_ctrl_, kDifAdcCtrlIrqCauseFilter0 | kDifAdcCtrlIrqCauseFilter3));
457 
458  EXPECT_WRITE32(ADC_CTRL_FILTER_STATUS_REG_OFFSET, 0x102);
459  EXPECT_WRITE32(ADC_CTRL_ADC_INTR_STATUS_REG_OFFSET, 0x102);
460  EXPECT_DIF_OK(dif_adc_ctrl_irq_clear_causes(
461  &adc_ctrl_, kDifAdcCtrlIrqCauseFilter1 | kDifAdcCtrlIrqCauseTrans));
462 
463  EXPECT_WRITE32(ADC_CTRL_FILTER_STATUS_REG_OFFSET, 0x001);
464  EXPECT_WRITE32(ADC_CTRL_ADC_INTR_STATUS_REG_OFFSET, 0x201);
465  EXPECT_DIF_OK(dif_adc_ctrl_irq_clear_causes(
466  &adc_ctrl_, kDifAdcCtrlIrqCauseFilter0 | kDifAdcCtrlIrqCauseOneshot));
467 }
468 
469 class FilterMatchWakeupSetEnabledTest : public AdcCtrlTest {};
470 
471 TEST_F(FilterMatchWakeupSetEnabledTest, NullHandle) {
472  EXPECT_DIF_BADARG(dif_adc_ctrl_filter_match_wakeup_set_enabled(
473  nullptr, kDifAdcCtrlFilter3, kDifToggleEnabled));
474 }
475 
476 TEST_F(FilterMatchWakeupSetEnabledTest, BadFilter) {
477  EXPECT_DIF_BADARG(dif_adc_ctrl_filter_match_wakeup_set_enabled(
478  &adc_ctrl_,
479  static_cast<dif_adc_ctrl_filter_t>(ADC_CTRL_PARAM_NUM_ADC_FILTER + 1),
480  kDifToggleEnabled));
481 }
482 
483 TEST_F(FilterMatchWakeupSetEnabledTest, BadEnabled) {
484  EXPECT_DIF_BADARG(dif_adc_ctrl_filter_match_wakeup_set_enabled(
485  &adc_ctrl_, kDifAdcCtrlFilter7, static_cast<dif_toggle_t>(2)));
486 }
487 
488 TEST_F(FilterMatchWakeupSetEnabledTest, Success) {
489  EXPECT_READ32(ADC_CTRL_ADC_WAKEUP_CTL_REG_OFFSET, 0xF);
490  EXPECT_WRITE32(ADC_CTRL_ADC_WAKEUP_CTL_REG_OFFSET, 0x8F);
491  EXPECT_DIF_OK(dif_adc_ctrl_filter_match_wakeup_set_enabled(
492  &adc_ctrl_, kDifAdcCtrlFilter7, kDifToggleEnabled));
493 
494  EXPECT_READ32(ADC_CTRL_ADC_WAKEUP_CTL_REG_OFFSET, 0x8F);
495  EXPECT_WRITE32(ADC_CTRL_ADC_WAKEUP_CTL_REG_OFFSET, 0xF);
496  EXPECT_DIF_OK(dif_adc_ctrl_filter_match_wakeup_set_enabled(
497  &adc_ctrl_, kDifAdcCtrlFilter7, kDifToggleDisabled));
498 
499  EXPECT_READ32(ADC_CTRL_ADC_WAKEUP_CTL_REG_OFFSET, 0xF);
500  EXPECT_WRITE32(ADC_CTRL_ADC_WAKEUP_CTL_REG_OFFSET, 0x10F);
501  EXPECT_DIF_OK(dif_adc_ctrl_filter_match_wakeup_set_enabled(
502  &adc_ctrl_, kDifAdcCtrlTrans, kDifToggleEnabled));
503 }
504 
505 class FilterMatchWakeupGetEnabledTest : public AdcCtrlTest {};
506 
507 TEST_F(FilterMatchWakeupGetEnabledTest, NullArgs) {
508  dif_toggle_t is_enabled;
509  EXPECT_DIF_BADARG(dif_adc_ctrl_filter_match_wakeup_get_enabled(
510  nullptr, kDifAdcCtrlFilter3, &is_enabled));
511  EXPECT_DIF_BADARG(dif_adc_ctrl_filter_match_wakeup_get_enabled(
512  &adc_ctrl_, kDifAdcCtrlFilter3, nullptr));
513 }
514 
515 TEST_F(FilterMatchWakeupGetEnabledTest, BadFilter) {
516  dif_toggle_t is_enabled;
517  EXPECT_DIF_BADARG(dif_adc_ctrl_filter_match_wakeup_get_enabled(
518  &adc_ctrl_,
519  static_cast<dif_adc_ctrl_filter_t>(ADC_CTRL_PARAM_NUM_ADC_FILTER + 1),
520  &is_enabled));
521 }
522 
523 TEST_F(FilterMatchWakeupGetEnabledTest, Success) {
524  dif_toggle_t is_enabled;
525 
526  EXPECT_READ32(ADC_CTRL_ADC_WAKEUP_CTL_REG_OFFSET, 0x88);
527  EXPECT_DIF_OK(dif_adc_ctrl_filter_match_wakeup_get_enabled(
528  &adc_ctrl_, kDifAdcCtrlFilter3, &is_enabled));
529  EXPECT_EQ(is_enabled, kDifToggleEnabled);
530 
531  EXPECT_READ32(ADC_CTRL_ADC_WAKEUP_CTL_REG_OFFSET, 0x88);
532  EXPECT_DIF_OK(dif_adc_ctrl_filter_match_wakeup_get_enabled(
533  &adc_ctrl_, kDifAdcCtrlFilter2, &is_enabled));
534  EXPECT_EQ(is_enabled, kDifToggleDisabled);
535 }
536 
537 class IrqCauseSetEnabledTest : public AdcCtrlTest {};
538 
539 TEST_F(IrqCauseSetEnabledTest, NullHandle) {
540  EXPECT_DIF_BADARG(dif_adc_ctrl_irq_cause_set_enabled(
541  nullptr, kDifAdcCtrlIrqCauseFilter2, kDifToggleEnabled));
542 }
543 
544 TEST_F(IrqCauseSetEnabledTest, BadCauses) {
545  EXPECT_DIF_BADARG(dif_adc_ctrl_irq_cause_set_enabled(
546  &adc_ctrl_, kDifAdcCtrlIrqCauseAll + 1, kDifToggleEnabled));
547 }
548 
549 TEST_F(IrqCauseSetEnabledTest, BadEnabled) {
550  EXPECT_DIF_BADARG(dif_adc_ctrl_irq_cause_set_enabled(
551  &adc_ctrl_, kDifAdcCtrlIrqCauseAll, static_cast<dif_toggle_t>(2)));
552 }
553 
554 TEST_F(IrqCauseSetEnabledTest, Success) {
555  EXPECT_READ32(ADC_CTRL_ADC_INTR_CTL_REG_OFFSET, 0x33);
556  EXPECT_WRITE32(ADC_CTRL_ADC_INTR_CTL_REG_OFFSET, 0x3F);
557  EXPECT_DIF_OK(dif_adc_ctrl_irq_cause_set_enabled(
558  &adc_ctrl_, kDifAdcCtrlIrqCauseFilter2 | kDifAdcCtrlIrqCauseFilter3,
559  kDifToggleEnabled));
560 
561  EXPECT_READ32(ADC_CTRL_ADC_INTR_CTL_REG_OFFSET, 0x3F);
562  EXPECT_WRITE32(ADC_CTRL_ADC_INTR_CTL_REG_OFFSET, 0x33);
563  EXPECT_DIF_OK(dif_adc_ctrl_irq_cause_set_enabled(
564  &adc_ctrl_, kDifAdcCtrlIrqCauseFilter2 | kDifAdcCtrlIrqCauseFilter3,
565  kDifToggleDisabled));
566 }
567 
568 class IrqCauseGetEnabledTest : public AdcCtrlTest {};
569 
570 TEST_F(IrqCauseGetEnabledTest, NullArgs) {
571  uint32_t enabled_causes;
572  EXPECT_DIF_BADARG(
573  dif_adc_ctrl_irq_cause_get_enabled(nullptr, &enabled_causes));
574  EXPECT_DIF_BADARG(dif_adc_ctrl_irq_cause_get_enabled(&adc_ctrl_, nullptr));
575 }
576 
577 TEST_F(IrqCauseGetEnabledTest, Success) {
578  uint32_t enabled_causes;
579  EXPECT_READ32(ADC_CTRL_ADC_INTR_CTL_REG_OFFSET, 0x1AA);
580  EXPECT_DIF_OK(
581  dif_adc_ctrl_irq_cause_get_enabled(&adc_ctrl_, &enabled_causes));
582  EXPECT_EQ(enabled_causes, 0x1AA);
583 }
584 
585 } // namespace
586 } // namespace dif_adc_ctrl_unittest
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