67 if (ac_range_check == NULL) {
74 alert_idx = AC_RANGE_CHECK_ALERT_TEST_RECOV_CTRL_UPDATE_ERR_BIT;
77 alert_idx = AC_RANGE_CHECK_ALERT_TEST_FATAL_FAULT_BIT;
83 uint32_t alert_test_reg = bitfield_bit32_write(0, alert_idx,
true);
86 (ptrdiff_t)AC_RANGE_CHECK_ALERT_TEST_REG_OFFSET,
172 dif_ac_range_check_irq_t irq,
175 if (ac_range_check == NULL || is_pending == NULL) {
180 if (!ac_range_check_get_irq_bit_index(irq, &index)) {
184 uint32_t intr_state_reg = mmio_region_read32(
186 (ptrdiff_t)AC_RANGE_CHECK_INTR_STATE_REG_OFFSET);
189 *is_pending = bitfield_bit32_read(intr_state_reg, index);
216 dif_ac_range_check_irq_t irq) {
218 if (ac_range_check == NULL) {
223 if (!ac_range_check_get_irq_bit_index(irq, &index)) {
228 uint32_t intr_state_reg = bitfield_bit32_write(0, index,
true);
231 (ptrdiff_t)AC_RANGE_CHECK_INTR_STATE_REG_OFFSET,
241 dif_ac_range_check_irq_t irq,
244 if (ac_range_check == NULL) {
249 if (!ac_range_check_get_irq_bit_index(irq, &index)) {
253 uint32_t intr_test_reg = bitfield_bit32_write(0, index, val);
256 (ptrdiff_t)AC_RANGE_CHECK_INTR_TEST_REG_OFFSET,
266 dif_ac_range_check_irq_t irq,
269 if (ac_range_check == NULL || state == NULL) {
274 if (!ac_range_check_get_irq_bit_index(irq, &index)) {
278 uint32_t intr_enable_reg = mmio_region_read32(
280 (ptrdiff_t)AC_RANGE_CHECK_INTR_ENABLE_REG_OFFSET);
283 bool is_enabled = bitfield_bit32_read(intr_enable_reg, index);
284 *state = is_enabled ?
293 dif_ac_range_check_irq_t irq,
296 if (ac_range_check == NULL) {
301 if (!ac_range_check_get_irq_bit_index(irq, &index)) {
305 uint32_t intr_enable_reg = mmio_region_read32(
307 (ptrdiff_t)AC_RANGE_CHECK_INTR_ENABLE_REG_OFFSET);
311 intr_enable_reg = bitfield_bit32_write(intr_enable_reg, index, enable_bit);
314 (ptrdiff_t)AC_RANGE_CHECK_INTR_ENABLE_REG_OFFSET,