cheriot_mem_sys.h

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// Copyright lowRISC contributors (OpenTitan project).
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Device table API auto-generated by `dtgen`
 
#ifndef OPENTITAN_DT_CHERIOT_MEM_SYS_H_
#define OPENTITAN_DT_CHERIOT_MEM_SYS_H_
 
#ifdef __cplusplus
extern "C" {
#endif  // __cplusplus
 
/**
 * @file
 * @brief Device Tables (DT) for IP cheriot_mem_sys and top earlgrey.
 *
 * This file contains the type definitions and global functions of the cheriot_mem_sys.
 */
 
#include "hw/top/dt/api.h"
#include <stdint.h>
 
 
 
/**
 * List of instances.
 */
typedef enum dt_cheriot_mem_sys {
  kDtCheriotMemSysFirst = 0, /**< First instance */
  kDtCheriotMemSys = 0, /**< cheriot_mem_sys */
} dt_cheriot_mem_sys_t;
 
enum {
  kDtCheriotMemSysCount = 1, /**< Number of instances */
};
 
 
/**
 * List of register blocks.
 *
 * Register blocks are guaranteed to start at 0 and to be consecutively numbered.
 */
typedef enum dt_cheriot_mem_sys_reg_block {
  kDtCheriotMemSysRegBlockRegs = 0, /**<  */
} dt_cheriot_mem_sys_reg_block_t;
 
enum {
  kDtCheriotMemSysRegBlockCount = 1, /**< Number of register blocks */
};
 
 
/** Primary register block (associated with the "primary" set of registers that control the IP). */
static const dt_cheriot_mem_sys_reg_block_t kDtCheriotMemSysRegBlockPrimary = kDtCheriotMemSysRegBlockRegs;
 
/**
 * List of memories.
 *
 * Memories are guaranteed to start at 0 and to be consecutively numbered.
 */
typedef enum dt_cheriot_mem_sys_memory {
  kDtCheriotMemSysMemoryRevbm = 0, /**<  */
} dt_cheriot_mem_sys_memory_t;
 
enum {
  kDtCheriotMemSysMemoryCount = 1, /**< Number of memories */
};
 
 
/**
 * List of IRQs.
 *
 * IRQs are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_cheriot_mem_sys_irq {
  kDtCheriotMemSysIrqTbreDone = 0, /**< Raised when the revocation engine has resolved every capability of a sweep. */
} dt_cheriot_mem_sys_irq_t;
 
enum {
  kDtCheriotMemSysIrqCount = 1, /**< Number of IRQs */
};
 
 
/**
 * List of Alerts.
 *
 * Alerts are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_cheriot_mem_sys_alert {
  kDtCheriotMemSysAlertFatalFault = 0, /**< This fatal alert is triggered when an integrity fault is detected, when the meta
  SRAM path returns a device error, when the revocation engine reports a fault, when a
  capability store to the NVM is partial, or when a request breaks the core's capability
  store sequence. */
} dt_cheriot_mem_sys_alert_t;
 
enum {
  kDtCheriotMemSysAlertCount = 1, /**< Number of Alerts */
};
 
 
/**
 * List of clock ports.
 *
 * Clock ports are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_cheriot_mem_sys_clock {
  kDtCheriotMemSysClockClk = 0, /**< Clock port clk_i */
} dt_cheriot_mem_sys_clock_t;
 
enum {
  kDtCheriotMemSysClockCount = 1, /**< Number of clock ports */
};
 
 
/**
 * List of reset ports.
 *
 * Reset ports are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_cheriot_mem_sys_reset {
  kDtCheriotMemSysResetRst = 0, /**< Reset port rst_ni */
} dt_cheriot_mem_sys_reset_t;
 
enum {
  kDtCheriotMemSysResetCount = 1, /**< Number of reset ports */
};
 
 
/**
 * List of supported hardware features.
 */
#define OPENTITAN_CHERIOT_MEM_SYS_HAS_TAG_SPLIT 1
#define OPENTITAN_CHERIOT_MEM_SYS_HAS_TAG_READ 1
#define OPENTITAN_CHERIOT_MEM_SYS_HAS_TAG_WRITE_RMW 1
#define OPENTITAN_CHERIOT_MEM_SYS_HAS_TAG_CLEAR_ON_DATA_WRITE 1
#define OPENTITAN_CHERIOT_MEM_SYS_HAS_REVOCATION_BITMAP 1
#define OPENTITAN_CHERIOT_MEM_SYS_HAS_ACCESS_CHECK 1
#define OPENTITAN_CHERIOT_MEM_SYS_HAS_MODE_GATING 1
#define OPENTITAN_CHERIOT_MEM_SYS_HAS_TBRE_SWEEP 1
#define OPENTITAN_CHERIOT_MEM_SYS_HAS_TBRE_CORE_WRITE_SNOOP 1
#define OPENTITAN_CHERIOT_MEM_SYS_HAS_TBRE_STATUS 1
 
 
 
/**
 * Get the cheriot_mem_sys instance from an instance ID
 *
 * For example, `dt_uart_from_instance_id(kDtInstanceIdUart3) == kDtUart3`.
 *
 * @param inst_id Instance ID.
 * @return A cheriot_mem_sys instance.
 *
 * **Note:** This function only makes sense if the instance ID has device type cheriot_mem_sys,
 * otherwise the returned value is unspecified.
 */
dt_cheriot_mem_sys_t dt_cheriot_mem_sys_from_instance_id(dt_instance_id_t inst_id);
 
/**
 * Get the instance ID of an instance.
 *
 * @param dt Instance of cheriot_mem_sys.
 * @return The instance ID of that instance.
 */
dt_instance_id_t dt_cheriot_mem_sys_instance_id(dt_cheriot_mem_sys_t dt);
 
/**
 * Get the register base address of an instance.
 *
 * @param dt Instance of cheriot_mem_sys.
 * @param reg_block The register block requested.
 * @return The register base address of the requested block.
 */
uint32_t dt_cheriot_mem_sys_reg_block(
    dt_cheriot_mem_sys_t dt,
    dt_cheriot_mem_sys_reg_block_t reg_block);
 
/**
 * Get the primary register base address of an instance.
 *
 * This is just a convenience function, equivalent to
 * `dt_cheriot_mem_sys_reg_block(dt, kDtCheriotMemSysRegBlockRegs)`
 *
 * @param dt Instance of cheriot_mem_sys.
 * @return The register base address of the primary register block.
 */
static inline uint32_t dt_cheriot_mem_sys_primary_reg_block(
    dt_cheriot_mem_sys_t dt) {
  return dt_cheriot_mem_sys_reg_block(dt, kDtCheriotMemSysRegBlockRegs);
}
 
/**
 * Get the base address of a memory.
 *
 * @param dt Instance of cheriot_mem_sys.
 * @param mem The memory requested.
 * @return The base address of the requested memory.
 */
uint32_t dt_cheriot_mem_sys_memory_base(
    dt_cheriot_mem_sys_t dt,
    dt_cheriot_mem_sys_memory_t mem);
 
/**
 * Get the size of a memory.
 *
 * @param dt Instance of cheriot_mem_sys.
 * @param mem The memory requested.
 * @return The size of the requested memory.
 */
uint32_t dt_cheriot_mem_sys_memory_size(
    dt_cheriot_mem_sys_t dt,
    dt_cheriot_mem_sys_memory_t mem);
 
/**
 * Get the PLIC ID of a cheriot_mem_sys IRQ for a given instance.
 *
 * If the instance is not connected to the PLIC, this function
 * will return `kDtPlicIrqIdNone`.
 *
 * @param dt Instance of cheriot_mem_sys.
 * @param irq A cheriot_mem_sys IRQ.
 * @return The PLIC ID of the IRQ of this instance.
 */
dt_plic_irq_id_t dt_cheriot_mem_sys_irq_to_plic_id(
    dt_cheriot_mem_sys_t dt,
    dt_cheriot_mem_sys_irq_t irq);
 
/**
 * Convert a global IRQ ID to a local cheriot_mem_sys IRQ type.
 *
 * @param dt Instance of cheriot_mem_sys.
 * @param irq A PLIC ID that belongs to this instance.
 * @return The cheriot_mem_sys IRQ, or `kDtCheriotMemSysIrqCount`.
 *
 * **Note:** This function assumes that the PLIC ID belongs to the instance
 * of cheriot_mem_sys passed in parameter. In other words, it must be the case that
 * `dt_cheriot_mem_sys_instance_id(dt) == dt_plic_id_to_instance_id(irq)`. Otherwise, this function
 * will return `kDtCheriotMemSysIrqCount`.
 */
dt_cheriot_mem_sys_irq_t dt_cheriot_mem_sys_irq_from_plic_id(
    dt_cheriot_mem_sys_t dt,
    dt_plic_irq_id_t irq);
 
 
/**
 * Get the alert ID of a cheriot_mem_sys alert for a given instance.
 *
 * **Note:** This function only makes sense if the instance is connected to the Alert Handler. For any
 * instances where the instance is not connected, the return value is unspecified.
 *
 * @param dt Instance of cheriot_mem_sys.
 * @param alert A cheriot_mem_sys alert.
 * @return The Alert Handler alert ID of the alert of this instance.
 */
dt_alert_id_t dt_cheriot_mem_sys_alert_to_alert_id(
    dt_cheriot_mem_sys_t dt,
    dt_cheriot_mem_sys_alert_t alert);
 
/**
 * Convert a global alert ID to a local cheriot_mem_sys alert type.
 *
 * @param dt Instance of cheriot_mem_sys.
 * @param alert A global alert ID that belongs to this instance.
 * @return The cheriot_mem_sys alert, or `kDtCheriotMemSysAlertCount`.
 *
 * **Note:** This function assumes that the global alert ID belongs to the
 * instance of cheriot_mem_sys passed in parameter. In other words, it must be the case
 * that `dt_cheriot_mem_sys_instance_id(dt) == dt_alert_id_to_instance_id(alert)`. Otherwise,
 * this function will return `kDtCheriotMemSysAlertCount`.
 */
dt_cheriot_mem_sys_alert_t dt_cheriot_mem_sys_alert_from_alert_id(
    dt_cheriot_mem_sys_t dt,
    dt_alert_id_t alert);
 
 
 
/**
 * Get the clock signal connected to a clock port of an instance.
 *
 * @param dt Instance of cheriot_mem_sys.
 * @param clk Clock port.
 * @return Clock signal.
 */
dt_clock_t dt_cheriot_mem_sys_clock(
    dt_cheriot_mem_sys_t dt,
    dt_cheriot_mem_sys_clock_t clk);
 
/**
 * Get the reset signal connected to a reset port of an instance.
 *
 * @param dt Instance of cheriot_mem_sys.
 * @param rst Reset port.
 * @return Reset signal.
 */
dt_reset_t dt_cheriot_mem_sys_reset(
    dt_cheriot_mem_sys_t dt,
    dt_cheriot_mem_sys_reset_t rst);
 
 
 
#ifdef __cplusplus
}  // extern "C"
#endif  // __cplusplus
 
#endif  // OPENTITAN_DT_CHERIOT_MEM_SYS_H_