ac_range_check_regs.h

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/**
 * @file
 * @brief Generated register defines for ac_range_check
 */
 
// Copyright information found in source file:
// Copyright lowRISC contributors (OpenTitan project).
 
// Licensing information found in source file:
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
 
#ifndef _AC_RANGE_CHECK_REG_DEFS_
#define _AC_RANGE_CHECK_REG_DEFS_
 
#ifdef __cplusplus
extern "C" {
#endif
// Number of range registers
#define AC_RANGE_CHECK_PARAM_NUM_RANGES 32
 
// Width of the deny counter
#define AC_RANGE_CHECK_PARAM_DENY_COUNT_WIDTH 8
 
// Number of alerts
#define AC_RANGE_CHECK_PARAM_NUM_ALERTS 2
 
// Register width
#define AC_RANGE_CHECK_PARAM_REG_WIDTH 32
 
// Common Interrupt Offsets
#define AC_RANGE_CHECK_INTR_COMMON_DENY_CNT_REACHED_BIT 0
 
// Interrupt State Register
#define AC_RANGE_CHECK_INTR_STATE_REG_OFFSET 0x0
#define AC_RANGE_CHECK_INTR_STATE_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_INTR_STATE_DENY_CNT_REACHED_BIT 0
 
// Interrupt Enable Register
#define AC_RANGE_CHECK_INTR_ENABLE_REG_OFFSET 0x4
#define AC_RANGE_CHECK_INTR_ENABLE_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_INTR_ENABLE_DENY_CNT_REACHED_BIT 0
 
// Interrupt Test Register
#define AC_RANGE_CHECK_INTR_TEST_REG_OFFSET 0x8
#define AC_RANGE_CHECK_INTR_TEST_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_INTR_TEST_DENY_CNT_REACHED_BIT 0
 
// Alert Test Register
#define AC_RANGE_CHECK_ALERT_TEST_REG_OFFSET 0xc
#define AC_RANGE_CHECK_ALERT_TEST_REG_RESVAL 0x80000000u
#define AC_RANGE_CHECK_ALERT_TEST_RECOV_CTRL_UPDATE_ERR_BIT 0
#define AC_RANGE_CHECK_ALERT_TEST_FATAL_FAULT_BIT 1
#define AC_RANGE_CHECK_ALERT_TEST_REGWEN_BIT 31
 
// Status of hardware alerts.
#define AC_RANGE_CHECK_ALERT_STATUS_REG_OFFSET 0x10
#define AC_RANGE_CHECK_ALERT_STATUS_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_ALERT_STATUS_SHADOWED_UPDATE_ERR_BIT 0
#define AC_RANGE_CHECK_ALERT_STATUS_SHADOWED_STORAGE_ERR_BIT 1
#define AC_RANGE_CHECK_ALERT_STATUS_REG_INTG_ERR_BIT 2
#define AC_RANGE_CHECK_ALERT_STATUS_COUNTER_ERR_BIT 3
 
 
#define AC_RANGE_CHECK_LOG_CONFIG_REG_OFFSET 0x14
#define AC_RANGE_CHECK_LOG_CONFIG_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_LOG_CONFIG_LOG_ENABLE_BIT 0
#define AC_RANGE_CHECK_LOG_CONFIG_LOG_CLEAR_BIT 1
#define AC_RANGE_CHECK_LOG_CONFIG_DENY_CNT_THRESHOLD_MASK 0xffu
#define AC_RANGE_CHECK_LOG_CONFIG_DENY_CNT_THRESHOLD_OFFSET 2
#define AC_RANGE_CHECK_LOG_CONFIG_DENY_CNT_THRESHOLD_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_LOG_CONFIG_DENY_CNT_THRESHOLD_MASK, .index = AC_RANGE_CHECK_LOG_CONFIG_DENY_CNT_THRESHOLD_OFFSET })
 
// The LOG_STATUS register stores the number of denied accesses and gives
// more detailed diagnostics to the first denied request.
#define AC_RANGE_CHECK_LOG_STATUS_REG_OFFSET 0x18
#define AC_RANGE_CHECK_LOG_STATUS_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_LOG_STATUS_DENY_CNT_MASK 0xffu
#define AC_RANGE_CHECK_LOG_STATUS_DENY_CNT_OFFSET 0
#define AC_RANGE_CHECK_LOG_STATUS_DENY_CNT_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_LOG_STATUS_DENY_CNT_MASK, .index = AC_RANGE_CHECK_LOG_STATUS_DENY_CNT_OFFSET })
#define AC_RANGE_CHECK_LOG_STATUS_DENIED_READ_ACCESS_BIT 8
#define AC_RANGE_CHECK_LOG_STATUS_DENIED_WRITE_ACCESS_BIT 9
#define AC_RANGE_CHECK_LOG_STATUS_DENIED_EXECUTE_ACCESS_BIT 10
#define AC_RANGE_CHECK_LOG_STATUS_DENIED_NO_MATCH_BIT 11
#define AC_RANGE_CHECK_LOG_STATUS_DENIED_RACL_READ_BIT 12
#define AC_RANGE_CHECK_LOG_STATUS_DENIED_RACL_WRITE_BIT 13
#define AC_RANGE_CHECK_LOG_STATUS_DENIED_SOURCE_ROLE_MASK 0xfu
#define AC_RANGE_CHECK_LOG_STATUS_DENIED_SOURCE_ROLE_OFFSET 14
#define AC_RANGE_CHECK_LOG_STATUS_DENIED_SOURCE_ROLE_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_LOG_STATUS_DENIED_SOURCE_ROLE_MASK, .index = AC_RANGE_CHECK_LOG_STATUS_DENIED_SOURCE_ROLE_OFFSET })
#define AC_RANGE_CHECK_LOG_STATUS_DENIED_CTN_UID_MASK 0x1fu
#define AC_RANGE_CHECK_LOG_STATUS_DENIED_CTN_UID_OFFSET 18
#define AC_RANGE_CHECK_LOG_STATUS_DENIED_CTN_UID_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_LOG_STATUS_DENIED_CTN_UID_MASK, .index = AC_RANGE_CHECK_LOG_STATUS_DENIED_CTN_UID_OFFSET })
#define AC_RANGE_CHECK_LOG_STATUS_DENY_RANGE_INDEX_MASK 0x1fu
#define AC_RANGE_CHECK_LOG_STATUS_DENY_RANGE_INDEX_OFFSET 23
#define AC_RANGE_CHECK_LOG_STATUS_DENY_RANGE_INDEX_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_LOG_STATUS_DENY_RANGE_INDEX_MASK, .index = AC_RANGE_CHECK_LOG_STATUS_DENY_RANGE_INDEX_OFFSET })
 
// First denied request address (if logging is enabled) gets written into
// that register.
#define AC_RANGE_CHECK_LOG_ADDRESS_REG_OFFSET 0x1c
#define AC_RANGE_CHECK_LOG_ADDRESS_REG_RESVAL 0x0u
 
// This register exists per range and provides a regwen signal for the
// RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and
// RANGE_RACL_POLICY_SHADOWED_x register.
#define AC_RANGE_CHECK_RANGE_REGWEN_REGWEN_FIELD_WIDTH 4
#define AC_RANGE_CHECK_RANGE_REGWEN_MULTIREG_COUNT 32
 
// This register exists per range and provides a regwen signal for the
// RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and
// RANGE_RACL_POLICY_SHADOWED_x register.
#define AC_RANGE_CHECK_RANGE_REGWEN_0_REG_OFFSET 0x20
#define AC_RANGE_CHECK_RANGE_REGWEN_0_REG_RESVAL 0x6u
#define AC_RANGE_CHECK_RANGE_REGWEN_0_REGWEN_0_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_REGWEN_0_REGWEN_0_OFFSET 0
#define AC_RANGE_CHECK_RANGE_REGWEN_0_REGWEN_0_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_REGWEN_0_REGWEN_0_MASK, .index = AC_RANGE_CHECK_RANGE_REGWEN_0_REGWEN_0_OFFSET })
 
// This register exists per range and provides a regwen signal for the
// RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and
// RANGE_RACL_POLICY_SHADOWED_x register.
#define AC_RANGE_CHECK_RANGE_REGWEN_1_REG_OFFSET 0x24
#define AC_RANGE_CHECK_RANGE_REGWEN_1_REG_RESVAL 0x6u
#define AC_RANGE_CHECK_RANGE_REGWEN_1_REGWEN_1_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_REGWEN_1_REGWEN_1_OFFSET 0
#define AC_RANGE_CHECK_RANGE_REGWEN_1_REGWEN_1_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_REGWEN_1_REGWEN_1_MASK, .index = AC_RANGE_CHECK_RANGE_REGWEN_1_REGWEN_1_OFFSET })
 
// This register exists per range and provides a regwen signal for the
// RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and
// RANGE_RACL_POLICY_SHADOWED_x register.
#define AC_RANGE_CHECK_RANGE_REGWEN_2_REG_OFFSET 0x28
#define AC_RANGE_CHECK_RANGE_REGWEN_2_REG_RESVAL 0x6u
#define AC_RANGE_CHECK_RANGE_REGWEN_2_REGWEN_2_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_REGWEN_2_REGWEN_2_OFFSET 0
#define AC_RANGE_CHECK_RANGE_REGWEN_2_REGWEN_2_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_REGWEN_2_REGWEN_2_MASK, .index = AC_RANGE_CHECK_RANGE_REGWEN_2_REGWEN_2_OFFSET })
 
// This register exists per range and provides a regwen signal for the
// RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and
// RANGE_RACL_POLICY_SHADOWED_x register.
#define AC_RANGE_CHECK_RANGE_REGWEN_3_REG_OFFSET 0x2c
#define AC_RANGE_CHECK_RANGE_REGWEN_3_REG_RESVAL 0x6u
#define AC_RANGE_CHECK_RANGE_REGWEN_3_REGWEN_3_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_REGWEN_3_REGWEN_3_OFFSET 0
#define AC_RANGE_CHECK_RANGE_REGWEN_3_REGWEN_3_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_REGWEN_3_REGWEN_3_MASK, .index = AC_RANGE_CHECK_RANGE_REGWEN_3_REGWEN_3_OFFSET })
 
// This register exists per range and provides a regwen signal for the
// RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and
// RANGE_RACL_POLICY_SHADOWED_x register.
#define AC_RANGE_CHECK_RANGE_REGWEN_4_REG_OFFSET 0x30
#define AC_RANGE_CHECK_RANGE_REGWEN_4_REG_RESVAL 0x6u
#define AC_RANGE_CHECK_RANGE_REGWEN_4_REGWEN_4_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_REGWEN_4_REGWEN_4_OFFSET 0
#define AC_RANGE_CHECK_RANGE_REGWEN_4_REGWEN_4_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_REGWEN_4_REGWEN_4_MASK, .index = AC_RANGE_CHECK_RANGE_REGWEN_4_REGWEN_4_OFFSET })
 
// This register exists per range and provides a regwen signal for the
// RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and
// RANGE_RACL_POLICY_SHADOWED_x register.
#define AC_RANGE_CHECK_RANGE_REGWEN_5_REG_OFFSET 0x34
#define AC_RANGE_CHECK_RANGE_REGWEN_5_REG_RESVAL 0x6u
#define AC_RANGE_CHECK_RANGE_REGWEN_5_REGWEN_5_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_REGWEN_5_REGWEN_5_OFFSET 0
#define AC_RANGE_CHECK_RANGE_REGWEN_5_REGWEN_5_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_REGWEN_5_REGWEN_5_MASK, .index = AC_RANGE_CHECK_RANGE_REGWEN_5_REGWEN_5_OFFSET })
 
// This register exists per range and provides a regwen signal for the
// RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and
// RANGE_RACL_POLICY_SHADOWED_x register.
#define AC_RANGE_CHECK_RANGE_REGWEN_6_REG_OFFSET 0x38
#define AC_RANGE_CHECK_RANGE_REGWEN_6_REG_RESVAL 0x6u
#define AC_RANGE_CHECK_RANGE_REGWEN_6_REGWEN_6_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_REGWEN_6_REGWEN_6_OFFSET 0
#define AC_RANGE_CHECK_RANGE_REGWEN_6_REGWEN_6_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_REGWEN_6_REGWEN_6_MASK, .index = AC_RANGE_CHECK_RANGE_REGWEN_6_REGWEN_6_OFFSET })
 
// This register exists per range and provides a regwen signal for the
// RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and
// RANGE_RACL_POLICY_SHADOWED_x register.
#define AC_RANGE_CHECK_RANGE_REGWEN_7_REG_OFFSET 0x3c
#define AC_RANGE_CHECK_RANGE_REGWEN_7_REG_RESVAL 0x6u
#define AC_RANGE_CHECK_RANGE_REGWEN_7_REGWEN_7_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_REGWEN_7_REGWEN_7_OFFSET 0
#define AC_RANGE_CHECK_RANGE_REGWEN_7_REGWEN_7_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_REGWEN_7_REGWEN_7_MASK, .index = AC_RANGE_CHECK_RANGE_REGWEN_7_REGWEN_7_OFFSET })
 
// This register exists per range and provides a regwen signal for the
// RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and
// RANGE_RACL_POLICY_SHADOWED_x register.
#define AC_RANGE_CHECK_RANGE_REGWEN_8_REG_OFFSET 0x40
#define AC_RANGE_CHECK_RANGE_REGWEN_8_REG_RESVAL 0x6u
#define AC_RANGE_CHECK_RANGE_REGWEN_8_REGWEN_8_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_REGWEN_8_REGWEN_8_OFFSET 0
#define AC_RANGE_CHECK_RANGE_REGWEN_8_REGWEN_8_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_REGWEN_8_REGWEN_8_MASK, .index = AC_RANGE_CHECK_RANGE_REGWEN_8_REGWEN_8_OFFSET })
 
// This register exists per range and provides a regwen signal for the
// RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and
// RANGE_RACL_POLICY_SHADOWED_x register.
#define AC_RANGE_CHECK_RANGE_REGWEN_9_REG_OFFSET 0x44
#define AC_RANGE_CHECK_RANGE_REGWEN_9_REG_RESVAL 0x6u
#define AC_RANGE_CHECK_RANGE_REGWEN_9_REGWEN_9_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_REGWEN_9_REGWEN_9_OFFSET 0
#define AC_RANGE_CHECK_RANGE_REGWEN_9_REGWEN_9_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_REGWEN_9_REGWEN_9_MASK, .index = AC_RANGE_CHECK_RANGE_REGWEN_9_REGWEN_9_OFFSET })
 
// This register exists per range and provides a regwen signal for the
// RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and
// RANGE_RACL_POLICY_SHADOWED_x register.
#define AC_RANGE_CHECK_RANGE_REGWEN_10_REG_OFFSET 0x48
#define AC_RANGE_CHECK_RANGE_REGWEN_10_REG_RESVAL 0x6u
#define AC_RANGE_CHECK_RANGE_REGWEN_10_REGWEN_10_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_REGWEN_10_REGWEN_10_OFFSET 0
#define AC_RANGE_CHECK_RANGE_REGWEN_10_REGWEN_10_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_REGWEN_10_REGWEN_10_MASK, .index = AC_RANGE_CHECK_RANGE_REGWEN_10_REGWEN_10_OFFSET })
 
// This register exists per range and provides a regwen signal for the
// RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and
// RANGE_RACL_POLICY_SHADOWED_x register.
#define AC_RANGE_CHECK_RANGE_REGWEN_11_REG_OFFSET 0x4c
#define AC_RANGE_CHECK_RANGE_REGWEN_11_REG_RESVAL 0x6u
#define AC_RANGE_CHECK_RANGE_REGWEN_11_REGWEN_11_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_REGWEN_11_REGWEN_11_OFFSET 0
#define AC_RANGE_CHECK_RANGE_REGWEN_11_REGWEN_11_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_REGWEN_11_REGWEN_11_MASK, .index = AC_RANGE_CHECK_RANGE_REGWEN_11_REGWEN_11_OFFSET })
 
// This register exists per range and provides a regwen signal for the
// RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and
// RANGE_RACL_POLICY_SHADOWED_x register.
#define AC_RANGE_CHECK_RANGE_REGWEN_12_REG_OFFSET 0x50
#define AC_RANGE_CHECK_RANGE_REGWEN_12_REG_RESVAL 0x6u
#define AC_RANGE_CHECK_RANGE_REGWEN_12_REGWEN_12_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_REGWEN_12_REGWEN_12_OFFSET 0
#define AC_RANGE_CHECK_RANGE_REGWEN_12_REGWEN_12_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_REGWEN_12_REGWEN_12_MASK, .index = AC_RANGE_CHECK_RANGE_REGWEN_12_REGWEN_12_OFFSET })
 
// This register exists per range and provides a regwen signal for the
// RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and
// RANGE_RACL_POLICY_SHADOWED_x register.
#define AC_RANGE_CHECK_RANGE_REGWEN_13_REG_OFFSET 0x54
#define AC_RANGE_CHECK_RANGE_REGWEN_13_REG_RESVAL 0x6u
#define AC_RANGE_CHECK_RANGE_REGWEN_13_REGWEN_13_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_REGWEN_13_REGWEN_13_OFFSET 0
#define AC_RANGE_CHECK_RANGE_REGWEN_13_REGWEN_13_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_REGWEN_13_REGWEN_13_MASK, .index = AC_RANGE_CHECK_RANGE_REGWEN_13_REGWEN_13_OFFSET })
 
// This register exists per range and provides a regwen signal for the
// RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and
// RANGE_RACL_POLICY_SHADOWED_x register.
#define AC_RANGE_CHECK_RANGE_REGWEN_14_REG_OFFSET 0x58
#define AC_RANGE_CHECK_RANGE_REGWEN_14_REG_RESVAL 0x6u
#define AC_RANGE_CHECK_RANGE_REGWEN_14_REGWEN_14_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_REGWEN_14_REGWEN_14_OFFSET 0
#define AC_RANGE_CHECK_RANGE_REGWEN_14_REGWEN_14_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_REGWEN_14_REGWEN_14_MASK, .index = AC_RANGE_CHECK_RANGE_REGWEN_14_REGWEN_14_OFFSET })
 
// This register exists per range and provides a regwen signal for the
// RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and
// RANGE_RACL_POLICY_SHADOWED_x register.
#define AC_RANGE_CHECK_RANGE_REGWEN_15_REG_OFFSET 0x5c
#define AC_RANGE_CHECK_RANGE_REGWEN_15_REG_RESVAL 0x6u
#define AC_RANGE_CHECK_RANGE_REGWEN_15_REGWEN_15_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_REGWEN_15_REGWEN_15_OFFSET 0
#define AC_RANGE_CHECK_RANGE_REGWEN_15_REGWEN_15_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_REGWEN_15_REGWEN_15_MASK, .index = AC_RANGE_CHECK_RANGE_REGWEN_15_REGWEN_15_OFFSET })
 
// This register exists per range and provides a regwen signal for the
// RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and
// RANGE_RACL_POLICY_SHADOWED_x register.
#define AC_RANGE_CHECK_RANGE_REGWEN_16_REG_OFFSET 0x60
#define AC_RANGE_CHECK_RANGE_REGWEN_16_REG_RESVAL 0x6u
#define AC_RANGE_CHECK_RANGE_REGWEN_16_REGWEN_16_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_REGWEN_16_REGWEN_16_OFFSET 0
#define AC_RANGE_CHECK_RANGE_REGWEN_16_REGWEN_16_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_REGWEN_16_REGWEN_16_MASK, .index = AC_RANGE_CHECK_RANGE_REGWEN_16_REGWEN_16_OFFSET })
 
// This register exists per range and provides a regwen signal for the
// RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and
// RANGE_RACL_POLICY_SHADOWED_x register.
#define AC_RANGE_CHECK_RANGE_REGWEN_17_REG_OFFSET 0x64
#define AC_RANGE_CHECK_RANGE_REGWEN_17_REG_RESVAL 0x6u
#define AC_RANGE_CHECK_RANGE_REGWEN_17_REGWEN_17_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_REGWEN_17_REGWEN_17_OFFSET 0
#define AC_RANGE_CHECK_RANGE_REGWEN_17_REGWEN_17_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_REGWEN_17_REGWEN_17_MASK, .index = AC_RANGE_CHECK_RANGE_REGWEN_17_REGWEN_17_OFFSET })
 
// This register exists per range and provides a regwen signal for the
// RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and
// RANGE_RACL_POLICY_SHADOWED_x register.
#define AC_RANGE_CHECK_RANGE_REGWEN_18_REG_OFFSET 0x68
#define AC_RANGE_CHECK_RANGE_REGWEN_18_REG_RESVAL 0x6u
#define AC_RANGE_CHECK_RANGE_REGWEN_18_REGWEN_18_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_REGWEN_18_REGWEN_18_OFFSET 0
#define AC_RANGE_CHECK_RANGE_REGWEN_18_REGWEN_18_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_REGWEN_18_REGWEN_18_MASK, .index = AC_RANGE_CHECK_RANGE_REGWEN_18_REGWEN_18_OFFSET })
 
// This register exists per range and provides a regwen signal for the
// RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and
// RANGE_RACL_POLICY_SHADOWED_x register.
#define AC_RANGE_CHECK_RANGE_REGWEN_19_REG_OFFSET 0x6c
#define AC_RANGE_CHECK_RANGE_REGWEN_19_REG_RESVAL 0x6u
#define AC_RANGE_CHECK_RANGE_REGWEN_19_REGWEN_19_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_REGWEN_19_REGWEN_19_OFFSET 0
#define AC_RANGE_CHECK_RANGE_REGWEN_19_REGWEN_19_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_REGWEN_19_REGWEN_19_MASK, .index = AC_RANGE_CHECK_RANGE_REGWEN_19_REGWEN_19_OFFSET })
 
// This register exists per range and provides a regwen signal for the
// RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and
// RANGE_RACL_POLICY_SHADOWED_x register.
#define AC_RANGE_CHECK_RANGE_REGWEN_20_REG_OFFSET 0x70
#define AC_RANGE_CHECK_RANGE_REGWEN_20_REG_RESVAL 0x6u
#define AC_RANGE_CHECK_RANGE_REGWEN_20_REGWEN_20_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_REGWEN_20_REGWEN_20_OFFSET 0
#define AC_RANGE_CHECK_RANGE_REGWEN_20_REGWEN_20_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_REGWEN_20_REGWEN_20_MASK, .index = AC_RANGE_CHECK_RANGE_REGWEN_20_REGWEN_20_OFFSET })
 
// This register exists per range and provides a regwen signal for the
// RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and
// RANGE_RACL_POLICY_SHADOWED_x register.
#define AC_RANGE_CHECK_RANGE_REGWEN_21_REG_OFFSET 0x74
#define AC_RANGE_CHECK_RANGE_REGWEN_21_REG_RESVAL 0x6u
#define AC_RANGE_CHECK_RANGE_REGWEN_21_REGWEN_21_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_REGWEN_21_REGWEN_21_OFFSET 0
#define AC_RANGE_CHECK_RANGE_REGWEN_21_REGWEN_21_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_REGWEN_21_REGWEN_21_MASK, .index = AC_RANGE_CHECK_RANGE_REGWEN_21_REGWEN_21_OFFSET })
 
// This register exists per range and provides a regwen signal for the
// RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and
// RANGE_RACL_POLICY_SHADOWED_x register.
#define AC_RANGE_CHECK_RANGE_REGWEN_22_REG_OFFSET 0x78
#define AC_RANGE_CHECK_RANGE_REGWEN_22_REG_RESVAL 0x6u
#define AC_RANGE_CHECK_RANGE_REGWEN_22_REGWEN_22_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_REGWEN_22_REGWEN_22_OFFSET 0
#define AC_RANGE_CHECK_RANGE_REGWEN_22_REGWEN_22_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_REGWEN_22_REGWEN_22_MASK, .index = AC_RANGE_CHECK_RANGE_REGWEN_22_REGWEN_22_OFFSET })
 
// This register exists per range and provides a regwen signal for the
// RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and
// RANGE_RACL_POLICY_SHADOWED_x register.
#define AC_RANGE_CHECK_RANGE_REGWEN_23_REG_OFFSET 0x7c
#define AC_RANGE_CHECK_RANGE_REGWEN_23_REG_RESVAL 0x6u
#define AC_RANGE_CHECK_RANGE_REGWEN_23_REGWEN_23_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_REGWEN_23_REGWEN_23_OFFSET 0
#define AC_RANGE_CHECK_RANGE_REGWEN_23_REGWEN_23_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_REGWEN_23_REGWEN_23_MASK, .index = AC_RANGE_CHECK_RANGE_REGWEN_23_REGWEN_23_OFFSET })
 
// This register exists per range and provides a regwen signal for the
// RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and
// RANGE_RACL_POLICY_SHADOWED_x register.
#define AC_RANGE_CHECK_RANGE_REGWEN_24_REG_OFFSET 0x80
#define AC_RANGE_CHECK_RANGE_REGWEN_24_REG_RESVAL 0x6u
#define AC_RANGE_CHECK_RANGE_REGWEN_24_REGWEN_24_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_REGWEN_24_REGWEN_24_OFFSET 0
#define AC_RANGE_CHECK_RANGE_REGWEN_24_REGWEN_24_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_REGWEN_24_REGWEN_24_MASK, .index = AC_RANGE_CHECK_RANGE_REGWEN_24_REGWEN_24_OFFSET })
 
// This register exists per range and provides a regwen signal for the
// RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and
// RANGE_RACL_POLICY_SHADOWED_x register.
#define AC_RANGE_CHECK_RANGE_REGWEN_25_REG_OFFSET 0x84
#define AC_RANGE_CHECK_RANGE_REGWEN_25_REG_RESVAL 0x6u
#define AC_RANGE_CHECK_RANGE_REGWEN_25_REGWEN_25_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_REGWEN_25_REGWEN_25_OFFSET 0
#define AC_RANGE_CHECK_RANGE_REGWEN_25_REGWEN_25_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_REGWEN_25_REGWEN_25_MASK, .index = AC_RANGE_CHECK_RANGE_REGWEN_25_REGWEN_25_OFFSET })
 
// This register exists per range and provides a regwen signal for the
// RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and
// RANGE_RACL_POLICY_SHADOWED_x register.
#define AC_RANGE_CHECK_RANGE_REGWEN_26_REG_OFFSET 0x88
#define AC_RANGE_CHECK_RANGE_REGWEN_26_REG_RESVAL 0x6u
#define AC_RANGE_CHECK_RANGE_REGWEN_26_REGWEN_26_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_REGWEN_26_REGWEN_26_OFFSET 0
#define AC_RANGE_CHECK_RANGE_REGWEN_26_REGWEN_26_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_REGWEN_26_REGWEN_26_MASK, .index = AC_RANGE_CHECK_RANGE_REGWEN_26_REGWEN_26_OFFSET })
 
// This register exists per range and provides a regwen signal for the
// RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and
// RANGE_RACL_POLICY_SHADOWED_x register.
#define AC_RANGE_CHECK_RANGE_REGWEN_27_REG_OFFSET 0x8c
#define AC_RANGE_CHECK_RANGE_REGWEN_27_REG_RESVAL 0x6u
#define AC_RANGE_CHECK_RANGE_REGWEN_27_REGWEN_27_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_REGWEN_27_REGWEN_27_OFFSET 0
#define AC_RANGE_CHECK_RANGE_REGWEN_27_REGWEN_27_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_REGWEN_27_REGWEN_27_MASK, .index = AC_RANGE_CHECK_RANGE_REGWEN_27_REGWEN_27_OFFSET })
 
// This register exists per range and provides a regwen signal for the
// RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and
// RANGE_RACL_POLICY_SHADOWED_x register.
#define AC_RANGE_CHECK_RANGE_REGWEN_28_REG_OFFSET 0x90
#define AC_RANGE_CHECK_RANGE_REGWEN_28_REG_RESVAL 0x6u
#define AC_RANGE_CHECK_RANGE_REGWEN_28_REGWEN_28_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_REGWEN_28_REGWEN_28_OFFSET 0
#define AC_RANGE_CHECK_RANGE_REGWEN_28_REGWEN_28_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_REGWEN_28_REGWEN_28_MASK, .index = AC_RANGE_CHECK_RANGE_REGWEN_28_REGWEN_28_OFFSET })
 
// This register exists per range and provides a regwen signal for the
// RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and
// RANGE_RACL_POLICY_SHADOWED_x register.
#define AC_RANGE_CHECK_RANGE_REGWEN_29_REG_OFFSET 0x94
#define AC_RANGE_CHECK_RANGE_REGWEN_29_REG_RESVAL 0x6u
#define AC_RANGE_CHECK_RANGE_REGWEN_29_REGWEN_29_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_REGWEN_29_REGWEN_29_OFFSET 0
#define AC_RANGE_CHECK_RANGE_REGWEN_29_REGWEN_29_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_REGWEN_29_REGWEN_29_MASK, .index = AC_RANGE_CHECK_RANGE_REGWEN_29_REGWEN_29_OFFSET })
 
// This register exists per range and provides a regwen signal for the
// RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and
// RANGE_RACL_POLICY_SHADOWED_x register.
#define AC_RANGE_CHECK_RANGE_REGWEN_30_REG_OFFSET 0x98
#define AC_RANGE_CHECK_RANGE_REGWEN_30_REG_RESVAL 0x6u
#define AC_RANGE_CHECK_RANGE_REGWEN_30_REGWEN_30_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_REGWEN_30_REGWEN_30_OFFSET 0
#define AC_RANGE_CHECK_RANGE_REGWEN_30_REGWEN_30_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_REGWEN_30_REGWEN_30_MASK, .index = AC_RANGE_CHECK_RANGE_REGWEN_30_REGWEN_30_OFFSET })
 
// This register exists per range and provides a regwen signal for the
// RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and
// RANGE_RACL_POLICY_SHADOWED_x register.
#define AC_RANGE_CHECK_RANGE_REGWEN_31_REG_OFFSET 0x9c
#define AC_RANGE_CHECK_RANGE_REGWEN_31_REG_RESVAL 0x6u
#define AC_RANGE_CHECK_RANGE_REGWEN_31_REGWEN_31_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_REGWEN_31_REGWEN_31_OFFSET 0
#define AC_RANGE_CHECK_RANGE_REGWEN_31_REGWEN_31_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_REGWEN_31_REGWEN_31_MASK, .index = AC_RANGE_CHECK_RANGE_REGWEN_31_REGWEN_31_OFFSET })
 
// Base address for the range check.
#define AC_RANGE_CHECK_RANGE_BASE_BASE_FIELD_WIDTH 30
#define AC_RANGE_CHECK_RANGE_BASE_MULTIREG_COUNT 32
 
// Base address for the range check.
#define AC_RANGE_CHECK_RANGE_BASE_0_REG_OFFSET 0xa0
#define AC_RANGE_CHECK_RANGE_BASE_0_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_BASE_0_BASE_0_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_BASE_0_BASE_0_OFFSET 2
#define AC_RANGE_CHECK_RANGE_BASE_0_BASE_0_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_BASE_0_BASE_0_MASK, .index = AC_RANGE_CHECK_RANGE_BASE_0_BASE_0_OFFSET })
 
// Base address for the range check.
#define AC_RANGE_CHECK_RANGE_BASE_1_REG_OFFSET 0xa4
#define AC_RANGE_CHECK_RANGE_BASE_1_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_BASE_1_BASE_1_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_BASE_1_BASE_1_OFFSET 2
#define AC_RANGE_CHECK_RANGE_BASE_1_BASE_1_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_BASE_1_BASE_1_MASK, .index = AC_RANGE_CHECK_RANGE_BASE_1_BASE_1_OFFSET })
 
// Base address for the range check.
#define AC_RANGE_CHECK_RANGE_BASE_2_REG_OFFSET 0xa8
#define AC_RANGE_CHECK_RANGE_BASE_2_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_BASE_2_BASE_2_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_BASE_2_BASE_2_OFFSET 2
#define AC_RANGE_CHECK_RANGE_BASE_2_BASE_2_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_BASE_2_BASE_2_MASK, .index = AC_RANGE_CHECK_RANGE_BASE_2_BASE_2_OFFSET })
 
// Base address for the range check.
#define AC_RANGE_CHECK_RANGE_BASE_3_REG_OFFSET 0xac
#define AC_RANGE_CHECK_RANGE_BASE_3_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_BASE_3_BASE_3_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_BASE_3_BASE_3_OFFSET 2
#define AC_RANGE_CHECK_RANGE_BASE_3_BASE_3_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_BASE_3_BASE_3_MASK, .index = AC_RANGE_CHECK_RANGE_BASE_3_BASE_3_OFFSET })
 
// Base address for the range check.
#define AC_RANGE_CHECK_RANGE_BASE_4_REG_OFFSET 0xb0
#define AC_RANGE_CHECK_RANGE_BASE_4_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_BASE_4_BASE_4_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_BASE_4_BASE_4_OFFSET 2
#define AC_RANGE_CHECK_RANGE_BASE_4_BASE_4_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_BASE_4_BASE_4_MASK, .index = AC_RANGE_CHECK_RANGE_BASE_4_BASE_4_OFFSET })
 
// Base address for the range check.
#define AC_RANGE_CHECK_RANGE_BASE_5_REG_OFFSET 0xb4
#define AC_RANGE_CHECK_RANGE_BASE_5_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_BASE_5_BASE_5_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_BASE_5_BASE_5_OFFSET 2
#define AC_RANGE_CHECK_RANGE_BASE_5_BASE_5_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_BASE_5_BASE_5_MASK, .index = AC_RANGE_CHECK_RANGE_BASE_5_BASE_5_OFFSET })
 
// Base address for the range check.
#define AC_RANGE_CHECK_RANGE_BASE_6_REG_OFFSET 0xb8
#define AC_RANGE_CHECK_RANGE_BASE_6_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_BASE_6_BASE_6_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_BASE_6_BASE_6_OFFSET 2
#define AC_RANGE_CHECK_RANGE_BASE_6_BASE_6_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_BASE_6_BASE_6_MASK, .index = AC_RANGE_CHECK_RANGE_BASE_6_BASE_6_OFFSET })
 
// Base address for the range check.
#define AC_RANGE_CHECK_RANGE_BASE_7_REG_OFFSET 0xbc
#define AC_RANGE_CHECK_RANGE_BASE_7_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_BASE_7_BASE_7_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_BASE_7_BASE_7_OFFSET 2
#define AC_RANGE_CHECK_RANGE_BASE_7_BASE_7_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_BASE_7_BASE_7_MASK, .index = AC_RANGE_CHECK_RANGE_BASE_7_BASE_7_OFFSET })
 
// Base address for the range check.
#define AC_RANGE_CHECK_RANGE_BASE_8_REG_OFFSET 0xc0
#define AC_RANGE_CHECK_RANGE_BASE_8_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_BASE_8_BASE_8_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_BASE_8_BASE_8_OFFSET 2
#define AC_RANGE_CHECK_RANGE_BASE_8_BASE_8_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_BASE_8_BASE_8_MASK, .index = AC_RANGE_CHECK_RANGE_BASE_8_BASE_8_OFFSET })
 
// Base address for the range check.
#define AC_RANGE_CHECK_RANGE_BASE_9_REG_OFFSET 0xc4
#define AC_RANGE_CHECK_RANGE_BASE_9_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_BASE_9_BASE_9_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_BASE_9_BASE_9_OFFSET 2
#define AC_RANGE_CHECK_RANGE_BASE_9_BASE_9_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_BASE_9_BASE_9_MASK, .index = AC_RANGE_CHECK_RANGE_BASE_9_BASE_9_OFFSET })
 
// Base address for the range check.
#define AC_RANGE_CHECK_RANGE_BASE_10_REG_OFFSET 0xc8
#define AC_RANGE_CHECK_RANGE_BASE_10_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_BASE_10_BASE_10_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_BASE_10_BASE_10_OFFSET 2
#define AC_RANGE_CHECK_RANGE_BASE_10_BASE_10_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_BASE_10_BASE_10_MASK, .index = AC_RANGE_CHECK_RANGE_BASE_10_BASE_10_OFFSET })
 
// Base address for the range check.
#define AC_RANGE_CHECK_RANGE_BASE_11_REG_OFFSET 0xcc
#define AC_RANGE_CHECK_RANGE_BASE_11_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_BASE_11_BASE_11_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_BASE_11_BASE_11_OFFSET 2
#define AC_RANGE_CHECK_RANGE_BASE_11_BASE_11_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_BASE_11_BASE_11_MASK, .index = AC_RANGE_CHECK_RANGE_BASE_11_BASE_11_OFFSET })
 
// Base address for the range check.
#define AC_RANGE_CHECK_RANGE_BASE_12_REG_OFFSET 0xd0
#define AC_RANGE_CHECK_RANGE_BASE_12_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_BASE_12_BASE_12_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_BASE_12_BASE_12_OFFSET 2
#define AC_RANGE_CHECK_RANGE_BASE_12_BASE_12_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_BASE_12_BASE_12_MASK, .index = AC_RANGE_CHECK_RANGE_BASE_12_BASE_12_OFFSET })
 
// Base address for the range check.
#define AC_RANGE_CHECK_RANGE_BASE_13_REG_OFFSET 0xd4
#define AC_RANGE_CHECK_RANGE_BASE_13_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_BASE_13_BASE_13_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_BASE_13_BASE_13_OFFSET 2
#define AC_RANGE_CHECK_RANGE_BASE_13_BASE_13_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_BASE_13_BASE_13_MASK, .index = AC_RANGE_CHECK_RANGE_BASE_13_BASE_13_OFFSET })
 
// Base address for the range check.
#define AC_RANGE_CHECK_RANGE_BASE_14_REG_OFFSET 0xd8
#define AC_RANGE_CHECK_RANGE_BASE_14_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_BASE_14_BASE_14_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_BASE_14_BASE_14_OFFSET 2
#define AC_RANGE_CHECK_RANGE_BASE_14_BASE_14_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_BASE_14_BASE_14_MASK, .index = AC_RANGE_CHECK_RANGE_BASE_14_BASE_14_OFFSET })
 
// Base address for the range check.
#define AC_RANGE_CHECK_RANGE_BASE_15_REG_OFFSET 0xdc
#define AC_RANGE_CHECK_RANGE_BASE_15_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_BASE_15_BASE_15_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_BASE_15_BASE_15_OFFSET 2
#define AC_RANGE_CHECK_RANGE_BASE_15_BASE_15_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_BASE_15_BASE_15_MASK, .index = AC_RANGE_CHECK_RANGE_BASE_15_BASE_15_OFFSET })
 
// Base address for the range check.
#define AC_RANGE_CHECK_RANGE_BASE_16_REG_OFFSET 0xe0
#define AC_RANGE_CHECK_RANGE_BASE_16_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_BASE_16_BASE_16_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_BASE_16_BASE_16_OFFSET 2
#define AC_RANGE_CHECK_RANGE_BASE_16_BASE_16_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_BASE_16_BASE_16_MASK, .index = AC_RANGE_CHECK_RANGE_BASE_16_BASE_16_OFFSET })
 
// Base address for the range check.
#define AC_RANGE_CHECK_RANGE_BASE_17_REG_OFFSET 0xe4
#define AC_RANGE_CHECK_RANGE_BASE_17_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_BASE_17_BASE_17_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_BASE_17_BASE_17_OFFSET 2
#define AC_RANGE_CHECK_RANGE_BASE_17_BASE_17_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_BASE_17_BASE_17_MASK, .index = AC_RANGE_CHECK_RANGE_BASE_17_BASE_17_OFFSET })
 
// Base address for the range check.
#define AC_RANGE_CHECK_RANGE_BASE_18_REG_OFFSET 0xe8
#define AC_RANGE_CHECK_RANGE_BASE_18_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_BASE_18_BASE_18_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_BASE_18_BASE_18_OFFSET 2
#define AC_RANGE_CHECK_RANGE_BASE_18_BASE_18_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_BASE_18_BASE_18_MASK, .index = AC_RANGE_CHECK_RANGE_BASE_18_BASE_18_OFFSET })
 
// Base address for the range check.
#define AC_RANGE_CHECK_RANGE_BASE_19_REG_OFFSET 0xec
#define AC_RANGE_CHECK_RANGE_BASE_19_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_BASE_19_BASE_19_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_BASE_19_BASE_19_OFFSET 2
#define AC_RANGE_CHECK_RANGE_BASE_19_BASE_19_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_BASE_19_BASE_19_MASK, .index = AC_RANGE_CHECK_RANGE_BASE_19_BASE_19_OFFSET })
 
// Base address for the range check.
#define AC_RANGE_CHECK_RANGE_BASE_20_REG_OFFSET 0xf0
#define AC_RANGE_CHECK_RANGE_BASE_20_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_BASE_20_BASE_20_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_BASE_20_BASE_20_OFFSET 2
#define AC_RANGE_CHECK_RANGE_BASE_20_BASE_20_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_BASE_20_BASE_20_MASK, .index = AC_RANGE_CHECK_RANGE_BASE_20_BASE_20_OFFSET })
 
// Base address for the range check.
#define AC_RANGE_CHECK_RANGE_BASE_21_REG_OFFSET 0xf4
#define AC_RANGE_CHECK_RANGE_BASE_21_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_BASE_21_BASE_21_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_BASE_21_BASE_21_OFFSET 2
#define AC_RANGE_CHECK_RANGE_BASE_21_BASE_21_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_BASE_21_BASE_21_MASK, .index = AC_RANGE_CHECK_RANGE_BASE_21_BASE_21_OFFSET })
 
// Base address for the range check.
#define AC_RANGE_CHECK_RANGE_BASE_22_REG_OFFSET 0xf8
#define AC_RANGE_CHECK_RANGE_BASE_22_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_BASE_22_BASE_22_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_BASE_22_BASE_22_OFFSET 2
#define AC_RANGE_CHECK_RANGE_BASE_22_BASE_22_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_BASE_22_BASE_22_MASK, .index = AC_RANGE_CHECK_RANGE_BASE_22_BASE_22_OFFSET })
 
// Base address for the range check.
#define AC_RANGE_CHECK_RANGE_BASE_23_REG_OFFSET 0xfc
#define AC_RANGE_CHECK_RANGE_BASE_23_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_BASE_23_BASE_23_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_BASE_23_BASE_23_OFFSET 2
#define AC_RANGE_CHECK_RANGE_BASE_23_BASE_23_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_BASE_23_BASE_23_MASK, .index = AC_RANGE_CHECK_RANGE_BASE_23_BASE_23_OFFSET })
 
// Base address for the range check.
#define AC_RANGE_CHECK_RANGE_BASE_24_REG_OFFSET 0x100
#define AC_RANGE_CHECK_RANGE_BASE_24_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_BASE_24_BASE_24_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_BASE_24_BASE_24_OFFSET 2
#define AC_RANGE_CHECK_RANGE_BASE_24_BASE_24_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_BASE_24_BASE_24_MASK, .index = AC_RANGE_CHECK_RANGE_BASE_24_BASE_24_OFFSET })
 
// Base address for the range check.
#define AC_RANGE_CHECK_RANGE_BASE_25_REG_OFFSET 0x104
#define AC_RANGE_CHECK_RANGE_BASE_25_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_BASE_25_BASE_25_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_BASE_25_BASE_25_OFFSET 2
#define AC_RANGE_CHECK_RANGE_BASE_25_BASE_25_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_BASE_25_BASE_25_MASK, .index = AC_RANGE_CHECK_RANGE_BASE_25_BASE_25_OFFSET })
 
// Base address for the range check.
#define AC_RANGE_CHECK_RANGE_BASE_26_REG_OFFSET 0x108
#define AC_RANGE_CHECK_RANGE_BASE_26_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_BASE_26_BASE_26_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_BASE_26_BASE_26_OFFSET 2
#define AC_RANGE_CHECK_RANGE_BASE_26_BASE_26_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_BASE_26_BASE_26_MASK, .index = AC_RANGE_CHECK_RANGE_BASE_26_BASE_26_OFFSET })
 
// Base address for the range check.
#define AC_RANGE_CHECK_RANGE_BASE_27_REG_OFFSET 0x10c
#define AC_RANGE_CHECK_RANGE_BASE_27_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_BASE_27_BASE_27_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_BASE_27_BASE_27_OFFSET 2
#define AC_RANGE_CHECK_RANGE_BASE_27_BASE_27_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_BASE_27_BASE_27_MASK, .index = AC_RANGE_CHECK_RANGE_BASE_27_BASE_27_OFFSET })
 
// Base address for the range check.
#define AC_RANGE_CHECK_RANGE_BASE_28_REG_OFFSET 0x110
#define AC_RANGE_CHECK_RANGE_BASE_28_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_BASE_28_BASE_28_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_BASE_28_BASE_28_OFFSET 2
#define AC_RANGE_CHECK_RANGE_BASE_28_BASE_28_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_BASE_28_BASE_28_MASK, .index = AC_RANGE_CHECK_RANGE_BASE_28_BASE_28_OFFSET })
 
// Base address for the range check.
#define AC_RANGE_CHECK_RANGE_BASE_29_REG_OFFSET 0x114
#define AC_RANGE_CHECK_RANGE_BASE_29_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_BASE_29_BASE_29_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_BASE_29_BASE_29_OFFSET 2
#define AC_RANGE_CHECK_RANGE_BASE_29_BASE_29_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_BASE_29_BASE_29_MASK, .index = AC_RANGE_CHECK_RANGE_BASE_29_BASE_29_OFFSET })
 
// Base address for the range check.
#define AC_RANGE_CHECK_RANGE_BASE_30_REG_OFFSET 0x118
#define AC_RANGE_CHECK_RANGE_BASE_30_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_BASE_30_BASE_30_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_BASE_30_BASE_30_OFFSET 2
#define AC_RANGE_CHECK_RANGE_BASE_30_BASE_30_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_BASE_30_BASE_30_MASK, .index = AC_RANGE_CHECK_RANGE_BASE_30_BASE_30_OFFSET })
 
// Base address for the range check.
#define AC_RANGE_CHECK_RANGE_BASE_31_REG_OFFSET 0x11c
#define AC_RANGE_CHECK_RANGE_BASE_31_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_BASE_31_BASE_31_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_BASE_31_BASE_31_OFFSET 2
#define AC_RANGE_CHECK_RANGE_BASE_31_BASE_31_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_BASE_31_BASE_31_MASK, .index = AC_RANGE_CHECK_RANGE_BASE_31_BASE_31_OFFSET })
 
// The (exclusive) limit address register used for the address matching.
// (common parameters)
#define AC_RANGE_CHECK_RANGE_LIMIT_LIMIT_FIELD_WIDTH 30
#define AC_RANGE_CHECK_RANGE_LIMIT_MULTIREG_COUNT 32
 
// The (exclusive) limit address register used for the address matching.
#define AC_RANGE_CHECK_RANGE_LIMIT_0_REG_OFFSET 0x120
#define AC_RANGE_CHECK_RANGE_LIMIT_0_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_LIMIT_0_LIMIT_0_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_LIMIT_0_LIMIT_0_OFFSET 2
#define AC_RANGE_CHECK_RANGE_LIMIT_0_LIMIT_0_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_LIMIT_0_LIMIT_0_MASK, .index = AC_RANGE_CHECK_RANGE_LIMIT_0_LIMIT_0_OFFSET })
 
// The (exclusive) limit address register used for the address matching.
#define AC_RANGE_CHECK_RANGE_LIMIT_1_REG_OFFSET 0x124
#define AC_RANGE_CHECK_RANGE_LIMIT_1_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_LIMIT_1_LIMIT_1_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_LIMIT_1_LIMIT_1_OFFSET 2
#define AC_RANGE_CHECK_RANGE_LIMIT_1_LIMIT_1_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_LIMIT_1_LIMIT_1_MASK, .index = AC_RANGE_CHECK_RANGE_LIMIT_1_LIMIT_1_OFFSET })
 
// The (exclusive) limit address register used for the address matching.
#define AC_RANGE_CHECK_RANGE_LIMIT_2_REG_OFFSET 0x128
#define AC_RANGE_CHECK_RANGE_LIMIT_2_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_LIMIT_2_LIMIT_2_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_LIMIT_2_LIMIT_2_OFFSET 2
#define AC_RANGE_CHECK_RANGE_LIMIT_2_LIMIT_2_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_LIMIT_2_LIMIT_2_MASK, .index = AC_RANGE_CHECK_RANGE_LIMIT_2_LIMIT_2_OFFSET })
 
// The (exclusive) limit address register used for the address matching.
#define AC_RANGE_CHECK_RANGE_LIMIT_3_REG_OFFSET 0x12c
#define AC_RANGE_CHECK_RANGE_LIMIT_3_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_LIMIT_3_LIMIT_3_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_LIMIT_3_LIMIT_3_OFFSET 2
#define AC_RANGE_CHECK_RANGE_LIMIT_3_LIMIT_3_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_LIMIT_3_LIMIT_3_MASK, .index = AC_RANGE_CHECK_RANGE_LIMIT_3_LIMIT_3_OFFSET })
 
// The (exclusive) limit address register used for the address matching.
#define AC_RANGE_CHECK_RANGE_LIMIT_4_REG_OFFSET 0x130
#define AC_RANGE_CHECK_RANGE_LIMIT_4_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_LIMIT_4_LIMIT_4_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_LIMIT_4_LIMIT_4_OFFSET 2
#define AC_RANGE_CHECK_RANGE_LIMIT_4_LIMIT_4_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_LIMIT_4_LIMIT_4_MASK, .index = AC_RANGE_CHECK_RANGE_LIMIT_4_LIMIT_4_OFFSET })
 
// The (exclusive) limit address register used for the address matching.
#define AC_RANGE_CHECK_RANGE_LIMIT_5_REG_OFFSET 0x134
#define AC_RANGE_CHECK_RANGE_LIMIT_5_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_LIMIT_5_LIMIT_5_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_LIMIT_5_LIMIT_5_OFFSET 2
#define AC_RANGE_CHECK_RANGE_LIMIT_5_LIMIT_5_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_LIMIT_5_LIMIT_5_MASK, .index = AC_RANGE_CHECK_RANGE_LIMIT_5_LIMIT_5_OFFSET })
 
// The (exclusive) limit address register used for the address matching.
#define AC_RANGE_CHECK_RANGE_LIMIT_6_REG_OFFSET 0x138
#define AC_RANGE_CHECK_RANGE_LIMIT_6_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_LIMIT_6_LIMIT_6_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_LIMIT_6_LIMIT_6_OFFSET 2
#define AC_RANGE_CHECK_RANGE_LIMIT_6_LIMIT_6_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_LIMIT_6_LIMIT_6_MASK, .index = AC_RANGE_CHECK_RANGE_LIMIT_6_LIMIT_6_OFFSET })
 
// The (exclusive) limit address register used for the address matching.
#define AC_RANGE_CHECK_RANGE_LIMIT_7_REG_OFFSET 0x13c
#define AC_RANGE_CHECK_RANGE_LIMIT_7_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_LIMIT_7_LIMIT_7_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_LIMIT_7_LIMIT_7_OFFSET 2
#define AC_RANGE_CHECK_RANGE_LIMIT_7_LIMIT_7_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_LIMIT_7_LIMIT_7_MASK, .index = AC_RANGE_CHECK_RANGE_LIMIT_7_LIMIT_7_OFFSET })
 
// The (exclusive) limit address register used for the address matching.
#define AC_RANGE_CHECK_RANGE_LIMIT_8_REG_OFFSET 0x140
#define AC_RANGE_CHECK_RANGE_LIMIT_8_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_LIMIT_8_LIMIT_8_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_LIMIT_8_LIMIT_8_OFFSET 2
#define AC_RANGE_CHECK_RANGE_LIMIT_8_LIMIT_8_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_LIMIT_8_LIMIT_8_MASK, .index = AC_RANGE_CHECK_RANGE_LIMIT_8_LIMIT_8_OFFSET })
 
// The (exclusive) limit address register used for the address matching.
#define AC_RANGE_CHECK_RANGE_LIMIT_9_REG_OFFSET 0x144
#define AC_RANGE_CHECK_RANGE_LIMIT_9_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_LIMIT_9_LIMIT_9_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_LIMIT_9_LIMIT_9_OFFSET 2
#define AC_RANGE_CHECK_RANGE_LIMIT_9_LIMIT_9_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_LIMIT_9_LIMIT_9_MASK, .index = AC_RANGE_CHECK_RANGE_LIMIT_9_LIMIT_9_OFFSET })
 
// The (exclusive) limit address register used for the address matching.
#define AC_RANGE_CHECK_RANGE_LIMIT_10_REG_OFFSET 0x148
#define AC_RANGE_CHECK_RANGE_LIMIT_10_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_LIMIT_10_LIMIT_10_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_LIMIT_10_LIMIT_10_OFFSET 2
#define AC_RANGE_CHECK_RANGE_LIMIT_10_LIMIT_10_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_LIMIT_10_LIMIT_10_MASK, .index = AC_RANGE_CHECK_RANGE_LIMIT_10_LIMIT_10_OFFSET })
 
// The (exclusive) limit address register used for the address matching.
#define AC_RANGE_CHECK_RANGE_LIMIT_11_REG_OFFSET 0x14c
#define AC_RANGE_CHECK_RANGE_LIMIT_11_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_LIMIT_11_LIMIT_11_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_LIMIT_11_LIMIT_11_OFFSET 2
#define AC_RANGE_CHECK_RANGE_LIMIT_11_LIMIT_11_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_LIMIT_11_LIMIT_11_MASK, .index = AC_RANGE_CHECK_RANGE_LIMIT_11_LIMIT_11_OFFSET })
 
// The (exclusive) limit address register used for the address matching.
#define AC_RANGE_CHECK_RANGE_LIMIT_12_REG_OFFSET 0x150
#define AC_RANGE_CHECK_RANGE_LIMIT_12_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_LIMIT_12_LIMIT_12_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_LIMIT_12_LIMIT_12_OFFSET 2
#define AC_RANGE_CHECK_RANGE_LIMIT_12_LIMIT_12_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_LIMIT_12_LIMIT_12_MASK, .index = AC_RANGE_CHECK_RANGE_LIMIT_12_LIMIT_12_OFFSET })
 
// The (exclusive) limit address register used for the address matching.
#define AC_RANGE_CHECK_RANGE_LIMIT_13_REG_OFFSET 0x154
#define AC_RANGE_CHECK_RANGE_LIMIT_13_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_LIMIT_13_LIMIT_13_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_LIMIT_13_LIMIT_13_OFFSET 2
#define AC_RANGE_CHECK_RANGE_LIMIT_13_LIMIT_13_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_LIMIT_13_LIMIT_13_MASK, .index = AC_RANGE_CHECK_RANGE_LIMIT_13_LIMIT_13_OFFSET })
 
// The (exclusive) limit address register used for the address matching.
#define AC_RANGE_CHECK_RANGE_LIMIT_14_REG_OFFSET 0x158
#define AC_RANGE_CHECK_RANGE_LIMIT_14_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_LIMIT_14_LIMIT_14_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_LIMIT_14_LIMIT_14_OFFSET 2
#define AC_RANGE_CHECK_RANGE_LIMIT_14_LIMIT_14_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_LIMIT_14_LIMIT_14_MASK, .index = AC_RANGE_CHECK_RANGE_LIMIT_14_LIMIT_14_OFFSET })
 
// The (exclusive) limit address register used for the address matching.
#define AC_RANGE_CHECK_RANGE_LIMIT_15_REG_OFFSET 0x15c
#define AC_RANGE_CHECK_RANGE_LIMIT_15_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_LIMIT_15_LIMIT_15_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_LIMIT_15_LIMIT_15_OFFSET 2
#define AC_RANGE_CHECK_RANGE_LIMIT_15_LIMIT_15_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_LIMIT_15_LIMIT_15_MASK, .index = AC_RANGE_CHECK_RANGE_LIMIT_15_LIMIT_15_OFFSET })
 
// The (exclusive) limit address register used for the address matching.
#define AC_RANGE_CHECK_RANGE_LIMIT_16_REG_OFFSET 0x160
#define AC_RANGE_CHECK_RANGE_LIMIT_16_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_LIMIT_16_LIMIT_16_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_LIMIT_16_LIMIT_16_OFFSET 2
#define AC_RANGE_CHECK_RANGE_LIMIT_16_LIMIT_16_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_LIMIT_16_LIMIT_16_MASK, .index = AC_RANGE_CHECK_RANGE_LIMIT_16_LIMIT_16_OFFSET })
 
// The (exclusive) limit address register used for the address matching.
#define AC_RANGE_CHECK_RANGE_LIMIT_17_REG_OFFSET 0x164
#define AC_RANGE_CHECK_RANGE_LIMIT_17_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_LIMIT_17_LIMIT_17_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_LIMIT_17_LIMIT_17_OFFSET 2
#define AC_RANGE_CHECK_RANGE_LIMIT_17_LIMIT_17_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_LIMIT_17_LIMIT_17_MASK, .index = AC_RANGE_CHECK_RANGE_LIMIT_17_LIMIT_17_OFFSET })
 
// The (exclusive) limit address register used for the address matching.
#define AC_RANGE_CHECK_RANGE_LIMIT_18_REG_OFFSET 0x168
#define AC_RANGE_CHECK_RANGE_LIMIT_18_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_LIMIT_18_LIMIT_18_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_LIMIT_18_LIMIT_18_OFFSET 2
#define AC_RANGE_CHECK_RANGE_LIMIT_18_LIMIT_18_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_LIMIT_18_LIMIT_18_MASK, .index = AC_RANGE_CHECK_RANGE_LIMIT_18_LIMIT_18_OFFSET })
 
// The (exclusive) limit address register used for the address matching.
#define AC_RANGE_CHECK_RANGE_LIMIT_19_REG_OFFSET 0x16c
#define AC_RANGE_CHECK_RANGE_LIMIT_19_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_LIMIT_19_LIMIT_19_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_LIMIT_19_LIMIT_19_OFFSET 2
#define AC_RANGE_CHECK_RANGE_LIMIT_19_LIMIT_19_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_LIMIT_19_LIMIT_19_MASK, .index = AC_RANGE_CHECK_RANGE_LIMIT_19_LIMIT_19_OFFSET })
 
// The (exclusive) limit address register used for the address matching.
#define AC_RANGE_CHECK_RANGE_LIMIT_20_REG_OFFSET 0x170
#define AC_RANGE_CHECK_RANGE_LIMIT_20_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_LIMIT_20_LIMIT_20_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_LIMIT_20_LIMIT_20_OFFSET 2
#define AC_RANGE_CHECK_RANGE_LIMIT_20_LIMIT_20_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_LIMIT_20_LIMIT_20_MASK, .index = AC_RANGE_CHECK_RANGE_LIMIT_20_LIMIT_20_OFFSET })
 
// The (exclusive) limit address register used for the address matching.
#define AC_RANGE_CHECK_RANGE_LIMIT_21_REG_OFFSET 0x174
#define AC_RANGE_CHECK_RANGE_LIMIT_21_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_LIMIT_21_LIMIT_21_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_LIMIT_21_LIMIT_21_OFFSET 2
#define AC_RANGE_CHECK_RANGE_LIMIT_21_LIMIT_21_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_LIMIT_21_LIMIT_21_MASK, .index = AC_RANGE_CHECK_RANGE_LIMIT_21_LIMIT_21_OFFSET })
 
// The (exclusive) limit address register used for the address matching.
#define AC_RANGE_CHECK_RANGE_LIMIT_22_REG_OFFSET 0x178
#define AC_RANGE_CHECK_RANGE_LIMIT_22_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_LIMIT_22_LIMIT_22_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_LIMIT_22_LIMIT_22_OFFSET 2
#define AC_RANGE_CHECK_RANGE_LIMIT_22_LIMIT_22_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_LIMIT_22_LIMIT_22_MASK, .index = AC_RANGE_CHECK_RANGE_LIMIT_22_LIMIT_22_OFFSET })
 
// The (exclusive) limit address register used for the address matching.
#define AC_RANGE_CHECK_RANGE_LIMIT_23_REG_OFFSET 0x17c
#define AC_RANGE_CHECK_RANGE_LIMIT_23_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_LIMIT_23_LIMIT_23_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_LIMIT_23_LIMIT_23_OFFSET 2
#define AC_RANGE_CHECK_RANGE_LIMIT_23_LIMIT_23_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_LIMIT_23_LIMIT_23_MASK, .index = AC_RANGE_CHECK_RANGE_LIMIT_23_LIMIT_23_OFFSET })
 
// The (exclusive) limit address register used for the address matching.
#define AC_RANGE_CHECK_RANGE_LIMIT_24_REG_OFFSET 0x180
#define AC_RANGE_CHECK_RANGE_LIMIT_24_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_LIMIT_24_LIMIT_24_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_LIMIT_24_LIMIT_24_OFFSET 2
#define AC_RANGE_CHECK_RANGE_LIMIT_24_LIMIT_24_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_LIMIT_24_LIMIT_24_MASK, .index = AC_RANGE_CHECK_RANGE_LIMIT_24_LIMIT_24_OFFSET })
 
// The (exclusive) limit address register used for the address matching.
#define AC_RANGE_CHECK_RANGE_LIMIT_25_REG_OFFSET 0x184
#define AC_RANGE_CHECK_RANGE_LIMIT_25_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_LIMIT_25_LIMIT_25_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_LIMIT_25_LIMIT_25_OFFSET 2
#define AC_RANGE_CHECK_RANGE_LIMIT_25_LIMIT_25_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_LIMIT_25_LIMIT_25_MASK, .index = AC_RANGE_CHECK_RANGE_LIMIT_25_LIMIT_25_OFFSET })
 
// The (exclusive) limit address register used for the address matching.
#define AC_RANGE_CHECK_RANGE_LIMIT_26_REG_OFFSET 0x188
#define AC_RANGE_CHECK_RANGE_LIMIT_26_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_LIMIT_26_LIMIT_26_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_LIMIT_26_LIMIT_26_OFFSET 2
#define AC_RANGE_CHECK_RANGE_LIMIT_26_LIMIT_26_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_LIMIT_26_LIMIT_26_MASK, .index = AC_RANGE_CHECK_RANGE_LIMIT_26_LIMIT_26_OFFSET })
 
// The (exclusive) limit address register used for the address matching.
#define AC_RANGE_CHECK_RANGE_LIMIT_27_REG_OFFSET 0x18c
#define AC_RANGE_CHECK_RANGE_LIMIT_27_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_LIMIT_27_LIMIT_27_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_LIMIT_27_LIMIT_27_OFFSET 2
#define AC_RANGE_CHECK_RANGE_LIMIT_27_LIMIT_27_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_LIMIT_27_LIMIT_27_MASK, .index = AC_RANGE_CHECK_RANGE_LIMIT_27_LIMIT_27_OFFSET })
 
// The (exclusive) limit address register used for the address matching.
#define AC_RANGE_CHECK_RANGE_LIMIT_28_REG_OFFSET 0x190
#define AC_RANGE_CHECK_RANGE_LIMIT_28_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_LIMIT_28_LIMIT_28_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_LIMIT_28_LIMIT_28_OFFSET 2
#define AC_RANGE_CHECK_RANGE_LIMIT_28_LIMIT_28_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_LIMIT_28_LIMIT_28_MASK, .index = AC_RANGE_CHECK_RANGE_LIMIT_28_LIMIT_28_OFFSET })
 
// The (exclusive) limit address register used for the address matching.
#define AC_RANGE_CHECK_RANGE_LIMIT_29_REG_OFFSET 0x194
#define AC_RANGE_CHECK_RANGE_LIMIT_29_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_LIMIT_29_LIMIT_29_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_LIMIT_29_LIMIT_29_OFFSET 2
#define AC_RANGE_CHECK_RANGE_LIMIT_29_LIMIT_29_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_LIMIT_29_LIMIT_29_MASK, .index = AC_RANGE_CHECK_RANGE_LIMIT_29_LIMIT_29_OFFSET })
 
// The (exclusive) limit address register used for the address matching.
#define AC_RANGE_CHECK_RANGE_LIMIT_30_REG_OFFSET 0x198
#define AC_RANGE_CHECK_RANGE_LIMIT_30_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_LIMIT_30_LIMIT_30_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_LIMIT_30_LIMIT_30_OFFSET 2
#define AC_RANGE_CHECK_RANGE_LIMIT_30_LIMIT_30_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_LIMIT_30_LIMIT_30_MASK, .index = AC_RANGE_CHECK_RANGE_LIMIT_30_LIMIT_30_OFFSET })
 
// The (exclusive) limit address register used for the address matching.
#define AC_RANGE_CHECK_RANGE_LIMIT_31_REG_OFFSET 0x19c
#define AC_RANGE_CHECK_RANGE_LIMIT_31_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_LIMIT_31_LIMIT_31_MASK 0x3fffffffu
#define AC_RANGE_CHECK_RANGE_LIMIT_31_LIMIT_31_OFFSET 2
#define AC_RANGE_CHECK_RANGE_LIMIT_31_LIMIT_31_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_LIMIT_31_LIMIT_31_MASK, .index = AC_RANGE_CHECK_RANGE_LIMIT_31_LIMIT_31_OFFSET })
 
// Attributes of the range.
#define AC_RANGE_CHECK_RANGE_ATTR_ENABLE_FIELD_WIDTH 4
#define AC_RANGE_CHECK_RANGE_ATTR_READ_ACCESS_FIELD_WIDTH 4
#define AC_RANGE_CHECK_RANGE_ATTR_WRITE_ACCESS_FIELD_WIDTH 4
#define AC_RANGE_CHECK_RANGE_ATTR_EXECUTE_ACCESS_FIELD_WIDTH 4
#define AC_RANGE_CHECK_RANGE_ATTR_LOG_DENIED_ACCESS_FIELD_WIDTH 4
#define AC_RANGE_CHECK_RANGE_ATTR_MULTIREG_COUNT 32
 
// Attributes of the range.
#define AC_RANGE_CHECK_RANGE_ATTR_0_REG_OFFSET 0x1a0
#define AC_RANGE_CHECK_RANGE_ATTR_0_REG_RESVAL 0x69999u
#define AC_RANGE_CHECK_RANGE_ATTR_0_ENABLE_0_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_0_ENABLE_0_OFFSET 0
#define AC_RANGE_CHECK_RANGE_ATTR_0_ENABLE_0_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_0_ENABLE_0_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_0_ENABLE_0_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_0_READ_ACCESS_0_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_0_READ_ACCESS_0_OFFSET 4
#define AC_RANGE_CHECK_RANGE_ATTR_0_READ_ACCESS_0_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_0_READ_ACCESS_0_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_0_READ_ACCESS_0_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_0_WRITE_ACCESS_0_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_0_WRITE_ACCESS_0_OFFSET 8
#define AC_RANGE_CHECK_RANGE_ATTR_0_WRITE_ACCESS_0_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_0_WRITE_ACCESS_0_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_0_WRITE_ACCESS_0_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_0_EXECUTE_ACCESS_0_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_0_EXECUTE_ACCESS_0_OFFSET 12
#define AC_RANGE_CHECK_RANGE_ATTR_0_EXECUTE_ACCESS_0_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_0_EXECUTE_ACCESS_0_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_0_EXECUTE_ACCESS_0_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_0_LOG_DENIED_ACCESS_0_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_0_LOG_DENIED_ACCESS_0_OFFSET 16
#define AC_RANGE_CHECK_RANGE_ATTR_0_LOG_DENIED_ACCESS_0_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_0_LOG_DENIED_ACCESS_0_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_0_LOG_DENIED_ACCESS_0_OFFSET })
 
// Attributes of the range.
#define AC_RANGE_CHECK_RANGE_ATTR_1_REG_OFFSET 0x1a4
#define AC_RANGE_CHECK_RANGE_ATTR_1_REG_RESVAL 0x69999u
#define AC_RANGE_CHECK_RANGE_ATTR_1_ENABLE_1_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_1_ENABLE_1_OFFSET 0
#define AC_RANGE_CHECK_RANGE_ATTR_1_ENABLE_1_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_1_ENABLE_1_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_1_ENABLE_1_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_1_READ_ACCESS_1_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_1_READ_ACCESS_1_OFFSET 4
#define AC_RANGE_CHECK_RANGE_ATTR_1_READ_ACCESS_1_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_1_READ_ACCESS_1_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_1_READ_ACCESS_1_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_1_WRITE_ACCESS_1_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_1_WRITE_ACCESS_1_OFFSET 8
#define AC_RANGE_CHECK_RANGE_ATTR_1_WRITE_ACCESS_1_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_1_WRITE_ACCESS_1_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_1_WRITE_ACCESS_1_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_1_EXECUTE_ACCESS_1_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_1_EXECUTE_ACCESS_1_OFFSET 12
#define AC_RANGE_CHECK_RANGE_ATTR_1_EXECUTE_ACCESS_1_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_1_EXECUTE_ACCESS_1_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_1_EXECUTE_ACCESS_1_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_1_LOG_DENIED_ACCESS_1_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_1_LOG_DENIED_ACCESS_1_OFFSET 16
#define AC_RANGE_CHECK_RANGE_ATTR_1_LOG_DENIED_ACCESS_1_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_1_LOG_DENIED_ACCESS_1_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_1_LOG_DENIED_ACCESS_1_OFFSET })
 
// Attributes of the range.
#define AC_RANGE_CHECK_RANGE_ATTR_2_REG_OFFSET 0x1a8
#define AC_RANGE_CHECK_RANGE_ATTR_2_REG_RESVAL 0x69999u
#define AC_RANGE_CHECK_RANGE_ATTR_2_ENABLE_2_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_2_ENABLE_2_OFFSET 0
#define AC_RANGE_CHECK_RANGE_ATTR_2_ENABLE_2_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_2_ENABLE_2_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_2_ENABLE_2_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_2_READ_ACCESS_2_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_2_READ_ACCESS_2_OFFSET 4
#define AC_RANGE_CHECK_RANGE_ATTR_2_READ_ACCESS_2_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_2_READ_ACCESS_2_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_2_READ_ACCESS_2_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_2_WRITE_ACCESS_2_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_2_WRITE_ACCESS_2_OFFSET 8
#define AC_RANGE_CHECK_RANGE_ATTR_2_WRITE_ACCESS_2_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_2_WRITE_ACCESS_2_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_2_WRITE_ACCESS_2_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_2_EXECUTE_ACCESS_2_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_2_EXECUTE_ACCESS_2_OFFSET 12
#define AC_RANGE_CHECK_RANGE_ATTR_2_EXECUTE_ACCESS_2_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_2_EXECUTE_ACCESS_2_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_2_EXECUTE_ACCESS_2_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_2_LOG_DENIED_ACCESS_2_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_2_LOG_DENIED_ACCESS_2_OFFSET 16
#define AC_RANGE_CHECK_RANGE_ATTR_2_LOG_DENIED_ACCESS_2_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_2_LOG_DENIED_ACCESS_2_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_2_LOG_DENIED_ACCESS_2_OFFSET })
 
// Attributes of the range.
#define AC_RANGE_CHECK_RANGE_ATTR_3_REG_OFFSET 0x1ac
#define AC_RANGE_CHECK_RANGE_ATTR_3_REG_RESVAL 0x69999u
#define AC_RANGE_CHECK_RANGE_ATTR_3_ENABLE_3_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_3_ENABLE_3_OFFSET 0
#define AC_RANGE_CHECK_RANGE_ATTR_3_ENABLE_3_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_3_ENABLE_3_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_3_ENABLE_3_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_3_READ_ACCESS_3_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_3_READ_ACCESS_3_OFFSET 4
#define AC_RANGE_CHECK_RANGE_ATTR_3_READ_ACCESS_3_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_3_READ_ACCESS_3_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_3_READ_ACCESS_3_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_3_WRITE_ACCESS_3_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_3_WRITE_ACCESS_3_OFFSET 8
#define AC_RANGE_CHECK_RANGE_ATTR_3_WRITE_ACCESS_3_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_3_WRITE_ACCESS_3_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_3_WRITE_ACCESS_3_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_3_EXECUTE_ACCESS_3_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_3_EXECUTE_ACCESS_3_OFFSET 12
#define AC_RANGE_CHECK_RANGE_ATTR_3_EXECUTE_ACCESS_3_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_3_EXECUTE_ACCESS_3_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_3_EXECUTE_ACCESS_3_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_3_LOG_DENIED_ACCESS_3_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_3_LOG_DENIED_ACCESS_3_OFFSET 16
#define AC_RANGE_CHECK_RANGE_ATTR_3_LOG_DENIED_ACCESS_3_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_3_LOG_DENIED_ACCESS_3_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_3_LOG_DENIED_ACCESS_3_OFFSET })
 
// Attributes of the range.
#define AC_RANGE_CHECK_RANGE_ATTR_4_REG_OFFSET 0x1b0
#define AC_RANGE_CHECK_RANGE_ATTR_4_REG_RESVAL 0x69999u
#define AC_RANGE_CHECK_RANGE_ATTR_4_ENABLE_4_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_4_ENABLE_4_OFFSET 0
#define AC_RANGE_CHECK_RANGE_ATTR_4_ENABLE_4_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_4_ENABLE_4_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_4_ENABLE_4_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_4_READ_ACCESS_4_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_4_READ_ACCESS_4_OFFSET 4
#define AC_RANGE_CHECK_RANGE_ATTR_4_READ_ACCESS_4_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_4_READ_ACCESS_4_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_4_READ_ACCESS_4_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_4_WRITE_ACCESS_4_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_4_WRITE_ACCESS_4_OFFSET 8
#define AC_RANGE_CHECK_RANGE_ATTR_4_WRITE_ACCESS_4_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_4_WRITE_ACCESS_4_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_4_WRITE_ACCESS_4_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_4_EXECUTE_ACCESS_4_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_4_EXECUTE_ACCESS_4_OFFSET 12
#define AC_RANGE_CHECK_RANGE_ATTR_4_EXECUTE_ACCESS_4_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_4_EXECUTE_ACCESS_4_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_4_EXECUTE_ACCESS_4_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_4_LOG_DENIED_ACCESS_4_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_4_LOG_DENIED_ACCESS_4_OFFSET 16
#define AC_RANGE_CHECK_RANGE_ATTR_4_LOG_DENIED_ACCESS_4_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_4_LOG_DENIED_ACCESS_4_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_4_LOG_DENIED_ACCESS_4_OFFSET })
 
// Attributes of the range.
#define AC_RANGE_CHECK_RANGE_ATTR_5_REG_OFFSET 0x1b4
#define AC_RANGE_CHECK_RANGE_ATTR_5_REG_RESVAL 0x69999u
#define AC_RANGE_CHECK_RANGE_ATTR_5_ENABLE_5_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_5_ENABLE_5_OFFSET 0
#define AC_RANGE_CHECK_RANGE_ATTR_5_ENABLE_5_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_5_ENABLE_5_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_5_ENABLE_5_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_5_READ_ACCESS_5_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_5_READ_ACCESS_5_OFFSET 4
#define AC_RANGE_CHECK_RANGE_ATTR_5_READ_ACCESS_5_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_5_READ_ACCESS_5_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_5_READ_ACCESS_5_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_5_WRITE_ACCESS_5_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_5_WRITE_ACCESS_5_OFFSET 8
#define AC_RANGE_CHECK_RANGE_ATTR_5_WRITE_ACCESS_5_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_5_WRITE_ACCESS_5_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_5_WRITE_ACCESS_5_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_5_EXECUTE_ACCESS_5_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_5_EXECUTE_ACCESS_5_OFFSET 12
#define AC_RANGE_CHECK_RANGE_ATTR_5_EXECUTE_ACCESS_5_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_5_EXECUTE_ACCESS_5_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_5_EXECUTE_ACCESS_5_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_5_LOG_DENIED_ACCESS_5_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_5_LOG_DENIED_ACCESS_5_OFFSET 16
#define AC_RANGE_CHECK_RANGE_ATTR_5_LOG_DENIED_ACCESS_5_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_5_LOG_DENIED_ACCESS_5_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_5_LOG_DENIED_ACCESS_5_OFFSET })
 
// Attributes of the range.
#define AC_RANGE_CHECK_RANGE_ATTR_6_REG_OFFSET 0x1b8
#define AC_RANGE_CHECK_RANGE_ATTR_6_REG_RESVAL 0x69999u
#define AC_RANGE_CHECK_RANGE_ATTR_6_ENABLE_6_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_6_ENABLE_6_OFFSET 0
#define AC_RANGE_CHECK_RANGE_ATTR_6_ENABLE_6_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_6_ENABLE_6_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_6_ENABLE_6_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_6_READ_ACCESS_6_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_6_READ_ACCESS_6_OFFSET 4
#define AC_RANGE_CHECK_RANGE_ATTR_6_READ_ACCESS_6_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_6_READ_ACCESS_6_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_6_READ_ACCESS_6_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_6_WRITE_ACCESS_6_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_6_WRITE_ACCESS_6_OFFSET 8
#define AC_RANGE_CHECK_RANGE_ATTR_6_WRITE_ACCESS_6_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_6_WRITE_ACCESS_6_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_6_WRITE_ACCESS_6_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_6_EXECUTE_ACCESS_6_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_6_EXECUTE_ACCESS_6_OFFSET 12
#define AC_RANGE_CHECK_RANGE_ATTR_6_EXECUTE_ACCESS_6_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_6_EXECUTE_ACCESS_6_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_6_EXECUTE_ACCESS_6_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_6_LOG_DENIED_ACCESS_6_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_6_LOG_DENIED_ACCESS_6_OFFSET 16
#define AC_RANGE_CHECK_RANGE_ATTR_6_LOG_DENIED_ACCESS_6_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_6_LOG_DENIED_ACCESS_6_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_6_LOG_DENIED_ACCESS_6_OFFSET })
 
// Attributes of the range.
#define AC_RANGE_CHECK_RANGE_ATTR_7_REG_OFFSET 0x1bc
#define AC_RANGE_CHECK_RANGE_ATTR_7_REG_RESVAL 0x69999u
#define AC_RANGE_CHECK_RANGE_ATTR_7_ENABLE_7_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_7_ENABLE_7_OFFSET 0
#define AC_RANGE_CHECK_RANGE_ATTR_7_ENABLE_7_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_7_ENABLE_7_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_7_ENABLE_7_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_7_READ_ACCESS_7_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_7_READ_ACCESS_7_OFFSET 4
#define AC_RANGE_CHECK_RANGE_ATTR_7_READ_ACCESS_7_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_7_READ_ACCESS_7_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_7_READ_ACCESS_7_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_7_WRITE_ACCESS_7_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_7_WRITE_ACCESS_7_OFFSET 8
#define AC_RANGE_CHECK_RANGE_ATTR_7_WRITE_ACCESS_7_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_7_WRITE_ACCESS_7_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_7_WRITE_ACCESS_7_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_7_EXECUTE_ACCESS_7_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_7_EXECUTE_ACCESS_7_OFFSET 12
#define AC_RANGE_CHECK_RANGE_ATTR_7_EXECUTE_ACCESS_7_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_7_EXECUTE_ACCESS_7_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_7_EXECUTE_ACCESS_7_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_7_LOG_DENIED_ACCESS_7_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_7_LOG_DENIED_ACCESS_7_OFFSET 16
#define AC_RANGE_CHECK_RANGE_ATTR_7_LOG_DENIED_ACCESS_7_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_7_LOG_DENIED_ACCESS_7_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_7_LOG_DENIED_ACCESS_7_OFFSET })
 
// Attributes of the range.
#define AC_RANGE_CHECK_RANGE_ATTR_8_REG_OFFSET 0x1c0
#define AC_RANGE_CHECK_RANGE_ATTR_8_REG_RESVAL 0x69999u
#define AC_RANGE_CHECK_RANGE_ATTR_8_ENABLE_8_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_8_ENABLE_8_OFFSET 0
#define AC_RANGE_CHECK_RANGE_ATTR_8_ENABLE_8_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_8_ENABLE_8_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_8_ENABLE_8_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_8_READ_ACCESS_8_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_8_READ_ACCESS_8_OFFSET 4
#define AC_RANGE_CHECK_RANGE_ATTR_8_READ_ACCESS_8_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_8_READ_ACCESS_8_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_8_READ_ACCESS_8_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_8_WRITE_ACCESS_8_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_8_WRITE_ACCESS_8_OFFSET 8
#define AC_RANGE_CHECK_RANGE_ATTR_8_WRITE_ACCESS_8_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_8_WRITE_ACCESS_8_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_8_WRITE_ACCESS_8_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_8_EXECUTE_ACCESS_8_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_8_EXECUTE_ACCESS_8_OFFSET 12
#define AC_RANGE_CHECK_RANGE_ATTR_8_EXECUTE_ACCESS_8_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_8_EXECUTE_ACCESS_8_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_8_EXECUTE_ACCESS_8_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_8_LOG_DENIED_ACCESS_8_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_8_LOG_DENIED_ACCESS_8_OFFSET 16
#define AC_RANGE_CHECK_RANGE_ATTR_8_LOG_DENIED_ACCESS_8_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_8_LOG_DENIED_ACCESS_8_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_8_LOG_DENIED_ACCESS_8_OFFSET })
 
// Attributes of the range.
#define AC_RANGE_CHECK_RANGE_ATTR_9_REG_OFFSET 0x1c4
#define AC_RANGE_CHECK_RANGE_ATTR_9_REG_RESVAL 0x69999u
#define AC_RANGE_CHECK_RANGE_ATTR_9_ENABLE_9_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_9_ENABLE_9_OFFSET 0
#define AC_RANGE_CHECK_RANGE_ATTR_9_ENABLE_9_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_9_ENABLE_9_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_9_ENABLE_9_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_9_READ_ACCESS_9_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_9_READ_ACCESS_9_OFFSET 4
#define AC_RANGE_CHECK_RANGE_ATTR_9_READ_ACCESS_9_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_9_READ_ACCESS_9_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_9_READ_ACCESS_9_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_9_WRITE_ACCESS_9_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_9_WRITE_ACCESS_9_OFFSET 8
#define AC_RANGE_CHECK_RANGE_ATTR_9_WRITE_ACCESS_9_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_9_WRITE_ACCESS_9_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_9_WRITE_ACCESS_9_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_9_EXECUTE_ACCESS_9_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_9_EXECUTE_ACCESS_9_OFFSET 12
#define AC_RANGE_CHECK_RANGE_ATTR_9_EXECUTE_ACCESS_9_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_9_EXECUTE_ACCESS_9_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_9_EXECUTE_ACCESS_9_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_9_LOG_DENIED_ACCESS_9_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_9_LOG_DENIED_ACCESS_9_OFFSET 16
#define AC_RANGE_CHECK_RANGE_ATTR_9_LOG_DENIED_ACCESS_9_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_9_LOG_DENIED_ACCESS_9_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_9_LOG_DENIED_ACCESS_9_OFFSET })
 
// Attributes of the range.
#define AC_RANGE_CHECK_RANGE_ATTR_10_REG_OFFSET 0x1c8
#define AC_RANGE_CHECK_RANGE_ATTR_10_REG_RESVAL 0x69999u
#define AC_RANGE_CHECK_RANGE_ATTR_10_ENABLE_10_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_10_ENABLE_10_OFFSET 0
#define AC_RANGE_CHECK_RANGE_ATTR_10_ENABLE_10_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_10_ENABLE_10_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_10_ENABLE_10_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_10_READ_ACCESS_10_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_10_READ_ACCESS_10_OFFSET 4
#define AC_RANGE_CHECK_RANGE_ATTR_10_READ_ACCESS_10_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_10_READ_ACCESS_10_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_10_READ_ACCESS_10_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_10_WRITE_ACCESS_10_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_10_WRITE_ACCESS_10_OFFSET 8
#define AC_RANGE_CHECK_RANGE_ATTR_10_WRITE_ACCESS_10_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_10_WRITE_ACCESS_10_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_10_WRITE_ACCESS_10_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_10_EXECUTE_ACCESS_10_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_10_EXECUTE_ACCESS_10_OFFSET 12
#define AC_RANGE_CHECK_RANGE_ATTR_10_EXECUTE_ACCESS_10_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_10_EXECUTE_ACCESS_10_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_10_EXECUTE_ACCESS_10_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_10_LOG_DENIED_ACCESS_10_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_10_LOG_DENIED_ACCESS_10_OFFSET 16
#define AC_RANGE_CHECK_RANGE_ATTR_10_LOG_DENIED_ACCESS_10_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_10_LOG_DENIED_ACCESS_10_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_10_LOG_DENIED_ACCESS_10_OFFSET })
 
// Attributes of the range.
#define AC_RANGE_CHECK_RANGE_ATTR_11_REG_OFFSET 0x1cc
#define AC_RANGE_CHECK_RANGE_ATTR_11_REG_RESVAL 0x69999u
#define AC_RANGE_CHECK_RANGE_ATTR_11_ENABLE_11_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_11_ENABLE_11_OFFSET 0
#define AC_RANGE_CHECK_RANGE_ATTR_11_ENABLE_11_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_11_ENABLE_11_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_11_ENABLE_11_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_11_READ_ACCESS_11_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_11_READ_ACCESS_11_OFFSET 4
#define AC_RANGE_CHECK_RANGE_ATTR_11_READ_ACCESS_11_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_11_READ_ACCESS_11_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_11_READ_ACCESS_11_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_11_WRITE_ACCESS_11_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_11_WRITE_ACCESS_11_OFFSET 8
#define AC_RANGE_CHECK_RANGE_ATTR_11_WRITE_ACCESS_11_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_11_WRITE_ACCESS_11_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_11_WRITE_ACCESS_11_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_11_EXECUTE_ACCESS_11_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_11_EXECUTE_ACCESS_11_OFFSET 12
#define AC_RANGE_CHECK_RANGE_ATTR_11_EXECUTE_ACCESS_11_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_11_EXECUTE_ACCESS_11_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_11_EXECUTE_ACCESS_11_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_11_LOG_DENIED_ACCESS_11_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_11_LOG_DENIED_ACCESS_11_OFFSET 16
#define AC_RANGE_CHECK_RANGE_ATTR_11_LOG_DENIED_ACCESS_11_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_11_LOG_DENIED_ACCESS_11_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_11_LOG_DENIED_ACCESS_11_OFFSET })
 
// Attributes of the range.
#define AC_RANGE_CHECK_RANGE_ATTR_12_REG_OFFSET 0x1d0
#define AC_RANGE_CHECK_RANGE_ATTR_12_REG_RESVAL 0x69999u
#define AC_RANGE_CHECK_RANGE_ATTR_12_ENABLE_12_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_12_ENABLE_12_OFFSET 0
#define AC_RANGE_CHECK_RANGE_ATTR_12_ENABLE_12_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_12_ENABLE_12_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_12_ENABLE_12_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_12_READ_ACCESS_12_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_12_READ_ACCESS_12_OFFSET 4
#define AC_RANGE_CHECK_RANGE_ATTR_12_READ_ACCESS_12_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_12_READ_ACCESS_12_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_12_READ_ACCESS_12_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_12_WRITE_ACCESS_12_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_12_WRITE_ACCESS_12_OFFSET 8
#define AC_RANGE_CHECK_RANGE_ATTR_12_WRITE_ACCESS_12_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_12_WRITE_ACCESS_12_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_12_WRITE_ACCESS_12_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_12_EXECUTE_ACCESS_12_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_12_EXECUTE_ACCESS_12_OFFSET 12
#define AC_RANGE_CHECK_RANGE_ATTR_12_EXECUTE_ACCESS_12_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_12_EXECUTE_ACCESS_12_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_12_EXECUTE_ACCESS_12_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_12_LOG_DENIED_ACCESS_12_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_12_LOG_DENIED_ACCESS_12_OFFSET 16
#define AC_RANGE_CHECK_RANGE_ATTR_12_LOG_DENIED_ACCESS_12_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_12_LOG_DENIED_ACCESS_12_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_12_LOG_DENIED_ACCESS_12_OFFSET })
 
// Attributes of the range.
#define AC_RANGE_CHECK_RANGE_ATTR_13_REG_OFFSET 0x1d4
#define AC_RANGE_CHECK_RANGE_ATTR_13_REG_RESVAL 0x69999u
#define AC_RANGE_CHECK_RANGE_ATTR_13_ENABLE_13_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_13_ENABLE_13_OFFSET 0
#define AC_RANGE_CHECK_RANGE_ATTR_13_ENABLE_13_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_13_ENABLE_13_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_13_ENABLE_13_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_13_READ_ACCESS_13_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_13_READ_ACCESS_13_OFFSET 4
#define AC_RANGE_CHECK_RANGE_ATTR_13_READ_ACCESS_13_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_13_READ_ACCESS_13_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_13_READ_ACCESS_13_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_13_WRITE_ACCESS_13_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_13_WRITE_ACCESS_13_OFFSET 8
#define AC_RANGE_CHECK_RANGE_ATTR_13_WRITE_ACCESS_13_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_13_WRITE_ACCESS_13_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_13_WRITE_ACCESS_13_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_13_EXECUTE_ACCESS_13_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_13_EXECUTE_ACCESS_13_OFFSET 12
#define AC_RANGE_CHECK_RANGE_ATTR_13_EXECUTE_ACCESS_13_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_13_EXECUTE_ACCESS_13_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_13_EXECUTE_ACCESS_13_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_13_LOG_DENIED_ACCESS_13_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_13_LOG_DENIED_ACCESS_13_OFFSET 16
#define AC_RANGE_CHECK_RANGE_ATTR_13_LOG_DENIED_ACCESS_13_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_13_LOG_DENIED_ACCESS_13_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_13_LOG_DENIED_ACCESS_13_OFFSET })
 
// Attributes of the range.
#define AC_RANGE_CHECK_RANGE_ATTR_14_REG_OFFSET 0x1d8
#define AC_RANGE_CHECK_RANGE_ATTR_14_REG_RESVAL 0x69999u
#define AC_RANGE_CHECK_RANGE_ATTR_14_ENABLE_14_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_14_ENABLE_14_OFFSET 0
#define AC_RANGE_CHECK_RANGE_ATTR_14_ENABLE_14_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_14_ENABLE_14_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_14_ENABLE_14_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_14_READ_ACCESS_14_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_14_READ_ACCESS_14_OFFSET 4
#define AC_RANGE_CHECK_RANGE_ATTR_14_READ_ACCESS_14_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_14_READ_ACCESS_14_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_14_READ_ACCESS_14_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_14_WRITE_ACCESS_14_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_14_WRITE_ACCESS_14_OFFSET 8
#define AC_RANGE_CHECK_RANGE_ATTR_14_WRITE_ACCESS_14_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_14_WRITE_ACCESS_14_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_14_WRITE_ACCESS_14_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_14_EXECUTE_ACCESS_14_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_14_EXECUTE_ACCESS_14_OFFSET 12
#define AC_RANGE_CHECK_RANGE_ATTR_14_EXECUTE_ACCESS_14_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_14_EXECUTE_ACCESS_14_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_14_EXECUTE_ACCESS_14_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_14_LOG_DENIED_ACCESS_14_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_14_LOG_DENIED_ACCESS_14_OFFSET 16
#define AC_RANGE_CHECK_RANGE_ATTR_14_LOG_DENIED_ACCESS_14_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_14_LOG_DENIED_ACCESS_14_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_14_LOG_DENIED_ACCESS_14_OFFSET })
 
// Attributes of the range.
#define AC_RANGE_CHECK_RANGE_ATTR_15_REG_OFFSET 0x1dc
#define AC_RANGE_CHECK_RANGE_ATTR_15_REG_RESVAL 0x69999u
#define AC_RANGE_CHECK_RANGE_ATTR_15_ENABLE_15_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_15_ENABLE_15_OFFSET 0
#define AC_RANGE_CHECK_RANGE_ATTR_15_ENABLE_15_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_15_ENABLE_15_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_15_ENABLE_15_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_15_READ_ACCESS_15_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_15_READ_ACCESS_15_OFFSET 4
#define AC_RANGE_CHECK_RANGE_ATTR_15_READ_ACCESS_15_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_15_READ_ACCESS_15_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_15_READ_ACCESS_15_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_15_WRITE_ACCESS_15_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_15_WRITE_ACCESS_15_OFFSET 8
#define AC_RANGE_CHECK_RANGE_ATTR_15_WRITE_ACCESS_15_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_15_WRITE_ACCESS_15_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_15_WRITE_ACCESS_15_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_15_EXECUTE_ACCESS_15_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_15_EXECUTE_ACCESS_15_OFFSET 12
#define AC_RANGE_CHECK_RANGE_ATTR_15_EXECUTE_ACCESS_15_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_15_EXECUTE_ACCESS_15_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_15_EXECUTE_ACCESS_15_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_15_LOG_DENIED_ACCESS_15_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_15_LOG_DENIED_ACCESS_15_OFFSET 16
#define AC_RANGE_CHECK_RANGE_ATTR_15_LOG_DENIED_ACCESS_15_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_15_LOG_DENIED_ACCESS_15_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_15_LOG_DENIED_ACCESS_15_OFFSET })
 
// Attributes of the range.
#define AC_RANGE_CHECK_RANGE_ATTR_16_REG_OFFSET 0x1e0
#define AC_RANGE_CHECK_RANGE_ATTR_16_REG_RESVAL 0x69999u
#define AC_RANGE_CHECK_RANGE_ATTR_16_ENABLE_16_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_16_ENABLE_16_OFFSET 0
#define AC_RANGE_CHECK_RANGE_ATTR_16_ENABLE_16_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_16_ENABLE_16_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_16_ENABLE_16_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_16_READ_ACCESS_16_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_16_READ_ACCESS_16_OFFSET 4
#define AC_RANGE_CHECK_RANGE_ATTR_16_READ_ACCESS_16_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_16_READ_ACCESS_16_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_16_READ_ACCESS_16_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_16_WRITE_ACCESS_16_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_16_WRITE_ACCESS_16_OFFSET 8
#define AC_RANGE_CHECK_RANGE_ATTR_16_WRITE_ACCESS_16_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_16_WRITE_ACCESS_16_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_16_WRITE_ACCESS_16_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_16_EXECUTE_ACCESS_16_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_16_EXECUTE_ACCESS_16_OFFSET 12
#define AC_RANGE_CHECK_RANGE_ATTR_16_EXECUTE_ACCESS_16_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_16_EXECUTE_ACCESS_16_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_16_EXECUTE_ACCESS_16_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_16_LOG_DENIED_ACCESS_16_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_16_LOG_DENIED_ACCESS_16_OFFSET 16
#define AC_RANGE_CHECK_RANGE_ATTR_16_LOG_DENIED_ACCESS_16_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_16_LOG_DENIED_ACCESS_16_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_16_LOG_DENIED_ACCESS_16_OFFSET })
 
// Attributes of the range.
#define AC_RANGE_CHECK_RANGE_ATTR_17_REG_OFFSET 0x1e4
#define AC_RANGE_CHECK_RANGE_ATTR_17_REG_RESVAL 0x69999u
#define AC_RANGE_CHECK_RANGE_ATTR_17_ENABLE_17_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_17_ENABLE_17_OFFSET 0
#define AC_RANGE_CHECK_RANGE_ATTR_17_ENABLE_17_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_17_ENABLE_17_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_17_ENABLE_17_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_17_READ_ACCESS_17_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_17_READ_ACCESS_17_OFFSET 4
#define AC_RANGE_CHECK_RANGE_ATTR_17_READ_ACCESS_17_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_17_READ_ACCESS_17_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_17_READ_ACCESS_17_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_17_WRITE_ACCESS_17_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_17_WRITE_ACCESS_17_OFFSET 8
#define AC_RANGE_CHECK_RANGE_ATTR_17_WRITE_ACCESS_17_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_17_WRITE_ACCESS_17_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_17_WRITE_ACCESS_17_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_17_EXECUTE_ACCESS_17_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_17_EXECUTE_ACCESS_17_OFFSET 12
#define AC_RANGE_CHECK_RANGE_ATTR_17_EXECUTE_ACCESS_17_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_17_EXECUTE_ACCESS_17_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_17_EXECUTE_ACCESS_17_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_17_LOG_DENIED_ACCESS_17_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_17_LOG_DENIED_ACCESS_17_OFFSET 16
#define AC_RANGE_CHECK_RANGE_ATTR_17_LOG_DENIED_ACCESS_17_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_17_LOG_DENIED_ACCESS_17_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_17_LOG_DENIED_ACCESS_17_OFFSET })
 
// Attributes of the range.
#define AC_RANGE_CHECK_RANGE_ATTR_18_REG_OFFSET 0x1e8
#define AC_RANGE_CHECK_RANGE_ATTR_18_REG_RESVAL 0x69999u
#define AC_RANGE_CHECK_RANGE_ATTR_18_ENABLE_18_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_18_ENABLE_18_OFFSET 0
#define AC_RANGE_CHECK_RANGE_ATTR_18_ENABLE_18_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_18_ENABLE_18_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_18_ENABLE_18_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_18_READ_ACCESS_18_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_18_READ_ACCESS_18_OFFSET 4
#define AC_RANGE_CHECK_RANGE_ATTR_18_READ_ACCESS_18_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_18_READ_ACCESS_18_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_18_READ_ACCESS_18_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_18_WRITE_ACCESS_18_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_18_WRITE_ACCESS_18_OFFSET 8
#define AC_RANGE_CHECK_RANGE_ATTR_18_WRITE_ACCESS_18_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_18_WRITE_ACCESS_18_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_18_WRITE_ACCESS_18_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_18_EXECUTE_ACCESS_18_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_18_EXECUTE_ACCESS_18_OFFSET 12
#define AC_RANGE_CHECK_RANGE_ATTR_18_EXECUTE_ACCESS_18_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_18_EXECUTE_ACCESS_18_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_18_EXECUTE_ACCESS_18_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_18_LOG_DENIED_ACCESS_18_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_18_LOG_DENIED_ACCESS_18_OFFSET 16
#define AC_RANGE_CHECK_RANGE_ATTR_18_LOG_DENIED_ACCESS_18_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_18_LOG_DENIED_ACCESS_18_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_18_LOG_DENIED_ACCESS_18_OFFSET })
 
// Attributes of the range.
#define AC_RANGE_CHECK_RANGE_ATTR_19_REG_OFFSET 0x1ec
#define AC_RANGE_CHECK_RANGE_ATTR_19_REG_RESVAL 0x69999u
#define AC_RANGE_CHECK_RANGE_ATTR_19_ENABLE_19_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_19_ENABLE_19_OFFSET 0
#define AC_RANGE_CHECK_RANGE_ATTR_19_ENABLE_19_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_19_ENABLE_19_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_19_ENABLE_19_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_19_READ_ACCESS_19_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_19_READ_ACCESS_19_OFFSET 4
#define AC_RANGE_CHECK_RANGE_ATTR_19_READ_ACCESS_19_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_19_READ_ACCESS_19_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_19_READ_ACCESS_19_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_19_WRITE_ACCESS_19_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_19_WRITE_ACCESS_19_OFFSET 8
#define AC_RANGE_CHECK_RANGE_ATTR_19_WRITE_ACCESS_19_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_19_WRITE_ACCESS_19_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_19_WRITE_ACCESS_19_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_19_EXECUTE_ACCESS_19_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_19_EXECUTE_ACCESS_19_OFFSET 12
#define AC_RANGE_CHECK_RANGE_ATTR_19_EXECUTE_ACCESS_19_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_19_EXECUTE_ACCESS_19_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_19_EXECUTE_ACCESS_19_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_19_LOG_DENIED_ACCESS_19_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_19_LOG_DENIED_ACCESS_19_OFFSET 16
#define AC_RANGE_CHECK_RANGE_ATTR_19_LOG_DENIED_ACCESS_19_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_19_LOG_DENIED_ACCESS_19_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_19_LOG_DENIED_ACCESS_19_OFFSET })
 
// Attributes of the range.
#define AC_RANGE_CHECK_RANGE_ATTR_20_REG_OFFSET 0x1f0
#define AC_RANGE_CHECK_RANGE_ATTR_20_REG_RESVAL 0x69999u
#define AC_RANGE_CHECK_RANGE_ATTR_20_ENABLE_20_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_20_ENABLE_20_OFFSET 0
#define AC_RANGE_CHECK_RANGE_ATTR_20_ENABLE_20_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_20_ENABLE_20_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_20_ENABLE_20_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_20_READ_ACCESS_20_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_20_READ_ACCESS_20_OFFSET 4
#define AC_RANGE_CHECK_RANGE_ATTR_20_READ_ACCESS_20_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_20_READ_ACCESS_20_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_20_READ_ACCESS_20_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_20_WRITE_ACCESS_20_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_20_WRITE_ACCESS_20_OFFSET 8
#define AC_RANGE_CHECK_RANGE_ATTR_20_WRITE_ACCESS_20_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_20_WRITE_ACCESS_20_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_20_WRITE_ACCESS_20_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_20_EXECUTE_ACCESS_20_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_20_EXECUTE_ACCESS_20_OFFSET 12
#define AC_RANGE_CHECK_RANGE_ATTR_20_EXECUTE_ACCESS_20_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_20_EXECUTE_ACCESS_20_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_20_EXECUTE_ACCESS_20_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_20_LOG_DENIED_ACCESS_20_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_20_LOG_DENIED_ACCESS_20_OFFSET 16
#define AC_RANGE_CHECK_RANGE_ATTR_20_LOG_DENIED_ACCESS_20_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_20_LOG_DENIED_ACCESS_20_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_20_LOG_DENIED_ACCESS_20_OFFSET })
 
// Attributes of the range.
#define AC_RANGE_CHECK_RANGE_ATTR_21_REG_OFFSET 0x1f4
#define AC_RANGE_CHECK_RANGE_ATTR_21_REG_RESVAL 0x69999u
#define AC_RANGE_CHECK_RANGE_ATTR_21_ENABLE_21_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_21_ENABLE_21_OFFSET 0
#define AC_RANGE_CHECK_RANGE_ATTR_21_ENABLE_21_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_21_ENABLE_21_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_21_ENABLE_21_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_21_READ_ACCESS_21_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_21_READ_ACCESS_21_OFFSET 4
#define AC_RANGE_CHECK_RANGE_ATTR_21_READ_ACCESS_21_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_21_READ_ACCESS_21_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_21_READ_ACCESS_21_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_21_WRITE_ACCESS_21_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_21_WRITE_ACCESS_21_OFFSET 8
#define AC_RANGE_CHECK_RANGE_ATTR_21_WRITE_ACCESS_21_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_21_WRITE_ACCESS_21_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_21_WRITE_ACCESS_21_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_21_EXECUTE_ACCESS_21_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_21_EXECUTE_ACCESS_21_OFFSET 12
#define AC_RANGE_CHECK_RANGE_ATTR_21_EXECUTE_ACCESS_21_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_21_EXECUTE_ACCESS_21_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_21_EXECUTE_ACCESS_21_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_21_LOG_DENIED_ACCESS_21_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_21_LOG_DENIED_ACCESS_21_OFFSET 16
#define AC_RANGE_CHECK_RANGE_ATTR_21_LOG_DENIED_ACCESS_21_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_21_LOG_DENIED_ACCESS_21_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_21_LOG_DENIED_ACCESS_21_OFFSET })
 
// Attributes of the range.
#define AC_RANGE_CHECK_RANGE_ATTR_22_REG_OFFSET 0x1f8
#define AC_RANGE_CHECK_RANGE_ATTR_22_REG_RESVAL 0x69999u
#define AC_RANGE_CHECK_RANGE_ATTR_22_ENABLE_22_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_22_ENABLE_22_OFFSET 0
#define AC_RANGE_CHECK_RANGE_ATTR_22_ENABLE_22_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_22_ENABLE_22_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_22_ENABLE_22_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_22_READ_ACCESS_22_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_22_READ_ACCESS_22_OFFSET 4
#define AC_RANGE_CHECK_RANGE_ATTR_22_READ_ACCESS_22_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_22_READ_ACCESS_22_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_22_READ_ACCESS_22_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_22_WRITE_ACCESS_22_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_22_WRITE_ACCESS_22_OFFSET 8
#define AC_RANGE_CHECK_RANGE_ATTR_22_WRITE_ACCESS_22_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_22_WRITE_ACCESS_22_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_22_WRITE_ACCESS_22_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_22_EXECUTE_ACCESS_22_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_22_EXECUTE_ACCESS_22_OFFSET 12
#define AC_RANGE_CHECK_RANGE_ATTR_22_EXECUTE_ACCESS_22_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_22_EXECUTE_ACCESS_22_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_22_EXECUTE_ACCESS_22_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_22_LOG_DENIED_ACCESS_22_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_22_LOG_DENIED_ACCESS_22_OFFSET 16
#define AC_RANGE_CHECK_RANGE_ATTR_22_LOG_DENIED_ACCESS_22_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_22_LOG_DENIED_ACCESS_22_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_22_LOG_DENIED_ACCESS_22_OFFSET })
 
// Attributes of the range.
#define AC_RANGE_CHECK_RANGE_ATTR_23_REG_OFFSET 0x1fc
#define AC_RANGE_CHECK_RANGE_ATTR_23_REG_RESVAL 0x69999u
#define AC_RANGE_CHECK_RANGE_ATTR_23_ENABLE_23_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_23_ENABLE_23_OFFSET 0
#define AC_RANGE_CHECK_RANGE_ATTR_23_ENABLE_23_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_23_ENABLE_23_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_23_ENABLE_23_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_23_READ_ACCESS_23_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_23_READ_ACCESS_23_OFFSET 4
#define AC_RANGE_CHECK_RANGE_ATTR_23_READ_ACCESS_23_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_23_READ_ACCESS_23_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_23_READ_ACCESS_23_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_23_WRITE_ACCESS_23_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_23_WRITE_ACCESS_23_OFFSET 8
#define AC_RANGE_CHECK_RANGE_ATTR_23_WRITE_ACCESS_23_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_23_WRITE_ACCESS_23_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_23_WRITE_ACCESS_23_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_23_EXECUTE_ACCESS_23_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_23_EXECUTE_ACCESS_23_OFFSET 12
#define AC_RANGE_CHECK_RANGE_ATTR_23_EXECUTE_ACCESS_23_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_23_EXECUTE_ACCESS_23_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_23_EXECUTE_ACCESS_23_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_23_LOG_DENIED_ACCESS_23_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_23_LOG_DENIED_ACCESS_23_OFFSET 16
#define AC_RANGE_CHECK_RANGE_ATTR_23_LOG_DENIED_ACCESS_23_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_23_LOG_DENIED_ACCESS_23_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_23_LOG_DENIED_ACCESS_23_OFFSET })
 
// Attributes of the range.
#define AC_RANGE_CHECK_RANGE_ATTR_24_REG_OFFSET 0x200
#define AC_RANGE_CHECK_RANGE_ATTR_24_REG_RESVAL 0x69999u
#define AC_RANGE_CHECK_RANGE_ATTR_24_ENABLE_24_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_24_ENABLE_24_OFFSET 0
#define AC_RANGE_CHECK_RANGE_ATTR_24_ENABLE_24_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_24_ENABLE_24_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_24_ENABLE_24_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_24_READ_ACCESS_24_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_24_READ_ACCESS_24_OFFSET 4
#define AC_RANGE_CHECK_RANGE_ATTR_24_READ_ACCESS_24_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_24_READ_ACCESS_24_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_24_READ_ACCESS_24_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_24_WRITE_ACCESS_24_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_24_WRITE_ACCESS_24_OFFSET 8
#define AC_RANGE_CHECK_RANGE_ATTR_24_WRITE_ACCESS_24_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_24_WRITE_ACCESS_24_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_24_WRITE_ACCESS_24_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_24_EXECUTE_ACCESS_24_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_24_EXECUTE_ACCESS_24_OFFSET 12
#define AC_RANGE_CHECK_RANGE_ATTR_24_EXECUTE_ACCESS_24_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_24_EXECUTE_ACCESS_24_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_24_EXECUTE_ACCESS_24_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_24_LOG_DENIED_ACCESS_24_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_24_LOG_DENIED_ACCESS_24_OFFSET 16
#define AC_RANGE_CHECK_RANGE_ATTR_24_LOG_DENIED_ACCESS_24_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_24_LOG_DENIED_ACCESS_24_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_24_LOG_DENIED_ACCESS_24_OFFSET })
 
// Attributes of the range.
#define AC_RANGE_CHECK_RANGE_ATTR_25_REG_OFFSET 0x204
#define AC_RANGE_CHECK_RANGE_ATTR_25_REG_RESVAL 0x69999u
#define AC_RANGE_CHECK_RANGE_ATTR_25_ENABLE_25_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_25_ENABLE_25_OFFSET 0
#define AC_RANGE_CHECK_RANGE_ATTR_25_ENABLE_25_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_25_ENABLE_25_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_25_ENABLE_25_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_25_READ_ACCESS_25_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_25_READ_ACCESS_25_OFFSET 4
#define AC_RANGE_CHECK_RANGE_ATTR_25_READ_ACCESS_25_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_25_READ_ACCESS_25_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_25_READ_ACCESS_25_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_25_WRITE_ACCESS_25_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_25_WRITE_ACCESS_25_OFFSET 8
#define AC_RANGE_CHECK_RANGE_ATTR_25_WRITE_ACCESS_25_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_25_WRITE_ACCESS_25_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_25_WRITE_ACCESS_25_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_25_EXECUTE_ACCESS_25_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_25_EXECUTE_ACCESS_25_OFFSET 12
#define AC_RANGE_CHECK_RANGE_ATTR_25_EXECUTE_ACCESS_25_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_25_EXECUTE_ACCESS_25_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_25_EXECUTE_ACCESS_25_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_25_LOG_DENIED_ACCESS_25_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_25_LOG_DENIED_ACCESS_25_OFFSET 16
#define AC_RANGE_CHECK_RANGE_ATTR_25_LOG_DENIED_ACCESS_25_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_25_LOG_DENIED_ACCESS_25_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_25_LOG_DENIED_ACCESS_25_OFFSET })
 
// Attributes of the range.
#define AC_RANGE_CHECK_RANGE_ATTR_26_REG_OFFSET 0x208
#define AC_RANGE_CHECK_RANGE_ATTR_26_REG_RESVAL 0x69999u
#define AC_RANGE_CHECK_RANGE_ATTR_26_ENABLE_26_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_26_ENABLE_26_OFFSET 0
#define AC_RANGE_CHECK_RANGE_ATTR_26_ENABLE_26_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_26_ENABLE_26_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_26_ENABLE_26_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_26_READ_ACCESS_26_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_26_READ_ACCESS_26_OFFSET 4
#define AC_RANGE_CHECK_RANGE_ATTR_26_READ_ACCESS_26_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_26_READ_ACCESS_26_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_26_READ_ACCESS_26_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_26_WRITE_ACCESS_26_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_26_WRITE_ACCESS_26_OFFSET 8
#define AC_RANGE_CHECK_RANGE_ATTR_26_WRITE_ACCESS_26_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_26_WRITE_ACCESS_26_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_26_WRITE_ACCESS_26_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_26_EXECUTE_ACCESS_26_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_26_EXECUTE_ACCESS_26_OFFSET 12
#define AC_RANGE_CHECK_RANGE_ATTR_26_EXECUTE_ACCESS_26_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_26_EXECUTE_ACCESS_26_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_26_EXECUTE_ACCESS_26_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_26_LOG_DENIED_ACCESS_26_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_26_LOG_DENIED_ACCESS_26_OFFSET 16
#define AC_RANGE_CHECK_RANGE_ATTR_26_LOG_DENIED_ACCESS_26_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_26_LOG_DENIED_ACCESS_26_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_26_LOG_DENIED_ACCESS_26_OFFSET })
 
// Attributes of the range.
#define AC_RANGE_CHECK_RANGE_ATTR_27_REG_OFFSET 0x20c
#define AC_RANGE_CHECK_RANGE_ATTR_27_REG_RESVAL 0x69999u
#define AC_RANGE_CHECK_RANGE_ATTR_27_ENABLE_27_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_27_ENABLE_27_OFFSET 0
#define AC_RANGE_CHECK_RANGE_ATTR_27_ENABLE_27_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_27_ENABLE_27_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_27_ENABLE_27_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_27_READ_ACCESS_27_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_27_READ_ACCESS_27_OFFSET 4
#define AC_RANGE_CHECK_RANGE_ATTR_27_READ_ACCESS_27_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_27_READ_ACCESS_27_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_27_READ_ACCESS_27_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_27_WRITE_ACCESS_27_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_27_WRITE_ACCESS_27_OFFSET 8
#define AC_RANGE_CHECK_RANGE_ATTR_27_WRITE_ACCESS_27_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_27_WRITE_ACCESS_27_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_27_WRITE_ACCESS_27_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_27_EXECUTE_ACCESS_27_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_27_EXECUTE_ACCESS_27_OFFSET 12
#define AC_RANGE_CHECK_RANGE_ATTR_27_EXECUTE_ACCESS_27_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_27_EXECUTE_ACCESS_27_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_27_EXECUTE_ACCESS_27_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_27_LOG_DENIED_ACCESS_27_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_27_LOG_DENIED_ACCESS_27_OFFSET 16
#define AC_RANGE_CHECK_RANGE_ATTR_27_LOG_DENIED_ACCESS_27_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_27_LOG_DENIED_ACCESS_27_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_27_LOG_DENIED_ACCESS_27_OFFSET })
 
// Attributes of the range.
#define AC_RANGE_CHECK_RANGE_ATTR_28_REG_OFFSET 0x210
#define AC_RANGE_CHECK_RANGE_ATTR_28_REG_RESVAL 0x69999u
#define AC_RANGE_CHECK_RANGE_ATTR_28_ENABLE_28_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_28_ENABLE_28_OFFSET 0
#define AC_RANGE_CHECK_RANGE_ATTR_28_ENABLE_28_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_28_ENABLE_28_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_28_ENABLE_28_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_28_READ_ACCESS_28_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_28_READ_ACCESS_28_OFFSET 4
#define AC_RANGE_CHECK_RANGE_ATTR_28_READ_ACCESS_28_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_28_READ_ACCESS_28_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_28_READ_ACCESS_28_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_28_WRITE_ACCESS_28_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_28_WRITE_ACCESS_28_OFFSET 8
#define AC_RANGE_CHECK_RANGE_ATTR_28_WRITE_ACCESS_28_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_28_WRITE_ACCESS_28_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_28_WRITE_ACCESS_28_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_28_EXECUTE_ACCESS_28_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_28_EXECUTE_ACCESS_28_OFFSET 12
#define AC_RANGE_CHECK_RANGE_ATTR_28_EXECUTE_ACCESS_28_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_28_EXECUTE_ACCESS_28_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_28_EXECUTE_ACCESS_28_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_28_LOG_DENIED_ACCESS_28_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_28_LOG_DENIED_ACCESS_28_OFFSET 16
#define AC_RANGE_CHECK_RANGE_ATTR_28_LOG_DENIED_ACCESS_28_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_28_LOG_DENIED_ACCESS_28_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_28_LOG_DENIED_ACCESS_28_OFFSET })
 
// Attributes of the range.
#define AC_RANGE_CHECK_RANGE_ATTR_29_REG_OFFSET 0x214
#define AC_RANGE_CHECK_RANGE_ATTR_29_REG_RESVAL 0x69999u
#define AC_RANGE_CHECK_RANGE_ATTR_29_ENABLE_29_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_29_ENABLE_29_OFFSET 0
#define AC_RANGE_CHECK_RANGE_ATTR_29_ENABLE_29_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_29_ENABLE_29_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_29_ENABLE_29_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_29_READ_ACCESS_29_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_29_READ_ACCESS_29_OFFSET 4
#define AC_RANGE_CHECK_RANGE_ATTR_29_READ_ACCESS_29_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_29_READ_ACCESS_29_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_29_READ_ACCESS_29_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_29_WRITE_ACCESS_29_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_29_WRITE_ACCESS_29_OFFSET 8
#define AC_RANGE_CHECK_RANGE_ATTR_29_WRITE_ACCESS_29_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_29_WRITE_ACCESS_29_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_29_WRITE_ACCESS_29_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_29_EXECUTE_ACCESS_29_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_29_EXECUTE_ACCESS_29_OFFSET 12
#define AC_RANGE_CHECK_RANGE_ATTR_29_EXECUTE_ACCESS_29_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_29_EXECUTE_ACCESS_29_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_29_EXECUTE_ACCESS_29_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_29_LOG_DENIED_ACCESS_29_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_29_LOG_DENIED_ACCESS_29_OFFSET 16
#define AC_RANGE_CHECK_RANGE_ATTR_29_LOG_DENIED_ACCESS_29_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_29_LOG_DENIED_ACCESS_29_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_29_LOG_DENIED_ACCESS_29_OFFSET })
 
// Attributes of the range.
#define AC_RANGE_CHECK_RANGE_ATTR_30_REG_OFFSET 0x218
#define AC_RANGE_CHECK_RANGE_ATTR_30_REG_RESVAL 0x69999u
#define AC_RANGE_CHECK_RANGE_ATTR_30_ENABLE_30_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_30_ENABLE_30_OFFSET 0
#define AC_RANGE_CHECK_RANGE_ATTR_30_ENABLE_30_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_30_ENABLE_30_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_30_ENABLE_30_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_30_READ_ACCESS_30_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_30_READ_ACCESS_30_OFFSET 4
#define AC_RANGE_CHECK_RANGE_ATTR_30_READ_ACCESS_30_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_30_READ_ACCESS_30_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_30_READ_ACCESS_30_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_30_WRITE_ACCESS_30_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_30_WRITE_ACCESS_30_OFFSET 8
#define AC_RANGE_CHECK_RANGE_ATTR_30_WRITE_ACCESS_30_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_30_WRITE_ACCESS_30_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_30_WRITE_ACCESS_30_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_30_EXECUTE_ACCESS_30_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_30_EXECUTE_ACCESS_30_OFFSET 12
#define AC_RANGE_CHECK_RANGE_ATTR_30_EXECUTE_ACCESS_30_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_30_EXECUTE_ACCESS_30_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_30_EXECUTE_ACCESS_30_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_30_LOG_DENIED_ACCESS_30_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_30_LOG_DENIED_ACCESS_30_OFFSET 16
#define AC_RANGE_CHECK_RANGE_ATTR_30_LOG_DENIED_ACCESS_30_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_30_LOG_DENIED_ACCESS_30_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_30_LOG_DENIED_ACCESS_30_OFFSET })
 
// Attributes of the range.
#define AC_RANGE_CHECK_RANGE_ATTR_31_REG_OFFSET 0x21c
#define AC_RANGE_CHECK_RANGE_ATTR_31_REG_RESVAL 0x69999u
#define AC_RANGE_CHECK_RANGE_ATTR_31_ENABLE_31_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_31_ENABLE_31_OFFSET 0
#define AC_RANGE_CHECK_RANGE_ATTR_31_ENABLE_31_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_31_ENABLE_31_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_31_ENABLE_31_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_31_READ_ACCESS_31_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_31_READ_ACCESS_31_OFFSET 4
#define AC_RANGE_CHECK_RANGE_ATTR_31_READ_ACCESS_31_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_31_READ_ACCESS_31_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_31_READ_ACCESS_31_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_31_WRITE_ACCESS_31_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_31_WRITE_ACCESS_31_OFFSET 8
#define AC_RANGE_CHECK_RANGE_ATTR_31_WRITE_ACCESS_31_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_31_WRITE_ACCESS_31_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_31_WRITE_ACCESS_31_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_31_EXECUTE_ACCESS_31_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_31_EXECUTE_ACCESS_31_OFFSET 12
#define AC_RANGE_CHECK_RANGE_ATTR_31_EXECUTE_ACCESS_31_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_31_EXECUTE_ACCESS_31_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_31_EXECUTE_ACCESS_31_OFFSET })
#define AC_RANGE_CHECK_RANGE_ATTR_31_LOG_DENIED_ACCESS_31_MASK 0xfu
#define AC_RANGE_CHECK_RANGE_ATTR_31_LOG_DENIED_ACCESS_31_OFFSET 16
#define AC_RANGE_CHECK_RANGE_ATTR_31_LOG_DENIED_ACCESS_31_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_ATTR_31_LOG_DENIED_ACCESS_31_MASK, .index = AC_RANGE_CHECK_RANGE_ATTR_31_LOG_DENIED_ACCESS_31_OFFSET })
 
// The RACL policy register allows the system to further restrict the access
// to specific source roles.
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_READ_PERM_FIELD_WIDTH 16
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_WRITE_PERM_FIELD_WIDTH 16
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_MULTIREG_COUNT 32
 
// The RACL policy register allows the system to further restrict the access
// to specific source roles.
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_0_REG_OFFSET 0x220
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_0_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_0_READ_PERM_0_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_0_READ_PERM_0_OFFSET 0
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_0_READ_PERM_0_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_0_READ_PERM_0_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_0_READ_PERM_0_OFFSET })
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_0_WRITE_PERM_0_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_0_WRITE_PERM_0_OFFSET 16
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_0_WRITE_PERM_0_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_0_WRITE_PERM_0_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_0_WRITE_PERM_0_OFFSET })
 
// The RACL policy register allows the system to further restrict the access
// to specific source roles.
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_1_REG_OFFSET 0x224
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_1_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_1_READ_PERM_1_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_1_READ_PERM_1_OFFSET 0
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_1_READ_PERM_1_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_1_READ_PERM_1_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_1_READ_PERM_1_OFFSET })
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_1_WRITE_PERM_1_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_1_WRITE_PERM_1_OFFSET 16
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_1_WRITE_PERM_1_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_1_WRITE_PERM_1_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_1_WRITE_PERM_1_OFFSET })
 
// The RACL policy register allows the system to further restrict the access
// to specific source roles.
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_2_REG_OFFSET 0x228
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_2_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_2_READ_PERM_2_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_2_READ_PERM_2_OFFSET 0
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_2_READ_PERM_2_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_2_READ_PERM_2_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_2_READ_PERM_2_OFFSET })
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_2_WRITE_PERM_2_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_2_WRITE_PERM_2_OFFSET 16
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_2_WRITE_PERM_2_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_2_WRITE_PERM_2_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_2_WRITE_PERM_2_OFFSET })
 
// The RACL policy register allows the system to further restrict the access
// to specific source roles.
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_3_REG_OFFSET 0x22c
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_3_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_3_READ_PERM_3_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_3_READ_PERM_3_OFFSET 0
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_3_READ_PERM_3_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_3_READ_PERM_3_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_3_READ_PERM_3_OFFSET })
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_3_WRITE_PERM_3_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_3_WRITE_PERM_3_OFFSET 16
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_3_WRITE_PERM_3_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_3_WRITE_PERM_3_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_3_WRITE_PERM_3_OFFSET })
 
// The RACL policy register allows the system to further restrict the access
// to specific source roles.
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_4_REG_OFFSET 0x230
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_4_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_4_READ_PERM_4_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_4_READ_PERM_4_OFFSET 0
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_4_READ_PERM_4_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_4_READ_PERM_4_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_4_READ_PERM_4_OFFSET })
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_4_WRITE_PERM_4_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_4_WRITE_PERM_4_OFFSET 16
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_4_WRITE_PERM_4_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_4_WRITE_PERM_4_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_4_WRITE_PERM_4_OFFSET })
 
// The RACL policy register allows the system to further restrict the access
// to specific source roles.
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_5_REG_OFFSET 0x234
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_5_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_5_READ_PERM_5_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_5_READ_PERM_5_OFFSET 0
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_5_READ_PERM_5_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_5_READ_PERM_5_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_5_READ_PERM_5_OFFSET })
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_5_WRITE_PERM_5_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_5_WRITE_PERM_5_OFFSET 16
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_5_WRITE_PERM_5_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_5_WRITE_PERM_5_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_5_WRITE_PERM_5_OFFSET })
 
// The RACL policy register allows the system to further restrict the access
// to specific source roles.
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_6_REG_OFFSET 0x238
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_6_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_6_READ_PERM_6_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_6_READ_PERM_6_OFFSET 0
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_6_READ_PERM_6_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_6_READ_PERM_6_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_6_READ_PERM_6_OFFSET })
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_6_WRITE_PERM_6_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_6_WRITE_PERM_6_OFFSET 16
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_6_WRITE_PERM_6_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_6_WRITE_PERM_6_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_6_WRITE_PERM_6_OFFSET })
 
// The RACL policy register allows the system to further restrict the access
// to specific source roles.
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_7_REG_OFFSET 0x23c
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_7_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_7_READ_PERM_7_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_7_READ_PERM_7_OFFSET 0
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_7_READ_PERM_7_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_7_READ_PERM_7_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_7_READ_PERM_7_OFFSET })
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_7_WRITE_PERM_7_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_7_WRITE_PERM_7_OFFSET 16
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_7_WRITE_PERM_7_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_7_WRITE_PERM_7_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_7_WRITE_PERM_7_OFFSET })
 
// The RACL policy register allows the system to further restrict the access
// to specific source roles.
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_8_REG_OFFSET 0x240
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_8_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_8_READ_PERM_8_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_8_READ_PERM_8_OFFSET 0
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_8_READ_PERM_8_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_8_READ_PERM_8_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_8_READ_PERM_8_OFFSET })
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_8_WRITE_PERM_8_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_8_WRITE_PERM_8_OFFSET 16
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_8_WRITE_PERM_8_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_8_WRITE_PERM_8_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_8_WRITE_PERM_8_OFFSET })
 
// The RACL policy register allows the system to further restrict the access
// to specific source roles.
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_9_REG_OFFSET 0x244
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_9_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_9_READ_PERM_9_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_9_READ_PERM_9_OFFSET 0
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_9_READ_PERM_9_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_9_READ_PERM_9_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_9_READ_PERM_9_OFFSET })
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_9_WRITE_PERM_9_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_9_WRITE_PERM_9_OFFSET 16
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_9_WRITE_PERM_9_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_9_WRITE_PERM_9_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_9_WRITE_PERM_9_OFFSET })
 
// The RACL policy register allows the system to further restrict the access
// to specific source roles.
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_10_REG_OFFSET 0x248
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_10_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_10_READ_PERM_10_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_10_READ_PERM_10_OFFSET 0
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_10_READ_PERM_10_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_10_READ_PERM_10_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_10_READ_PERM_10_OFFSET })
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_10_WRITE_PERM_10_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_10_WRITE_PERM_10_OFFSET 16
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_10_WRITE_PERM_10_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_10_WRITE_PERM_10_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_10_WRITE_PERM_10_OFFSET })
 
// The RACL policy register allows the system to further restrict the access
// to specific source roles.
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_11_REG_OFFSET 0x24c
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_11_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_11_READ_PERM_11_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_11_READ_PERM_11_OFFSET 0
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_11_READ_PERM_11_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_11_READ_PERM_11_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_11_READ_PERM_11_OFFSET })
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_11_WRITE_PERM_11_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_11_WRITE_PERM_11_OFFSET 16
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_11_WRITE_PERM_11_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_11_WRITE_PERM_11_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_11_WRITE_PERM_11_OFFSET })
 
// The RACL policy register allows the system to further restrict the access
// to specific source roles.
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_12_REG_OFFSET 0x250
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_12_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_12_READ_PERM_12_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_12_READ_PERM_12_OFFSET 0
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_12_READ_PERM_12_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_12_READ_PERM_12_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_12_READ_PERM_12_OFFSET })
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_12_WRITE_PERM_12_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_12_WRITE_PERM_12_OFFSET 16
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_12_WRITE_PERM_12_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_12_WRITE_PERM_12_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_12_WRITE_PERM_12_OFFSET })
 
// The RACL policy register allows the system to further restrict the access
// to specific source roles.
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_13_REG_OFFSET 0x254
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_13_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_13_READ_PERM_13_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_13_READ_PERM_13_OFFSET 0
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_13_READ_PERM_13_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_13_READ_PERM_13_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_13_READ_PERM_13_OFFSET })
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_13_WRITE_PERM_13_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_13_WRITE_PERM_13_OFFSET 16
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_13_WRITE_PERM_13_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_13_WRITE_PERM_13_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_13_WRITE_PERM_13_OFFSET })
 
// The RACL policy register allows the system to further restrict the access
// to specific source roles.
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_14_REG_OFFSET 0x258
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_14_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_14_READ_PERM_14_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_14_READ_PERM_14_OFFSET 0
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_14_READ_PERM_14_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_14_READ_PERM_14_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_14_READ_PERM_14_OFFSET })
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_14_WRITE_PERM_14_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_14_WRITE_PERM_14_OFFSET 16
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_14_WRITE_PERM_14_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_14_WRITE_PERM_14_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_14_WRITE_PERM_14_OFFSET })
 
// The RACL policy register allows the system to further restrict the access
// to specific source roles.
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_15_REG_OFFSET 0x25c
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_15_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_15_READ_PERM_15_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_15_READ_PERM_15_OFFSET 0
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_15_READ_PERM_15_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_15_READ_PERM_15_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_15_READ_PERM_15_OFFSET })
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_15_WRITE_PERM_15_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_15_WRITE_PERM_15_OFFSET 16
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_15_WRITE_PERM_15_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_15_WRITE_PERM_15_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_15_WRITE_PERM_15_OFFSET })
 
// The RACL policy register allows the system to further restrict the access
// to specific source roles.
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_16_REG_OFFSET 0x260
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_16_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_16_READ_PERM_16_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_16_READ_PERM_16_OFFSET 0
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_16_READ_PERM_16_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_16_READ_PERM_16_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_16_READ_PERM_16_OFFSET })
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_16_WRITE_PERM_16_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_16_WRITE_PERM_16_OFFSET 16
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_16_WRITE_PERM_16_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_16_WRITE_PERM_16_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_16_WRITE_PERM_16_OFFSET })
 
// The RACL policy register allows the system to further restrict the access
// to specific source roles.
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_17_REG_OFFSET 0x264
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_17_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_17_READ_PERM_17_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_17_READ_PERM_17_OFFSET 0
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_17_READ_PERM_17_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_17_READ_PERM_17_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_17_READ_PERM_17_OFFSET })
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_17_WRITE_PERM_17_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_17_WRITE_PERM_17_OFFSET 16
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_17_WRITE_PERM_17_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_17_WRITE_PERM_17_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_17_WRITE_PERM_17_OFFSET })
 
// The RACL policy register allows the system to further restrict the access
// to specific source roles.
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_18_REG_OFFSET 0x268
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_18_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_18_READ_PERM_18_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_18_READ_PERM_18_OFFSET 0
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_18_READ_PERM_18_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_18_READ_PERM_18_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_18_READ_PERM_18_OFFSET })
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_18_WRITE_PERM_18_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_18_WRITE_PERM_18_OFFSET 16
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_18_WRITE_PERM_18_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_18_WRITE_PERM_18_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_18_WRITE_PERM_18_OFFSET })
 
// The RACL policy register allows the system to further restrict the access
// to specific source roles.
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_19_REG_OFFSET 0x26c
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_19_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_19_READ_PERM_19_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_19_READ_PERM_19_OFFSET 0
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_19_READ_PERM_19_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_19_READ_PERM_19_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_19_READ_PERM_19_OFFSET })
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_19_WRITE_PERM_19_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_19_WRITE_PERM_19_OFFSET 16
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_19_WRITE_PERM_19_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_19_WRITE_PERM_19_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_19_WRITE_PERM_19_OFFSET })
 
// The RACL policy register allows the system to further restrict the access
// to specific source roles.
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_20_REG_OFFSET 0x270
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_20_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_20_READ_PERM_20_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_20_READ_PERM_20_OFFSET 0
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_20_READ_PERM_20_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_20_READ_PERM_20_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_20_READ_PERM_20_OFFSET })
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_20_WRITE_PERM_20_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_20_WRITE_PERM_20_OFFSET 16
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_20_WRITE_PERM_20_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_20_WRITE_PERM_20_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_20_WRITE_PERM_20_OFFSET })
 
// The RACL policy register allows the system to further restrict the access
// to specific source roles.
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_21_REG_OFFSET 0x274
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_21_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_21_READ_PERM_21_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_21_READ_PERM_21_OFFSET 0
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_21_READ_PERM_21_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_21_READ_PERM_21_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_21_READ_PERM_21_OFFSET })
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_21_WRITE_PERM_21_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_21_WRITE_PERM_21_OFFSET 16
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_21_WRITE_PERM_21_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_21_WRITE_PERM_21_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_21_WRITE_PERM_21_OFFSET })
 
// The RACL policy register allows the system to further restrict the access
// to specific source roles.
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_22_REG_OFFSET 0x278
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_22_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_22_READ_PERM_22_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_22_READ_PERM_22_OFFSET 0
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_22_READ_PERM_22_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_22_READ_PERM_22_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_22_READ_PERM_22_OFFSET })
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_22_WRITE_PERM_22_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_22_WRITE_PERM_22_OFFSET 16
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_22_WRITE_PERM_22_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_22_WRITE_PERM_22_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_22_WRITE_PERM_22_OFFSET })
 
// The RACL policy register allows the system to further restrict the access
// to specific source roles.
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_23_REG_OFFSET 0x27c
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_23_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_23_READ_PERM_23_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_23_READ_PERM_23_OFFSET 0
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_23_READ_PERM_23_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_23_READ_PERM_23_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_23_READ_PERM_23_OFFSET })
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_23_WRITE_PERM_23_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_23_WRITE_PERM_23_OFFSET 16
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_23_WRITE_PERM_23_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_23_WRITE_PERM_23_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_23_WRITE_PERM_23_OFFSET })
 
// The RACL policy register allows the system to further restrict the access
// to specific source roles.
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_24_REG_OFFSET 0x280
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_24_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_24_READ_PERM_24_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_24_READ_PERM_24_OFFSET 0
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_24_READ_PERM_24_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_24_READ_PERM_24_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_24_READ_PERM_24_OFFSET })
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_24_WRITE_PERM_24_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_24_WRITE_PERM_24_OFFSET 16
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_24_WRITE_PERM_24_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_24_WRITE_PERM_24_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_24_WRITE_PERM_24_OFFSET })
 
// The RACL policy register allows the system to further restrict the access
// to specific source roles.
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_25_REG_OFFSET 0x284
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_25_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_25_READ_PERM_25_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_25_READ_PERM_25_OFFSET 0
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_25_READ_PERM_25_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_25_READ_PERM_25_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_25_READ_PERM_25_OFFSET })
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_25_WRITE_PERM_25_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_25_WRITE_PERM_25_OFFSET 16
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_25_WRITE_PERM_25_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_25_WRITE_PERM_25_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_25_WRITE_PERM_25_OFFSET })
 
// The RACL policy register allows the system to further restrict the access
// to specific source roles.
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_26_REG_OFFSET 0x288
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_26_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_26_READ_PERM_26_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_26_READ_PERM_26_OFFSET 0
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_26_READ_PERM_26_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_26_READ_PERM_26_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_26_READ_PERM_26_OFFSET })
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_26_WRITE_PERM_26_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_26_WRITE_PERM_26_OFFSET 16
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_26_WRITE_PERM_26_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_26_WRITE_PERM_26_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_26_WRITE_PERM_26_OFFSET })
 
// The RACL policy register allows the system to further restrict the access
// to specific source roles.
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_27_REG_OFFSET 0x28c
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_27_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_27_READ_PERM_27_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_27_READ_PERM_27_OFFSET 0
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_27_READ_PERM_27_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_27_READ_PERM_27_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_27_READ_PERM_27_OFFSET })
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_27_WRITE_PERM_27_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_27_WRITE_PERM_27_OFFSET 16
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_27_WRITE_PERM_27_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_27_WRITE_PERM_27_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_27_WRITE_PERM_27_OFFSET })
 
// The RACL policy register allows the system to further restrict the access
// to specific source roles.
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_28_REG_OFFSET 0x290
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_28_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_28_READ_PERM_28_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_28_READ_PERM_28_OFFSET 0
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_28_READ_PERM_28_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_28_READ_PERM_28_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_28_READ_PERM_28_OFFSET })
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_28_WRITE_PERM_28_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_28_WRITE_PERM_28_OFFSET 16
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_28_WRITE_PERM_28_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_28_WRITE_PERM_28_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_28_WRITE_PERM_28_OFFSET })
 
// The RACL policy register allows the system to further restrict the access
// to specific source roles.
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_29_REG_OFFSET 0x294
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_29_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_29_READ_PERM_29_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_29_READ_PERM_29_OFFSET 0
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_29_READ_PERM_29_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_29_READ_PERM_29_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_29_READ_PERM_29_OFFSET })
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_29_WRITE_PERM_29_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_29_WRITE_PERM_29_OFFSET 16
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_29_WRITE_PERM_29_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_29_WRITE_PERM_29_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_29_WRITE_PERM_29_OFFSET })
 
// The RACL policy register allows the system to further restrict the access
// to specific source roles.
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_30_REG_OFFSET 0x298
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_30_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_30_READ_PERM_30_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_30_READ_PERM_30_OFFSET 0
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_30_READ_PERM_30_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_30_READ_PERM_30_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_30_READ_PERM_30_OFFSET })
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_30_WRITE_PERM_30_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_30_WRITE_PERM_30_OFFSET 16
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_30_WRITE_PERM_30_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_30_WRITE_PERM_30_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_30_WRITE_PERM_30_OFFSET })
 
// The RACL policy register allows the system to further restrict the access
// to specific source roles.
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_31_REG_OFFSET 0x29c
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_31_REG_RESVAL 0x0u
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_31_READ_PERM_31_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_31_READ_PERM_31_OFFSET 0
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_31_READ_PERM_31_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_31_READ_PERM_31_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_31_READ_PERM_31_OFFSET })
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_31_WRITE_PERM_31_MASK 0xffffu
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_31_WRITE_PERM_31_OFFSET 16
#define AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_31_WRITE_PERM_31_FIELD \
  ((bitfield_field32_t) { .mask = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_31_WRITE_PERM_31_MASK, .index = AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_31_WRITE_PERM_31_OFFSET })
 
#ifdef __cplusplus
}  // extern "C"
#endif
#endif  // _AC_RANGE_CHECK_REG_DEFS_
// End generated register defines for ac_range_check