spi_host_regs.h

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/**
 * @file
 * @brief Generated register defines for spi_host
 */
 
// Copyright information found in source file:
// Copyright lowRISC contributors (OpenTitan project).
 
// Licensing information found in source file:
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
 
#ifndef _SPI_HOST_REG_DEFS_
#define _SPI_HOST_REG_DEFS_
 
#ifdef __cplusplus
extern "C" {
#endif
// Byte order to use when transmitting or receiving data.  If ByteOrder = 0,
#define SPI_HOST_PARAM_BYTE_ORDER 1
 
// The size of the Tx FIFO (in words)
#define SPI_HOST_PARAM_TX_DEPTH 72
 
// The size of the Rx FIFO (in words)
#define SPI_HOST_PARAM_RX_DEPTH 64
 
// The size of the Cmd FIFO (one segment descriptor per entry)
#define SPI_HOST_PARAM_CMD_DEPTH 4
 
// Number of alerts
#define SPI_HOST_PARAM_NUM_ALERTS 1
 
// Register width
#define SPI_HOST_PARAM_REG_WIDTH 32
 
// Common Interrupt Offsets
#define SPI_HOST_INTR_COMMON_ERROR_BIT 0
#define SPI_HOST_INTR_COMMON_SPI_EVENT_BIT 1
 
// Interrupt State Register
#define SPI_HOST_INTR_STATE_REG_OFFSET 0x0
#define SPI_HOST_INTR_STATE_REG_RESVAL 0x0u
#define SPI_HOST_INTR_STATE_ERROR_BIT 0
#define SPI_HOST_INTR_STATE_SPI_EVENT_BIT 1
 
// Interrupt Enable Register
#define SPI_HOST_INTR_ENABLE_REG_OFFSET 0x4
#define SPI_HOST_INTR_ENABLE_REG_RESVAL 0x0u
#define SPI_HOST_INTR_ENABLE_ERROR_BIT 0
#define SPI_HOST_INTR_ENABLE_SPI_EVENT_BIT 1
 
// Interrupt Test Register
#define SPI_HOST_INTR_TEST_REG_OFFSET 0x8
#define SPI_HOST_INTR_TEST_REG_RESVAL 0x0u
#define SPI_HOST_INTR_TEST_ERROR_BIT 0
#define SPI_HOST_INTR_TEST_SPI_EVENT_BIT 1
 
// Alert Test Register
#define SPI_HOST_ALERT_TEST_REG_OFFSET 0xc
#define SPI_HOST_ALERT_TEST_REG_RESVAL 0x80000000u
#define SPI_HOST_ALERT_TEST_FATAL_FAULT_BIT 0
#define SPI_HOST_ALERT_TEST_REGWEN_BIT 31
 
// Control register
#define SPI_HOST_CONTROL_REG_OFFSET 0x10
#define SPI_HOST_CONTROL_REG_RESVAL 0x7fu
#define SPI_HOST_CONTROL_RX_WATERMARK_MASK 0xffu
#define SPI_HOST_CONTROL_RX_WATERMARK_OFFSET 0
#define SPI_HOST_CONTROL_RX_WATERMARK_FIELD \
  ((bitfield_field32_t) { .mask = SPI_HOST_CONTROL_RX_WATERMARK_MASK, .index = SPI_HOST_CONTROL_RX_WATERMARK_OFFSET })
#define SPI_HOST_CONTROL_TX_WATERMARK_MASK 0xffu
#define SPI_HOST_CONTROL_TX_WATERMARK_OFFSET 8
#define SPI_HOST_CONTROL_TX_WATERMARK_FIELD \
  ((bitfield_field32_t) { .mask = SPI_HOST_CONTROL_TX_WATERMARK_MASK, .index = SPI_HOST_CONTROL_TX_WATERMARK_OFFSET })
#define SPI_HOST_CONTROL_OUTPUT_EN_BIT 29
#define SPI_HOST_CONTROL_SW_RST_BIT 30
#define SPI_HOST_CONTROL_SPIEN_BIT 31
 
// Status register
#define SPI_HOST_STATUS_REG_OFFSET 0x14
#define SPI_HOST_STATUS_REG_RESVAL 0x0u
#define SPI_HOST_STATUS_TXQD_MASK 0xffu
#define SPI_HOST_STATUS_TXQD_OFFSET 0
#define SPI_HOST_STATUS_TXQD_FIELD \
  ((bitfield_field32_t) { .mask = SPI_HOST_STATUS_TXQD_MASK, .index = SPI_HOST_STATUS_TXQD_OFFSET })
#define SPI_HOST_STATUS_RXQD_MASK 0xffu
#define SPI_HOST_STATUS_RXQD_OFFSET 8
#define SPI_HOST_STATUS_RXQD_FIELD \
  ((bitfield_field32_t) { .mask = SPI_HOST_STATUS_RXQD_MASK, .index = SPI_HOST_STATUS_RXQD_OFFSET })
#define SPI_HOST_STATUS_CMDQD_MASK 0xfu
#define SPI_HOST_STATUS_CMDQD_OFFSET 16
#define SPI_HOST_STATUS_CMDQD_FIELD \
  ((bitfield_field32_t) { .mask = SPI_HOST_STATUS_CMDQD_MASK, .index = SPI_HOST_STATUS_CMDQD_OFFSET })
#define SPI_HOST_STATUS_RXWM_BIT 20
#define SPI_HOST_STATUS_BYTEORDER_BIT 22
#define SPI_HOST_STATUS_RXSTALL_BIT 23
#define SPI_HOST_STATUS_RXEMPTY_BIT 24
#define SPI_HOST_STATUS_RXFULL_BIT 25
#define SPI_HOST_STATUS_TXWM_BIT 26
#define SPI_HOST_STATUS_TXSTALL_BIT 27
#define SPI_HOST_STATUS_TXEMPTY_BIT 28
#define SPI_HOST_STATUS_TXFULL_BIT 29
#define SPI_HOST_STATUS_ACTIVE_BIT 30
#define SPI_HOST_STATUS_READY_BIT 31
 
// Configuration options register.
#define SPI_HOST_CONFIGOPTS_REG_OFFSET 0x18
#define SPI_HOST_CONFIGOPTS_REG_RESVAL 0x0u
#define SPI_HOST_CONFIGOPTS_CLKDIV_MASK 0xffffu
#define SPI_HOST_CONFIGOPTS_CLKDIV_OFFSET 0
#define SPI_HOST_CONFIGOPTS_CLKDIV_FIELD \
  ((bitfield_field32_t) { .mask = SPI_HOST_CONFIGOPTS_CLKDIV_MASK, .index = SPI_HOST_CONFIGOPTS_CLKDIV_OFFSET })
#define SPI_HOST_CONFIGOPTS_CSNIDLE_MASK 0xfu
#define SPI_HOST_CONFIGOPTS_CSNIDLE_OFFSET 16
#define SPI_HOST_CONFIGOPTS_CSNIDLE_FIELD \
  ((bitfield_field32_t) { .mask = SPI_HOST_CONFIGOPTS_CSNIDLE_MASK, .index = SPI_HOST_CONFIGOPTS_CSNIDLE_OFFSET })
#define SPI_HOST_CONFIGOPTS_CSNTRAIL_MASK 0xfu
#define SPI_HOST_CONFIGOPTS_CSNTRAIL_OFFSET 20
#define SPI_HOST_CONFIGOPTS_CSNTRAIL_FIELD \
  ((bitfield_field32_t) { .mask = SPI_HOST_CONFIGOPTS_CSNTRAIL_MASK, .index = SPI_HOST_CONFIGOPTS_CSNTRAIL_OFFSET })
#define SPI_HOST_CONFIGOPTS_CSNLEAD_MASK 0xfu
#define SPI_HOST_CONFIGOPTS_CSNLEAD_OFFSET 24
#define SPI_HOST_CONFIGOPTS_CSNLEAD_FIELD \
  ((bitfield_field32_t) { .mask = SPI_HOST_CONFIGOPTS_CSNLEAD_MASK, .index = SPI_HOST_CONFIGOPTS_CSNLEAD_OFFSET })
#define SPI_HOST_CONFIGOPTS_FULLCYC_BIT 29
#define SPI_HOST_CONFIGOPTS_CPHA_BIT 30
#define SPI_HOST_CONFIGOPTS_CPOL_BIT 31
 
// Chip-Select ID
#define SPI_HOST_CSID_REG_OFFSET 0x1c
#define SPI_HOST_CSID_REG_RESVAL 0x0u
 
// Command Register
#define SPI_HOST_COMMAND_REG_OFFSET 0x20
#define SPI_HOST_COMMAND_REG_RESVAL 0x0u
#define SPI_HOST_COMMAND_CSAAT_BIT 0
#define SPI_HOST_COMMAND_SPEED_MASK 0x3u
#define SPI_HOST_COMMAND_SPEED_OFFSET 1
#define SPI_HOST_COMMAND_SPEED_FIELD \
  ((bitfield_field32_t) { .mask = SPI_HOST_COMMAND_SPEED_MASK, .index = SPI_HOST_COMMAND_SPEED_OFFSET })
#define SPI_HOST_COMMAND_DIRECTION_MASK 0x3u
#define SPI_HOST_COMMAND_DIRECTION_OFFSET 3
#define SPI_HOST_COMMAND_DIRECTION_FIELD \
  ((bitfield_field32_t) { .mask = SPI_HOST_COMMAND_DIRECTION_MASK, .index = SPI_HOST_COMMAND_DIRECTION_OFFSET })
#define SPI_HOST_COMMAND_LEN_MASK 0xfffffu
#define SPI_HOST_COMMAND_LEN_OFFSET 5
#define SPI_HOST_COMMAND_LEN_FIELD \
  ((bitfield_field32_t) { .mask = SPI_HOST_COMMAND_LEN_MASK, .index = SPI_HOST_COMMAND_LEN_OFFSET })
 
// Memory area: SPI Receive Data.
#define SPI_HOST_RXDATA_REG_OFFSET 0x24
#define SPI_HOST_RXDATA_SIZE_WORDS 1
#define SPI_HOST_RXDATA_SIZE_BYTES 4
// Memory area: SPI Transmit Data.
#define SPI_HOST_TXDATA_REG_OFFSET 0x28
#define SPI_HOST_TXDATA_SIZE_WORDS 1
#define SPI_HOST_TXDATA_SIZE_BYTES 4
// Controls which classes of errors raise an interrupt.
#define SPI_HOST_ERROR_ENABLE_REG_OFFSET 0x2c
#define SPI_HOST_ERROR_ENABLE_REG_RESVAL 0x1fu
#define SPI_HOST_ERROR_ENABLE_CMDBUSY_BIT 0
#define SPI_HOST_ERROR_ENABLE_OVERFLOW_BIT 1
#define SPI_HOST_ERROR_ENABLE_UNDERFLOW_BIT 2
#define SPI_HOST_ERROR_ENABLE_CMDINVAL_BIT 3
#define SPI_HOST_ERROR_ENABLE_CSIDINVAL_BIT 4
 
// Indicates that any errors that have occurred.
#define SPI_HOST_ERROR_STATUS_REG_OFFSET 0x30
#define SPI_HOST_ERROR_STATUS_REG_RESVAL 0x0u
#define SPI_HOST_ERROR_STATUS_CMDBUSY_BIT 0
#define SPI_HOST_ERROR_STATUS_OVERFLOW_BIT 1
#define SPI_HOST_ERROR_STATUS_UNDERFLOW_BIT 2
#define SPI_HOST_ERROR_STATUS_CMDINVAL_BIT 3
#define SPI_HOST_ERROR_STATUS_CSIDINVAL_BIT 4
#define SPI_HOST_ERROR_STATUS_ACCESSINVAL_BIT 5
 
// Controls which classes of SPI events raise an interrupt.
#define SPI_HOST_EVENT_ENABLE_REG_OFFSET 0x34
#define SPI_HOST_EVENT_ENABLE_REG_RESVAL 0x0u
#define SPI_HOST_EVENT_ENABLE_RXFULL_BIT 0
#define SPI_HOST_EVENT_ENABLE_TXEMPTY_BIT 1
#define SPI_HOST_EVENT_ENABLE_RXWM_BIT 2
#define SPI_HOST_EVENT_ENABLE_TXWM_BIT 3
#define SPI_HOST_EVENT_ENABLE_READY_BIT 4
#define SPI_HOST_EVENT_ENABLE_IDLE_BIT 5
 
#ifdef __cplusplus
}  // extern "C"
#endif
#endif  // _SPI_HOST_REG_DEFS_
// End generated register defines for spi_host