gpio.h

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// Copyright lowRISC contributors (OpenTitan project).
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Device table API auto-generated by `dtgen`
 
#ifndef OPENTITAN_DT_GPIO_H_
#define OPENTITAN_DT_GPIO_H_
 
#ifdef __cplusplus
extern "C" {
#endif  // __cplusplus
 
/**
 * @file
 * @brief Device Tables (DT) for IP gpio and top englishbreakfast.
 *
 * This file contains the type definitions and global functions of the gpio.
 */
 
#include "hw/top/dt/api.h"
#include <stdint.h>
 
 
 
 
 
/**
 * List of instances.
 */
typedef enum dt_gpio {
  kDtGpioFirst = 0, /**< First instance */
  kDtGpio = 0, /**< gpio */
} dt_gpio_t;
 
enum {
  kDtGpioCount = 1, /**< Number of instances */
};
 
 
/**
 * List of register blocks.
 *
 * Register blocks are guaranteed to start at 0 and to be consecutively numbered.
 */
typedef enum dt_gpio_reg_block {
  kDtGpioRegBlockCore = 0, /**<  */
} dt_gpio_reg_block_t;
 
enum {
  kDtGpioRegBlockCount = 1, /**< Number of register blocks */
};
 
 
/** Primary register block (associated with the "primary" set of registers that control the IP). */
static const dt_gpio_reg_block_t kDtGpioRegBlockPrimary = kDtGpioRegBlockCore;
 
/**
 * List of IRQs.
 *
 * IRQs are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_gpio_irq {
  kDtGpioIrqGpio0 = 0, /**< raised if any of GPIO pin detects configured interrupt mode */
  kDtGpioIrqGpio1 = 1, /**< raised if any of GPIO pin detects configured interrupt mode */
  kDtGpioIrqGpio2 = 2, /**< raised if any of GPIO pin detects configured interrupt mode */
  kDtGpioIrqGpio3 = 3, /**< raised if any of GPIO pin detects configured interrupt mode */
  kDtGpioIrqGpio4 = 4, /**< raised if any of GPIO pin detects configured interrupt mode */
  kDtGpioIrqGpio5 = 5, /**< raised if any of GPIO pin detects configured interrupt mode */
  kDtGpioIrqGpio6 = 6, /**< raised if any of GPIO pin detects configured interrupt mode */
  kDtGpioIrqGpio7 = 7, /**< raised if any of GPIO pin detects configured interrupt mode */
  kDtGpioIrqGpio8 = 8, /**< raised if any of GPIO pin detects configured interrupt mode */
  kDtGpioIrqGpio9 = 9, /**< raised if any of GPIO pin detects configured interrupt mode */
  kDtGpioIrqGpio10 = 10, /**< raised if any of GPIO pin detects configured interrupt mode */
  kDtGpioIrqGpio11 = 11, /**< raised if any of GPIO pin detects configured interrupt mode */
  kDtGpioIrqGpio12 = 12, /**< raised if any of GPIO pin detects configured interrupt mode */
  kDtGpioIrqGpio13 = 13, /**< raised if any of GPIO pin detects configured interrupt mode */
  kDtGpioIrqGpio14 = 14, /**< raised if any of GPIO pin detects configured interrupt mode */
  kDtGpioIrqGpio15 = 15, /**< raised if any of GPIO pin detects configured interrupt mode */
  kDtGpioIrqGpio16 = 16, /**< raised if any of GPIO pin detects configured interrupt mode */
  kDtGpioIrqGpio17 = 17, /**< raised if any of GPIO pin detects configured interrupt mode */
  kDtGpioIrqGpio18 = 18, /**< raised if any of GPIO pin detects configured interrupt mode */
  kDtGpioIrqGpio19 = 19, /**< raised if any of GPIO pin detects configured interrupt mode */
  kDtGpioIrqGpio20 = 20, /**< raised if any of GPIO pin detects configured interrupt mode */
  kDtGpioIrqGpio21 = 21, /**< raised if any of GPIO pin detects configured interrupt mode */
  kDtGpioIrqGpio22 = 22, /**< raised if any of GPIO pin detects configured interrupt mode */
  kDtGpioIrqGpio23 = 23, /**< raised if any of GPIO pin detects configured interrupt mode */
  kDtGpioIrqGpio24 = 24, /**< raised if any of GPIO pin detects configured interrupt mode */
  kDtGpioIrqGpio25 = 25, /**< raised if any of GPIO pin detects configured interrupt mode */
  kDtGpioIrqGpio26 = 26, /**< raised if any of GPIO pin detects configured interrupt mode */
  kDtGpioIrqGpio27 = 27, /**< raised if any of GPIO pin detects configured interrupt mode */
  kDtGpioIrqGpio28 = 28, /**< raised if any of GPIO pin detects configured interrupt mode */
  kDtGpioIrqGpio29 = 29, /**< raised if any of GPIO pin detects configured interrupt mode */
  kDtGpioIrqGpio30 = 30, /**< raised if any of GPIO pin detects configured interrupt mode */
  kDtGpioIrqGpio31 = 31, /**< raised if any of GPIO pin detects configured interrupt mode */
} dt_gpio_irq_t;
 
enum {
  kDtGpioIrqCount = 32, /**< Number of IRQs */
};
 
 
/**
 * List of clock ports.
 *
 * Clock ports are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_gpio_clock {
  kDtGpioClockClk = 0, /**< Clock port clk_i */
} dt_gpio_clock_t;
 
enum {
  kDtGpioClockCount = 1, /**< Number of clock ports */
};
 
 
/**
 * List of reset ports.
 *
 * Reset ports are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_gpio_reset {
  kDtGpioResetRst = 0, /**< Reset port rst_ni */
} dt_gpio_reset_t;
 
enum {
  kDtGpioResetCount = 1, /**< Number of reset ports */
};
 
 
/**
 * List of peripheral I/O.
 *
 * Peripheral I/O are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_gpio_periph_io {
  kDtGpioPeriphIoGpio0 = 0, /**<  */
  kDtGpioPeriphIoGpio1 = 1, /**<  */
  kDtGpioPeriphIoGpio2 = 2, /**<  */
  kDtGpioPeriphIoGpio3 = 3, /**<  */
  kDtGpioPeriphIoGpio4 = 4, /**<  */
  kDtGpioPeriphIoGpio5 = 5, /**<  */
  kDtGpioPeriphIoGpio6 = 6, /**<  */
  kDtGpioPeriphIoGpio7 = 7, /**<  */
  kDtGpioPeriphIoGpio8 = 8, /**<  */
  kDtGpioPeriphIoGpio9 = 9, /**<  */
  kDtGpioPeriphIoGpio10 = 10, /**<  */
  kDtGpioPeriphIoGpio11 = 11, /**<  */
  kDtGpioPeriphIoGpio12 = 12, /**<  */
  kDtGpioPeriphIoGpio13 = 13, /**<  */
  kDtGpioPeriphIoGpio14 = 14, /**<  */
  kDtGpioPeriphIoGpio15 = 15, /**<  */
  kDtGpioPeriphIoGpio16 = 16, /**<  */
  kDtGpioPeriphIoGpio17 = 17, /**<  */
  kDtGpioPeriphIoGpio18 = 18, /**<  */
  kDtGpioPeriphIoGpio19 = 19, /**<  */
  kDtGpioPeriphIoGpio20 = 20, /**<  */
  kDtGpioPeriphIoGpio21 = 21, /**<  */
  kDtGpioPeriphIoGpio22 = 22, /**<  */
  kDtGpioPeriphIoGpio23 = 23, /**<  */
  kDtGpioPeriphIoGpio24 = 24, /**<  */
  kDtGpioPeriphIoGpio25 = 25, /**<  */
  kDtGpioPeriphIoGpio26 = 26, /**<  */
  kDtGpioPeriphIoGpio27 = 27, /**<  */
  kDtGpioPeriphIoGpio28 = 28, /**<  */
  kDtGpioPeriphIoGpio29 = 29, /**<  */
  kDtGpioPeriphIoGpio30 = 30, /**<  */
  kDtGpioPeriphIoGpio31 = 31, /**<  */
} dt_gpio_periph_io_t;
 
enum {
  kDtGpioPeriphIoCount = 32, /**< Number of peripheral I/O */
};
 
 
/**
 * List of supported hardware features.
 */
#define OPENTITAN_GPIO_HAS_IN_INTR_CTRL 1
#define OPENTITAN_GPIO_HAS_IN_FILTER 1
#define OPENTITAN_GPIO_HAS_OUT_MASK 1
 
 
 
/**
 * Get the gpio instance from an instance ID
 *
 * For example, `dt_uart_from_instance_id(kDtInstanceIdUart3) == kDtUart3`.
 *
 * @param inst_id Instance ID.
 * @return A gpio instance.
 *
 * **Note:** This function only makes sense if the instance ID has device type gpio,
 * otherwise the returned value is unspecified.
 */
dt_gpio_t dt_gpio_from_instance_id(dt_instance_id_t inst_id);
 
/**
 * Get the instance ID of an instance.
 *
 * @param dt Instance of gpio.
 * @return The instance ID of that instance.
 */
dt_instance_id_t dt_gpio_instance_id(dt_gpio_t dt);
 
/**
 * Get the register base address of an instance.
 *
 * @param dt Instance of gpio.
 * @param reg_block The register block requested.
 * @return The register base address of the requested block.
 */
uint32_t dt_gpio_reg_block(
    dt_gpio_t dt,
    dt_gpio_reg_block_t reg_block);
 
/**
 * Get the primary register base address of an instance.
 *
 * This is just a convenience function, equivalent to
 * `dt_gpio_reg_block(dt, kDtGpioRegBlockCore)`
 *
 * @param dt Instance of gpio.
 * @return The register base address of the primary register block.
 */
static inline uint32_t dt_gpio_primary_reg_block(
    dt_gpio_t dt) {
  return dt_gpio_reg_block(dt, kDtGpioRegBlockCore);
}
 
/**
 * Get the PLIC ID of a gpio IRQ for a given instance.
 *
 * If the instance is not connected to the PLIC, this function
 * will return `kDtPlicIrqIdNone`.
 *
 * @param dt Instance of gpio.
 * @param irq A gpio IRQ.
 * @return The PLIC ID of the IRQ of this instance.
 */
dt_plic_irq_id_t dt_gpio_irq_to_plic_id(
    dt_gpio_t dt,
    dt_gpio_irq_t irq);
 
/**
 * Convert a global IRQ ID to a local gpio IRQ type.
 *
 * @param dt Instance of gpio.
 * @param irq A PLIC ID that belongs to this instance.
 * @return The gpio IRQ, or `kDtGpioIrqCount`.
 *
 * **Note:** This function assumes that the PLIC ID belongs to the instance
 * of gpio passed in parameter. In other words, it must be the case that
 * `dt_gpio_instance_id(dt) == dt_plic_id_to_instance_id(irq)`. Otherwise, this function
 * will return `kDtGpioIrqCount`.
 */
dt_gpio_irq_t dt_gpio_irq_from_plic_id(
    dt_gpio_t dt,
    dt_plic_irq_id_t irq);
 
 
 
/**
 * Get the peripheral I/O description of an instance.
 *
 * @param dt Instance of gpio.
 * @param sig Requested peripheral I/O.
 * @return Description of the requested peripheral I/O for this instance.
 */
dt_periph_io_t dt_gpio_periph_io(
    dt_gpio_t dt,
    dt_gpio_periph_io_t sig);
 
/**
 * Get the clock signal connected to a clock port of an instance.
 *
 * @param dt Instance of gpio.
 * @param clk Clock port.
 * @return Clock signal.
 */
dt_clock_t dt_gpio_clock(
    dt_gpio_t dt,
    dt_gpio_clock_t clk);
 
/**
 * Get the reset signal connected to a reset port of an instance.
 *
 * @param dt Instance of gpio.
 * @param rst Reset port.
 * @return Reset signal.
 */
dt_reset_t dt_gpio_reset(
    dt_gpio_t dt,
    dt_gpio_reset_t rst);
 
 
 
/**
 * Get the number of input period counters.
 *
 * @param dt Instance of gpio.
 * @return number of input period counters.
 */
uint8_t dt_gpio_input_period_counter_count(dt_gpio_t dt);
 
 
 
#ifdef __cplusplus
}  // extern "C"
#endif  // __cplusplus
 
#endif  // OPENTITAN_DT_GPIO_H_