54kDtUsbdevIrqHostLost = 3, /**< Raised if link is active but SOF was not received from host for 4.096 ms. The SOF should be every 1 ms. */
55kDtUsbdevIrqLinkReset = 4, /**< Raised if the link is at SE0 longer than 3 us indicating a link reset (host asserts for min 10 ms, device can react after 2.5 us). */
56kDtUsbdevIrqLinkSuspend = 5, /**< Raised if the line has signaled J for longer than 3ms and is therefore in suspend state. */
57kDtUsbdevIrqLinkResume = 6, /**< Raised when the link becomes active again after being suspended. */
58kDtUsbdevIrqAvOutEmpty = 7, /**< Raised when the Available OUT Buffer FIFO is empty and the device interface is enabled.
59This interrupt is directly tied to the FIFO status, so the Available OUT Buffer FIFO must be provided with a free buffer before the interrupt can be cleared. */
60kDtUsbdevIrqRxFull = 8, /**< Raised when the RX FIFO is full and the device interface is enabled.
61This interrupt is directly tied to the FIFO status, so the RX FIFO must have an entry removed before the interrupt is cleared.
62If the condition is not cleared, the interrupt can re-assert. */
63kDtUsbdevIrqAvOverflow = 9, /**< Raised if a write was done to either the Available OUT Buffer FIFO or the Available SETUP Buffer FIFO when the FIFO was full. */
64kDtUsbdevIrqLinkInErr = 10, /**< Raised if a packet to an IN endpoint started to be received but was
65then dropped due to an error. After transmitting the IN payload,
66the USB device expects a valid ACK handshake packet. This error is
67raised if either the packet or CRC is invalid, leading to a NAK instead,
74kDtUsbdevIrqLinkOutErr = 16, /**< Raised if a packet to an OUT endpoint started to be received but was then dropped due to an error.
75This error is raised if the data toggle, token, packet and/or CRC are invalid, or if the appropriate Available OUT Buffer FIFO is empty and/or the Received Buffer FIFO is full when a packet should have been received. */
76kDtUsbdevIrqAvSetupEmpty = 17, /**< Raised when the Available SETUP Buffer FIFO is empty and the device interface is enabled.
77This interrupt is directly tied to the FIFO status, so the Available SETUP Buffer FIFO must be provided with a free buffer before the interrupt can be cleared. */
78 kDtUsbdevIrqCount = 18, /**< \internal Number of IRQs */