dt_sram_ctrl.c

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// Copyright lowRISC contributors (OpenTitan project).
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Device table API auto-generated by `dtgen`
 
/**
 * @file
 * @brief Device Tables (DT) for IP sram_ctrl and top englishbreakfast.
 */
 
#include "hw/top/dt/dt_sram_ctrl.h"
 
 
 
/**
 * Description of instances.
 */
typedef struct dt_desc_sram_ctrl {
  dt_instance_id_t inst_id; /**< Instance ID */
  uint32_t reg_addr[kDtSramCtrlRegBlockCount]; /**< Base address of each register block */
  uint32_t mem_addr[kDtSramCtrlMemoryCount]; /**< Base address of each memory */
  uint32_t mem_size[kDtSramCtrlMemoryCount]; /**< Size in bytes of each memory */
  dt_clock_t clock[kDtSramCtrlClockCount]; /**< Clock signal connected to each clock port */
  dt_reset_t reset[kDtSramCtrlResetCount]; /**< Reset signal connected to each reset port */
} dt_desc_sram_ctrl_t;
 
 
 
 
static const dt_desc_sram_ctrl_t sram_ctrl_desc[kDtSramCtrlCount] = {
  [kDtSramCtrlMain] = {
    .inst_id = kDtInstanceIdSramCtrlMain,
    .reg_addr = {
      [kDtSramCtrlRegBlockRegs] = 0x411C0000,
    },
    .mem_addr = {
      [kDtSramCtrlMemoryRam] = 0x10000000,
    },
    .mem_size = {
      [kDtSramCtrlMemoryRam] = 0x20000,
    },
    .clock = {
      [kDtSramCtrlClockClk] = kDtClockMain,
      [kDtSramCtrlClockOtp] = kDtClockIoDiv4,
    },
    .reset = {
      [kDtSramCtrlResetRst] = kDtResetSys,
      [kDtSramCtrlResetOtp] = kDtResetLcIoDiv4,
    },
  },
};
 
/**
 * Return a pointer to the `dt_sram_ctrl_desc_t` structure of the requested
 * `dt` if it's a valid index. Otherwise, this macro will `return` (i.e. exit
 * the function) with the provided default value.
 */
#define TRY_GET_DT(dt, default)   ({     if ((dt) < (dt_sram_ctrl_t)0 || (dt) >= kDtSramCtrlCount)       return (default);     &sram_ctrl_desc[dt];   })
 
dt_sram_ctrl_t dt_sram_ctrl_from_instance_id(dt_instance_id_t inst_id) {
  if (inst_id >= kDtInstanceIdSramCtrlMain && inst_id <= kDtInstanceIdSramCtrlMain) {
    return (dt_sram_ctrl_t)(inst_id - kDtInstanceIdSramCtrlMain);
  }
  return (dt_sram_ctrl_t)0;
}
 
dt_instance_id_t dt_sram_ctrl_instance_id(
    dt_sram_ctrl_t dt) {
  return TRY_GET_DT(dt, kDtInstanceIdUnknown)->inst_id;
}
 
uint32_t dt_sram_ctrl_reg_block(
    dt_sram_ctrl_t dt,
    dt_sram_ctrl_reg_block_t reg_block) {
  // Return a recognizable address in case of wrong argument.
  return TRY_GET_DT(dt, 0xdeadbeef)->reg_addr[reg_block];
}
 
uint32_t dt_sram_ctrl_memory_base(
    dt_sram_ctrl_t dt,
    dt_sram_ctrl_memory_t mem) {
  // Return a recognizable address in case of wrong argument.
  return TRY_GET_DT(dt, 0xdeadbeef)->mem_addr[mem];
}
 
uint32_t dt_sram_ctrl_memory_size(
    dt_sram_ctrl_t dt,
    dt_sram_ctrl_memory_t mem)  {
  // Return an empty size in case of wrong argument.
  return TRY_GET_DT(dt, 0)->mem_size[mem];
}
 
 
 
 
dt_clock_t dt_sram_ctrl_clock(
    dt_sram_ctrl_t dt,
    dt_sram_ctrl_clock_t clk) {
  // Return the first clock in case of invalid argument.
  return TRY_GET_DT(dt, (dt_clock_t)0)->clock[clk];
}
 
dt_reset_t dt_sram_ctrl_reset(
    dt_sram_ctrl_t dt,
    dt_sram_ctrl_reset_t rst) {
  const dt_sram_ctrl_reset_t count = kDtSramCtrlResetCount;
  if (rst >= count) {
    return kDtResetUnknown;
  }
  return TRY_GET_DT(dt, kDtResetUnknown)->reset[rst];
}