Software APIs
dt_rstmgr.h
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Device table API auto-generated by `dtgen`
6
7#ifndef OPENTITAN_DT_RSTMGR_H_
8#define OPENTITAN_DT_RSTMGR_H_
9
10#ifdef __cplusplus
11extern "C" {
12#endif // __cplusplus
13
14/**
15 * @file
16 * @brief Device Tables (DT) for IP rstmgr and top englishbreakfast.
17 *
18 * This file contains the type definitions and global functions of the rstmgr.
19 */
20
21#include "dt_api.h"
22#include <stdint.h>
23
24
25
26
27
28/**
29 * List of instances.
30 */
31typedef enum dt_rstmgr {
32 kDtRstmgrAon = 0, /**< rstmgr_aon */
33 kDtRstmgrFirst = 0, /**< \internal First instance */
34 kDtRstmgrCount = 1, /**< \internal Number of instances */
36
37/**
38 * List of register blocks.
39 *
40 * Register blocks are guaranteed to start at 0 and to be consecutively numbered.
41 */
42typedef enum dt_rstmgr_reg_block {
43 kDtRstmgrRegBlockCore = 0, /**< */
44 kDtRstmgrRegBlockCount = 1, /**< \internal Number of register blocks */
46
47/** Primary register block (associated with the "primary" set of registers that control the IP). */
48static const dt_rstmgr_reg_block_t kDtRstmgrRegBlockPrimary = kDtRstmgrRegBlockCore;
49
50/**
51 * List of clock ports.
52 *
53 * Clock ports are guaranteed to be numbered consecutively from 0.
54 */
55typedef enum dt_rstmgr_clock {
56 kDtRstmgrClockClk = 0, /**< Clock port clk_i */
57 kDtRstmgrClockAon = 1, /**< Clock port clk_aon_i */
58 kDtRstmgrClockIoDiv4 = 2, /**< Clock port clk_io_div4_i */
59 kDtRstmgrClockMain = 3, /**< Clock port clk_main_i */
60 kDtRstmgrClockIo = 4, /**< Clock port clk_io_i */
61 kDtRstmgrClockIoDiv2 = 5, /**< Clock port clk_io_div2_i */
62 kDtRstmgrClockUsb = 6, /**< Clock port clk_usb_i */
63 kDtRstmgrClockPor = 7, /**< Clock port clk_por_i */
64 kDtRstmgrClockCount = 8, /**< \internal Number of clock ports */
66
67/**
68 * List of reset ports.
69 *
70 * Reset ports are guaranteed to be numbered consecutively from 0.
71 */
72typedef enum dt_rstmgr_reset {
73 kDtRstmgrResetRst = 0, /**< Reset port rst_ni */
74 kDtRstmgrResetPor = 1, /**< Reset port rst_por_ni */
75 kDtRstmgrResetCount = 2, /**< \internal Number of reset ports */
77
78/**
79 * List of supported hardware features.
80 */
81#define OPENTITAN_RSTMGR_HAS_SW_RST_CHIP_RESET 1
82#define OPENTITAN_RSTMGR_HAS_SW_RST_SPI_DEVICE_REQUEST 1
83#define OPENTITAN_RSTMGR_HAS_SW_RST_SPI_DEVICE_ENABLE 1
84#define OPENTITAN_RSTMGR_HAS_SW_RST_SPI_HOST0_REQUEST 1
85#define OPENTITAN_RSTMGR_HAS_SW_RST_SPI_HOST0_ENABLE 1
86#define OPENTITAN_RSTMGR_HAS_SW_RST_USB_REQUEST 1
87#define OPENTITAN_RSTMGR_HAS_SW_RST_USB_ENABLE 1
88#define OPENTITAN_RSTMGR_HAS_RESET_INFO_CAPTURE 1
89#define OPENTITAN_RSTMGR_HAS_RESET_INFO_CLEAR 1
90#define OPENTITAN_RSTMGR_HAS_ALERT_INFO_CAPTURE 1
91#define OPENTITAN_RSTMGR_HAS_ALERT_INFO_ENABLE 1
92#define OPENTITAN_RSTMGR_HAS_CPU_INFO_CAPTURE 1
93#define OPENTITAN_RSTMGR_HAS_CPU_INFO_ENABLE 1
94#define OPENTITAN_RSTMGR_HAS_ALERT_HANDLER_RESET_STATUS 1
95
96
97
98/**
99 * Get the rstmgr instance from an instance ID
100 *
101 * For example, `dt_uart_from_instance_id(kDtInstanceIdUart3) == kDtUart3`.
102 *
103 * @param inst_id Instance ID.
104 * @return A rstmgr instance.
105 *
106 * **Note:** This function only makes sense if the instance ID has device type rstmgr,
107 * otherwise the returned value is unspecified.
108 */
110
111/**
112 * Get the instance ID of an instance.
113 *
114 * @param dt Instance of rstmgr.
115 * @return The instance ID of that instance.
116 */
118
119/**
120 * Get the register base address of an instance.
121 *
122 * @param dt Instance of rstmgr.
123 * @param reg_block The register block requested.
124 * @return The register base address of the requested block.
125 */
126uint32_t dt_rstmgr_reg_block(
127 dt_rstmgr_t dt,
128 dt_rstmgr_reg_block_t reg_block);
129
130/**
131 * Get the primary register base address of an instance.
132 *
133 * This is just a convenience function, equivalent to
134 * `dt_rstmgr_reg_block(dt, kDtRstmgrRegBlockCore)`
135 *
136 * @param dt Instance of rstmgr.
137 * @return The register base address of the primary register block.
138 */
139static inline uint32_t dt_rstmgr_primary_reg_block(
140 dt_rstmgr_t dt) {
141 return dt_rstmgr_reg_block(dt, kDtRstmgrRegBlockCore);
142}
143
144
145
146
147/**
148 * Get the clock signal connected to a clock port of an instance.
149 *
150 * @param dt Instance of rstmgr.
151 * @param clk Clock port.
152 * @return Clock signal.
153 */
155 dt_rstmgr_t dt,
157
158/**
159 * Get the reset signal connected to a reset port of an instance.
160 *
161 * @param dt Instance of rstmgr.
162 * @param rst Reset port.
163 * @return Reset signal.
164 */
166 dt_rstmgr_t dt,
168
169
170
171/**
172 * Get the number of software resets.
173 *
174 * @param dt Instance of rstmgr.
175 * @return Number of software resets.
176 */
178
179/**
180 * Get the reset ID of a software reset.
181 *
182 * The resets are ordered in the same way as they appear in the registers.
183 *
184 * @param dt Instance of rstmgr.
185 * @param idx Index of the software reset, between 0 and `dt_rstmgr_sw_reset_count(dt)-1`.
186 * @return Reset ID, or `kDtResetUnknown` for invalid parameters.
187 */
189
190/**
191 * Description of a reset request source.
192 *
193 * A reset request source is always identified by the instance ID of the module where it comes
194 * from. In principle, some instances could have several reset requests. If this is the case,
195 * the `rst_req` can be used to distinguish between those. It should be cast to the
196 * `dt_<ip>_reset_req_t` type of the corresponding IP.
197 *
198 * WARNING At the moment, three hardcoded reset requests are treated specially and have their
199 * `rst_req` field set to `0` because there is no corresponding reset request declared by those IPs:
200 * - the main power glitch reset request, coming from the `pwrmgr`,
201 * - the escalation reset request, coming from the `alert_handler`,
202 * - the non-debug-module reset request, coming from the `rv_dm`.
203 */
204typedef struct dt_rstmgr_reset_req_src {
205 dt_instance_id_t inst_id; /**< Instance ID of the source of this reset request. */
206 size_t reset_req; /**< Index of the reset request signal for that instance. */
208
209
210/**
211 * Get the number of hardware reset requests.
212 *
213 * @param dt Instance of rstmgr.
214 * @return Number of reset requests.
215 */
217
218/**
219 * Get the description of a reset request.
220 *
221 * The reset requests are ordered as they appear in the registers.
222 *
223 * @param dt Instance of rstmgr.
224 * @param idx Index of the reset request source, between 0 and
225 * `dt_pwrmgr_hw_reset_req_src_count(dt)-1`.
226 * @return Description of the reset.
227 */
229
230
231
232#ifdef __cplusplus
233} // extern "C"
234#endif // __cplusplus
235
236#endif // OPENTITAN_DT_RSTMGR_H_