dt_rstmgr.c

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// Copyright lowRISC contributors (OpenTitan project).
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Device table API auto-generated by `dtgen`
 
/**
 * @file
 * @brief Device Tables (DT) for IP rstmgr and top englishbreakfast.
 */
 
#include "hw/top/dt/dt_rstmgr.h"
 
 
#include "dt_aon_timer.h"
 
 
 
/**
 * Description of instances.
 */
typedef struct dt_desc_rstmgr {
  dt_instance_id_t inst_id; /**< Instance ID */
  uint32_t reg_addr[kDtRstmgrRegBlockCount]; /**< Base address of each register block */
  uint32_t mem_addr[kDtRstmgrMemoryCount]; /**< Base address of each memory */
  uint32_t mem_size[kDtRstmgrMemoryCount]; /**< Size in bytes of each memory */
  dt_clock_t clock[kDtRstmgrClockCount]; /**< Clock signal connected to each clock port */
  dt_reset_t reset[kDtRstmgrResetCount]; /**< Reset signal connected to each reset port */
  struct {
    dt_reset_t sw_rst[3]; /**< List of software resets, in the order of the register fields */
    dt_rstmgr_reset_req_src_t hw_req[4]; /**< List of hardware reset requests, in the order of the register fields */
  } rstmgr_ext; /**< Extension */
} dt_desc_rstmgr_t;
 
 
 
 
static const dt_desc_rstmgr_t rstmgr_desc[kDtRstmgrCount] = {
  [kDtRstmgrAon] = {
    .inst_id = kDtInstanceIdRstmgrAon,
    .reg_addr = {
      [kDtRstmgrRegBlockCore] = 0x40410000,
    },
    .mem_addr = {
    },
    .mem_size = {
    },
    .clock = {
      [kDtRstmgrClockClk] = kDtClockIoDiv4,
      [kDtRstmgrClockPor] = kDtClockIoDiv4,
      [kDtRstmgrClockAon] = kDtClockAon,
      [kDtRstmgrClockMain] = kDtClockMain,
      [kDtRstmgrClockIo] = kDtClockIo,
      [kDtRstmgrClockUsb] = kDtClockUsb,
      [kDtRstmgrClockIoDiv2] = kDtClockIoDiv2,
      [kDtRstmgrClockIoDiv4] = kDtClockIoDiv4,
    },
    .reset = {
      [kDtRstmgrResetRst] = kDtResetLcIoDiv4,
      [kDtRstmgrResetPor] = kDtResetPorIoDiv4,
    },
    .rstmgr_ext = {
      .sw_rst = {
        [0] = kDtResetSpiDevice,
        [1] = kDtResetSpiHost0,
        [2] = kDtResetUsb,
      },
      .hw_req = {
        [0] = {
          .inst_id = kDtInstanceIdAonTimerAon,
          .reset_req = kDtAonTimerResetReqAonTimer,
        },
        [1] = {
          .inst_id = kDtInstanceIdPwrmgrAon,
          .reset_req = 0,
        },
        [2] = {
          .inst_id = kDtInstanceIdUnknown,
          .reset_req = 0,
        },
        [3] = {
          .inst_id = kDtInstanceIdUnknown,
          .reset_req = 0,
        },
      },
    },
  },
};
 
/**
 * Return a pointer to the `dt_rstmgr_desc_t` structure of the requested
 * `dt` if it's a valid index. Otherwise, this macro will `return` (i.e. exit
 * the function) with the provided default value.
 */
#define TRY_GET_DT(dt, default)   ({     if ((dt) < (dt_rstmgr_t)0 || (dt) >= kDtRstmgrCount)       return (default);     &rstmgr_desc[dt];   })
 
dt_rstmgr_t dt_rstmgr_from_instance_id(dt_instance_id_t inst_id) {
  if (inst_id >= kDtInstanceIdRstmgrAon && inst_id <= kDtInstanceIdRstmgrAon) {
    return (dt_rstmgr_t)(inst_id - kDtInstanceIdRstmgrAon);
  }
  return (dt_rstmgr_t)0;
}
 
dt_instance_id_t dt_rstmgr_instance_id(
    dt_rstmgr_t dt) {
  return TRY_GET_DT(dt, kDtInstanceIdUnknown)->inst_id;
}
 
uint32_t dt_rstmgr_reg_block(
    dt_rstmgr_t dt,
    dt_rstmgr_reg_block_t reg_block) {
  // Return a recognizable address in case of wrong argument.
  return TRY_GET_DT(dt, 0xdeadbeef)->reg_addr[reg_block];
}
 
uint32_t dt_rstmgr_memory_base(
    dt_rstmgr_t dt,
    dt_rstmgr_memory_t mem) {
  // Return a recognizable address in case of wrong argument.
  return TRY_GET_DT(dt, 0xdeadbeef)->mem_addr[mem];
}
 
uint32_t dt_rstmgr_memory_size(
    dt_rstmgr_t dt,
    dt_rstmgr_memory_t mem)  {
  // Return an empty size in case of wrong argument.
  return TRY_GET_DT(dt, 0)->mem_size[mem];
}
 
 
 
 
dt_clock_t dt_rstmgr_clock(
    dt_rstmgr_t dt,
    dt_rstmgr_clock_t clk) {
  // Return the first clock in case of invalid argument.
  return TRY_GET_DT(dt, (dt_clock_t)0)->clock[clk];
}
 
dt_reset_t dt_rstmgr_reset(
    dt_rstmgr_t dt,
    dt_rstmgr_reset_t rst) {
  const dt_rstmgr_reset_t count = kDtRstmgrResetCount;
  if (rst >= count) {
    return kDtResetUnknown;
  }
  return TRY_GET_DT(dt, kDtResetUnknown)->reset[rst];
}
 
 
 
size_t dt_rstmgr_sw_reset_count(dt_rstmgr_t dt) {
  return 3;
}
 
dt_reset_t dt_rstmgr_sw_reset(dt_rstmgr_t dt, size_t idx) {
  if (idx >= 3) {
    return kDtResetUnknown;
  }
  return TRY_GET_DT(dt, kDtResetUnknown)->rstmgr_ext.sw_rst[idx];
}
 
size_t dt_rstmgr_hw_reset_req_src_count(dt_rstmgr_t dt) {
  return 4;
}
 
dt_rstmgr_reset_req_src_t dt_rstmgr_hw_reset_req_src(dt_rstmgr_t dt, size_t idx) {
  dt_rstmgr_reset_req_src_t invalid_req =   {
    .inst_id = kDtInstanceIdUnknown,
    .reset_req = kDtResetUnknown,
  };
  if (idx >= 4) {
    return invalid_req;
  }
  return TRY_GET_DT(dt, invalid_req)->rstmgr_ext.hw_req[idx];
}