Software APIs
dt_rom_ctrl.h
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Device table API auto-generated by `dtgen`
6
7#ifndef OPENTITAN_DT_ROM_CTRL_H_
8#define OPENTITAN_DT_ROM_CTRL_H_
9
10#ifdef __cplusplus
11extern "C" {
12#endif // __cplusplus
13
14/**
15 * @file
16 * @brief Device Tables (DT) for IP rom_ctrl and top englishbreakfast.
17 *
18 * This file contains the type definitions and global functions of the rom_ctrl.
19 */
20
21#include "dt_api.h"
22#include <stdint.h>
23
24
25
26/**
27 * List of instances.
28 */
29typedef enum dt_rom_ctrl {
30 kDtRomCtrl = 0, /**< rom_ctrl */
31 kDtRomCtrlFirst = 0, /**< \internal First instance */
32 kDtRomCtrlCount = 1, /**< \internal Number of instances */
34
35/**
36 * List of register blocks.
37 *
38 * Register blocks are guaranteed to start at 0 and to be consecutively numbered.
39 */
41 kDtRomCtrlRegBlockRegs = 0, /**< */
42 kDtRomCtrlRegBlockRom = 1, /**< */
43 kDtRomCtrlRegBlockCount = 2, /**< \internal Number of register blocks */
45
46/** Primary register block (associated with the "primary" set of registers that control the IP). */
47static const dt_rom_ctrl_reg_block_t kDtRomCtrlRegBlockPrimary = kDtRomCtrlRegBlockRegs;
48
49/**
50 * List of clock ports.
51 *
52 * Clock ports are guaranteed to be numbered consecutively from 0.
53 */
54typedef enum dt_rom_ctrl_clock {
55 kDtRomCtrlClockClk = 0, /**< Clock port clk_i */
56 kDtRomCtrlClockCount = 1, /**< \internal Number of clock ports */
58
59/**
60 * List of reset ports.
61 *
62 * Reset ports are guaranteed to be numbered consecutively from 0.
63 */
64typedef enum dt_rom_ctrl_reset {
65 kDtRomCtrlResetRst = 0, /**< Reset port rst_ni */
66 kDtRomCtrlResetCount = 1, /**< \internal Number of reset ports */
68
69/**
70 * List of supported hardware features.
71 */
72#define OPENTITAN_ROM_CTRL_HAS_SCRAMBLED 1
73#define OPENTITAN_ROM_CTRL_HAS_DIGESTS 1
74#define OPENTITAN_ROM_CTRL_HAS_EXP_DIGESTS 1
75
76
77
78/**
79 * Get the rom_ctrl instance from an instance ID
80 *
81 * For example, `dt_uart_from_instance_id(kDtInstanceIdUart3) == kDtUart3`.
82 *
83 * @param inst_id Instance ID.
84 * @return A rom_ctrl instance.
85 *
86 * **Note:** This function only makes sense if the instance ID has device type rom_ctrl,
87 * otherwise the returned value is unspecified.
88 */
90
91/**
92 * Get the instance ID of an instance.
93 *
94 * @param dt Instance of rom_ctrl.
95 * @return The instance ID of that instance.
96 */
98
99/**
100 * Get the register base address of an instance.
101 *
102 * @param dt Instance of rom_ctrl.
103 * @param reg_block The register block requested.
104 * @return The register base address of the requested block.
105 */
106uint32_t dt_rom_ctrl_reg_block(
107 dt_rom_ctrl_t dt,
108 dt_rom_ctrl_reg_block_t reg_block);
109
110/**
111 * Get the primary register base address of an instance.
112 *
113 * This is just a convenience function, equivalent to
114 * `dt_rom_ctrl_reg_block(dt, kDtRomCtrlRegBlockRegs)`
115 *
116 * @param dt Instance of rom_ctrl.
117 * @return The register base address of the primary register block.
118 */
119static inline uint32_t dt_rom_ctrl_primary_reg_block(
120 dt_rom_ctrl_t dt) {
121 return dt_rom_ctrl_reg_block(dt, kDtRomCtrlRegBlockRegs);
122}
123
124
125
126
127/**
128 * Get the clock signal connected to a clock port of an instance.
129 *
130 * @param dt Instance of rom_ctrl.
131 * @param clk Clock port.
132 * @return Clock signal.
133 */
135 dt_rom_ctrl_t dt,
137
138/**
139 * Get the reset signal connected to a reset port of an instance.
140 *
141 * @param dt Instance of rom_ctrl.
142 * @param rst Reset port.
143 * @return Reset signal.
144 */
146 dt_rom_ctrl_t dt,
148
149
150
151#ifdef __cplusplus
152} // extern "C"
153#endif // __cplusplus
154
155#endif // OPENTITAN_DT_ROM_CTRL_H_