Software APIs
dt_gpio.h
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Device table API auto-generated by `dtgen`
6
7#ifndef OPENTITAN_DT_GPIO_H_
8#define OPENTITAN_DT_GPIO_H_
9
10/**
11 * @file
12 * @brief Device Tables (DT) for IP gpio and top englishbreakfast.
13 *
14 * This file contains the type definitions and global functions of the gpio.
15 */
16
17#include "dt_api.h"
18#include <stdint.h>
19
20
21
22
23
24/**
25 * List of instances.
26 */
27typedef enum dt_gpio {
28 kDtGpio = 0, /**< gpio */
29 kDtGpioFirst = 0, /**< \internal First instance */
30 kDtGpioCount = 1, /**< \internal Number of instances */
31} dt_gpio_t;
32
33/**
34 * List of register blocks.
35 *
36 * Register blocks are guaranteed to start at 0 and to be consecutively numbered.
37 */
38typedef enum dt_gpio_reg_block {
39 kDtGpioRegBlockCore = 0, /**< */
40 kDtGpioRegBlockCount = 1, /**< \internal Number of register blocks */
41} dt_gpio_reg_block_t;
42
43/** Primary register block (associated with the "primary" set of registers that control the IP). */
44static const dt_gpio_reg_block_t kDtGpioRegBlockPrimary = kDtGpioRegBlockCore;
45
46/**
47 * List of IRQs.
48 *
49 * IRQs are guaranteed to be numbered consecutively from 0.
50 */
51typedef enum dt_gpio_irq {
52 kDtGpioIrqGpio0 = 0, /**< raised if any of GPIO pin detects configured interrupt mode */
53 kDtGpioIrqGpio1 = 1, /**< raised if any of GPIO pin detects configured interrupt mode */
54 kDtGpioIrqGpio2 = 2, /**< raised if any of GPIO pin detects configured interrupt mode */
55 kDtGpioIrqGpio3 = 3, /**< raised if any of GPIO pin detects configured interrupt mode */
56 kDtGpioIrqGpio4 = 4, /**< raised if any of GPIO pin detects configured interrupt mode */
57 kDtGpioIrqGpio5 = 5, /**< raised if any of GPIO pin detects configured interrupt mode */
58 kDtGpioIrqGpio6 = 6, /**< raised if any of GPIO pin detects configured interrupt mode */
59 kDtGpioIrqGpio7 = 7, /**< raised if any of GPIO pin detects configured interrupt mode */
60 kDtGpioIrqGpio8 = 8, /**< raised if any of GPIO pin detects configured interrupt mode */
61 kDtGpioIrqGpio9 = 9, /**< raised if any of GPIO pin detects configured interrupt mode */
62 kDtGpioIrqGpio10 = 10, /**< raised if any of GPIO pin detects configured interrupt mode */
63 kDtGpioIrqGpio11 = 11, /**< raised if any of GPIO pin detects configured interrupt mode */
64 kDtGpioIrqGpio12 = 12, /**< raised if any of GPIO pin detects configured interrupt mode */
65 kDtGpioIrqGpio13 = 13, /**< raised if any of GPIO pin detects configured interrupt mode */
66 kDtGpioIrqGpio14 = 14, /**< raised if any of GPIO pin detects configured interrupt mode */
67 kDtGpioIrqGpio15 = 15, /**< raised if any of GPIO pin detects configured interrupt mode */
68 kDtGpioIrqGpio16 = 16, /**< raised if any of GPIO pin detects configured interrupt mode */
69 kDtGpioIrqGpio17 = 17, /**< raised if any of GPIO pin detects configured interrupt mode */
70 kDtGpioIrqGpio18 = 18, /**< raised if any of GPIO pin detects configured interrupt mode */
71 kDtGpioIrqGpio19 = 19, /**< raised if any of GPIO pin detects configured interrupt mode */
72 kDtGpioIrqGpio20 = 20, /**< raised if any of GPIO pin detects configured interrupt mode */
73 kDtGpioIrqGpio21 = 21, /**< raised if any of GPIO pin detects configured interrupt mode */
74 kDtGpioIrqGpio22 = 22, /**< raised if any of GPIO pin detects configured interrupt mode */
75 kDtGpioIrqGpio23 = 23, /**< raised if any of GPIO pin detects configured interrupt mode */
76 kDtGpioIrqGpio24 = 24, /**< raised if any of GPIO pin detects configured interrupt mode */
77 kDtGpioIrqGpio25 = 25, /**< raised if any of GPIO pin detects configured interrupt mode */
78 kDtGpioIrqGpio26 = 26, /**< raised if any of GPIO pin detects configured interrupt mode */
79 kDtGpioIrqGpio27 = 27, /**< raised if any of GPIO pin detects configured interrupt mode */
80 kDtGpioIrqGpio28 = 28, /**< raised if any of GPIO pin detects configured interrupt mode */
81 kDtGpioIrqGpio29 = 29, /**< raised if any of GPIO pin detects configured interrupt mode */
82 kDtGpioIrqGpio30 = 30, /**< raised if any of GPIO pin detects configured interrupt mode */
83 kDtGpioIrqGpio31 = 31, /**< raised if any of GPIO pin detects configured interrupt mode */
84 kDtGpioIrqCount = 32, /**< \internal Number of IRQs */
85} dt_gpio_irq_t;
86
87/**
88 * List of clock ports.
89 *
90 * Clock ports are guaranteed to be numbered consecutively from 0.
91 */
92typedef enum dt_gpio_clock {
93 kDtGpioClockClk = 0, /**< Clock port clk_i */
94 kDtGpioClockCount = 1, /**< \internal Number of clock ports */
95} dt_gpio_clock_t;
96
97/**
98 * List of reset ports.
99 *
100 * Reset ports are guaranteed to be numbered consecutively from 0.
101 */
102typedef enum dt_gpio_reset {
103 kDtGpioResetRst = 0, /**< Reset port rst_ni */
104 kDtGpioResetCount = 1, /**< \internal Number of reset ports */
105} dt_gpio_reset_t;
106
107/**
108 * List of peripheral I/O.
109 *
110 * Peripheral I/O are guaranteed to be numbered consecutively from 0.
111 */
112typedef enum dt_gpio_periph_io {
113 kDtGpioPeriphIoGpio0 = 0, /**< */
114 kDtGpioPeriphIoGpio1 = 1, /**< */
115 kDtGpioPeriphIoGpio2 = 2, /**< */
116 kDtGpioPeriphIoGpio3 = 3, /**< */
117 kDtGpioPeriphIoGpio4 = 4, /**< */
118 kDtGpioPeriphIoGpio5 = 5, /**< */
119 kDtGpioPeriphIoGpio6 = 6, /**< */
120 kDtGpioPeriphIoGpio7 = 7, /**< */
121 kDtGpioPeriphIoGpio8 = 8, /**< */
122 kDtGpioPeriphIoGpio9 = 9, /**< */
123 kDtGpioPeriphIoGpio10 = 10, /**< */
124 kDtGpioPeriphIoGpio11 = 11, /**< */
125 kDtGpioPeriphIoGpio12 = 12, /**< */
126 kDtGpioPeriphIoGpio13 = 13, /**< */
127 kDtGpioPeriphIoGpio14 = 14, /**< */
128 kDtGpioPeriphIoGpio15 = 15, /**< */
129 kDtGpioPeriphIoGpio16 = 16, /**< */
130 kDtGpioPeriphIoGpio17 = 17, /**< */
131 kDtGpioPeriphIoGpio18 = 18, /**< */
132 kDtGpioPeriphIoGpio19 = 19, /**< */
133 kDtGpioPeriphIoGpio20 = 20, /**< */
134 kDtGpioPeriphIoGpio21 = 21, /**< */
135 kDtGpioPeriphIoGpio22 = 22, /**< */
136 kDtGpioPeriphIoGpio23 = 23, /**< */
137 kDtGpioPeriphIoGpio24 = 24, /**< */
138 kDtGpioPeriphIoGpio25 = 25, /**< */
139 kDtGpioPeriphIoGpio26 = 26, /**< */
140 kDtGpioPeriphIoGpio27 = 27, /**< */
141 kDtGpioPeriphIoGpio28 = 28, /**< */
142 kDtGpioPeriphIoGpio29 = 29, /**< */
143 kDtGpioPeriphIoGpio30 = 30, /**< */
144 kDtGpioPeriphIoGpio31 = 31, /**< */
145 kDtGpioPeriphIoCount = 32, /**< \internal Number of peripheral I/O */
146} dt_gpio_periph_io_t;
147
148/**
149 * List of supported hardware features.
150 */
151#define OPENTITAN_GPIO_HAS_IN_INTR_CTRL 1
152#define OPENTITAN_GPIO_HAS_IN_FILTER 1
153#define OPENTITAN_GPIO_HAS_OUT_MASK 1
154
155
156
157/**
158 * Get the gpio instance from an instance ID
159 *
160 * For example, `dt_uart_from_instance_id(kDtInstanceIdUart3) == kDtUart3`.
161 *
162 * @param inst_id Instance ID.
163 * @return A gpio instance.
164 *
165 * **Note:** This function only makes sense if the instance ID has device type gpio,
166 * otherwise the returned value is unspecified.
167 */
168dt_gpio_t dt_gpio_from_instance_id(dt_instance_id_t inst_id);
169
170/**
171 * Get the instance ID of an instance.
172 *
173 * @param dt Instance of gpio.
174 * @return The instance ID of that instance.
175 */
176dt_instance_id_t dt_gpio_instance_id(dt_gpio_t dt);
177
178/**
179 * Get the register base address of an instance.
180 *
181 * @param dt Instance of gpio.
182 * @param reg_block The register block requested.
183 * @return The register base address of the requested block.
184 */
185uint32_t dt_gpio_reg_block(
186 dt_gpio_t dt,
187 dt_gpio_reg_block_t reg_block);
188
189/**
190 * Get the primary register base address of an instance.
191 *
192 * This is just a convenience function, equivalent to
193 * `dt_gpio_reg_block(dt, kDtGpioRegBlockCore)`
194 *
195 * @param dt Instance of gpio.
196 * @return The register base address of the primary register block.
197 */
198static inline uint32_t dt_gpio_primary_reg_block(
199 dt_gpio_t dt) {
200 return dt_gpio_reg_block(dt, kDtGpioRegBlockCore);
201}
202
203/**
204 * Get the PLIC ID of a gpio IRQ for a given instance.
205 *
206 * If the instance is not connected to the PLIC, this function
207 * will return `kDtPlicIrqIdNone`.
208 *
209 * @param dt Instance of gpio.
210 * @param irq A gpio IRQ.
211 * @return The PLIC ID of the IRQ of this instance.
212 */
213dt_plic_irq_id_t dt_gpio_irq_to_plic_id(
214 dt_gpio_t dt,
215 dt_gpio_irq_t irq);
216
217/**
218 * Convert a global IRQ ID to a local gpio IRQ type.
219 *
220 * @param dt Instance of gpio.
221 * @param irq A PLIC ID that belongs to this instance.
222 * @return The gpio IRQ, or `kDtGpioIrqCount`.
223 *
224 * **Note:** This function assumes that the PLIC ID belongs to the instance
225 * of gpio passed in parameter. In other words, it must be the case that
226 * `dt_gpio_instance_id(dt) == dt_plic_id_to_instance_id(irq)`. Otherwise, this function
227 * will return `kDtGpioIrqCount`.
228 */
229dt_gpio_irq_t dt_gpio_irq_from_plic_id(
230 dt_gpio_t dt,
231 dt_plic_irq_id_t irq);
232
233
234
235/**
236 * Get the peripheral I/O description of an instance.
237 *
238 * @param dt Instance of gpio.
239 * @param sig Requested peripheral I/O.
240 * @return Description of the requested peripheral I/O for this instance.
241 */
242dt_periph_io_t dt_gpio_periph_io(
243 dt_gpio_t dt,
244 dt_gpio_periph_io_t sig);
245
246/**
247 * Get the clock signal connected to a clock port of an instance.
248 *
249 * @param dt Instance of gpio.
250 * @param clk Clock port.
251 * @return Clock signal.
252 */
253dt_clock_t dt_gpio_clock(
254 dt_gpio_t dt,
255 dt_gpio_clock_t clk);
256
257/**
258 * Get the reset signal connected to a reset port of an instance.
259 *
260 * @param dt Instance of gpio.
261 * @param rst Reset port.
262 * @return Reset signal.
263 */
264dt_reset_t dt_gpio_reset(
265 dt_gpio_t dt,
266 dt_gpio_reset_t rst);
267
268
269
270/**
271 * Get the number of input period counters.
272 *
273 * @param dt Instance of gpio.
274 * @return number of input period counters.
275 */
276uint8_t dt_gpio_input_period_counter_count(dt_gpio_t dt);
277
278
279
280#endif // OPENTITAN_DT_GPIO_H_