Software APIs
dt_gpio.h
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Device table API auto-generated by `dtgen`
6
7#ifndef OPENTITAN_DT_GPIO_H_
8#define OPENTITAN_DT_GPIO_H_
9
10/**
11 * @file
12 * @brief Device Tables (DT) for IP gpio and top englishbreakfast.
13 *
14 * This file contains the type definitions and global functions of the gpio.
15 */
16
17#include "dt_api.h"
18#include <stdint.h>
19
20/**
21 * List of instances.
22 */
23typedef enum dt_gpio {
24 kDtGpio = 0, /**< gpio */
25 kDtGpioFirst = 0, /**< \internal First instance */
26 kDtGpioCount = 1, /**< \internal Number of instances */
27} dt_gpio_t;
28
29/**
30 * List of register blocks.
31 *
32 * Register blocks are guaranteed to start at 0 and to be consecutively numbered.
33 */
34typedef enum dt_gpio_reg_block {
35 kDtGpioRegBlockCore = 0, /**< */
36 kDtGpioRegBlockCount = 1, /**< \internal Number of register blocks */
37} dt_gpio_reg_block_t;
38
39/** Primary register block (associated with the "primary" set of registers that control the IP). */
40static const dt_gpio_reg_block_t kDtGpioRegBlockPrimary = kDtGpioRegBlockCore;
41
42/**
43 * List of IRQs.
44 *
45 * IRQs are guaranteed to be numbered consecutively from 0.
46 */
47typedef enum dt_gpio_irq {
48 kDtGpioIrqGpio0 = 0, /**< raised if any of GPIO pin detects configured interrupt mode */
49 kDtGpioIrqGpio1 = 1, /**< raised if any of GPIO pin detects configured interrupt mode */
50 kDtGpioIrqGpio2 = 2, /**< raised if any of GPIO pin detects configured interrupt mode */
51 kDtGpioIrqGpio3 = 3, /**< raised if any of GPIO pin detects configured interrupt mode */
52 kDtGpioIrqGpio4 = 4, /**< raised if any of GPIO pin detects configured interrupt mode */
53 kDtGpioIrqGpio5 = 5, /**< raised if any of GPIO pin detects configured interrupt mode */
54 kDtGpioIrqGpio6 = 6, /**< raised if any of GPIO pin detects configured interrupt mode */
55 kDtGpioIrqGpio7 = 7, /**< raised if any of GPIO pin detects configured interrupt mode */
56 kDtGpioIrqGpio8 = 8, /**< raised if any of GPIO pin detects configured interrupt mode */
57 kDtGpioIrqGpio9 = 9, /**< raised if any of GPIO pin detects configured interrupt mode */
58 kDtGpioIrqGpio10 = 10, /**< raised if any of GPIO pin detects configured interrupt mode */
59 kDtGpioIrqGpio11 = 11, /**< raised if any of GPIO pin detects configured interrupt mode */
60 kDtGpioIrqGpio12 = 12, /**< raised if any of GPIO pin detects configured interrupt mode */
61 kDtGpioIrqGpio13 = 13, /**< raised if any of GPIO pin detects configured interrupt mode */
62 kDtGpioIrqGpio14 = 14, /**< raised if any of GPIO pin detects configured interrupt mode */
63 kDtGpioIrqGpio15 = 15, /**< raised if any of GPIO pin detects configured interrupt mode */
64 kDtGpioIrqGpio16 = 16, /**< raised if any of GPIO pin detects configured interrupt mode */
65 kDtGpioIrqGpio17 = 17, /**< raised if any of GPIO pin detects configured interrupt mode */
66 kDtGpioIrqGpio18 = 18, /**< raised if any of GPIO pin detects configured interrupt mode */
67 kDtGpioIrqGpio19 = 19, /**< raised if any of GPIO pin detects configured interrupt mode */
68 kDtGpioIrqGpio20 = 20, /**< raised if any of GPIO pin detects configured interrupt mode */
69 kDtGpioIrqGpio21 = 21, /**< raised if any of GPIO pin detects configured interrupt mode */
70 kDtGpioIrqGpio22 = 22, /**< raised if any of GPIO pin detects configured interrupt mode */
71 kDtGpioIrqGpio23 = 23, /**< raised if any of GPIO pin detects configured interrupt mode */
72 kDtGpioIrqGpio24 = 24, /**< raised if any of GPIO pin detects configured interrupt mode */
73 kDtGpioIrqGpio25 = 25, /**< raised if any of GPIO pin detects configured interrupt mode */
74 kDtGpioIrqGpio26 = 26, /**< raised if any of GPIO pin detects configured interrupt mode */
75 kDtGpioIrqGpio27 = 27, /**< raised if any of GPIO pin detects configured interrupt mode */
76 kDtGpioIrqGpio28 = 28, /**< raised if any of GPIO pin detects configured interrupt mode */
77 kDtGpioIrqGpio29 = 29, /**< raised if any of GPIO pin detects configured interrupt mode */
78 kDtGpioIrqGpio30 = 30, /**< raised if any of GPIO pin detects configured interrupt mode */
79 kDtGpioIrqGpio31 = 31, /**< raised if any of GPIO pin detects configured interrupt mode */
80 kDtGpioIrqCount = 32, /**< \internal Number of IRQs */
81} dt_gpio_irq_t;
82
83/**
84 * List of clock ports.
85 *
86 * Clock ports are guaranteed to be numbered consecutively from 0.
87 */
88typedef enum dt_gpio_clock {
89 kDtGpioClockClk = 0, /**< Clock port clk_i */
90 kDtGpioClockCount = 1, /**< \internal Number of clock ports */
91} dt_gpio_clock_t;
92
93/**
94 * List of reset ports.
95 *
96 * Reset ports are guaranteed to be numbered consecutively from 0.
97 */
98typedef enum dt_gpio_reset {
99 kDtGpioResetRst = 0, /**< Reset port rst_ni */
100 kDtGpioResetCount = 1, /**< \internal Number of reset ports */
101} dt_gpio_reset_t;
102
103/**
104 * List of peripheral I/O.
105 *
106 * Peripheral I/O are guaranteed to be numbered consecutively from 0.
107 */
108typedef enum dt_gpio_periph_io {
109 kDtGpioPeriphIoGpio0 = 0, /**< */
110 kDtGpioPeriphIoGpio1 = 1, /**< */
111 kDtGpioPeriphIoGpio2 = 2, /**< */
112 kDtGpioPeriphIoGpio3 = 3, /**< */
113 kDtGpioPeriphIoGpio4 = 4, /**< */
114 kDtGpioPeriphIoGpio5 = 5, /**< */
115 kDtGpioPeriphIoGpio6 = 6, /**< */
116 kDtGpioPeriphIoGpio7 = 7, /**< */
117 kDtGpioPeriphIoGpio8 = 8, /**< */
118 kDtGpioPeriphIoGpio9 = 9, /**< */
119 kDtGpioPeriphIoGpio10 = 10, /**< */
120 kDtGpioPeriphIoGpio11 = 11, /**< */
121 kDtGpioPeriphIoGpio12 = 12, /**< */
122 kDtGpioPeriphIoGpio13 = 13, /**< */
123 kDtGpioPeriphIoGpio14 = 14, /**< */
124 kDtGpioPeriphIoGpio15 = 15, /**< */
125 kDtGpioPeriphIoGpio16 = 16, /**< */
126 kDtGpioPeriphIoGpio17 = 17, /**< */
127 kDtGpioPeriphIoGpio18 = 18, /**< */
128 kDtGpioPeriphIoGpio19 = 19, /**< */
129 kDtGpioPeriphIoGpio20 = 20, /**< */
130 kDtGpioPeriphIoGpio21 = 21, /**< */
131 kDtGpioPeriphIoGpio22 = 22, /**< */
132 kDtGpioPeriphIoGpio23 = 23, /**< */
133 kDtGpioPeriphIoGpio24 = 24, /**< */
134 kDtGpioPeriphIoGpio25 = 25, /**< */
135 kDtGpioPeriphIoGpio26 = 26, /**< */
136 kDtGpioPeriphIoGpio27 = 27, /**< */
137 kDtGpioPeriphIoGpio28 = 28, /**< */
138 kDtGpioPeriphIoGpio29 = 29, /**< */
139 kDtGpioPeriphIoGpio30 = 30, /**< */
140 kDtGpioPeriphIoGpio31 = 31, /**< */
141 kDtGpioPeriphIoCount = 32, /**< \internal Number of peripheral I/O */
142} dt_gpio_periph_io_t;
143
144/**
145 * List of supported hardware features.
146 */
147#define OPENTITAN_GPIO_HAS_IN_INTR_CTRL 1
148#define OPENTITAN_GPIO_HAS_IN_FILTER 1
149#define OPENTITAN_GPIO_HAS_OUT_MASK 1
150
151
152
153/**
154 * Get the gpio instance from an instance ID
155 *
156 * For example, `dt_uart_from_instance_id(kDtInstanceIdUart3) == kDtUart3`.
157 *
158 * @param inst_id Instance ID.
159 * @return A gpio instance.
160 *
161 * **Note:** This function only makes sense if the instance ID has device type gpio,
162 * otherwise the returned value is unspecified.
163 */
164dt_gpio_t dt_gpio_from_instance_id(dt_instance_id_t inst_id);
165
166/**
167 * Get the instance ID of an instance.
168 *
169 * @param dt Instance of gpio.
170 * @return The instance ID of that instance.
171 */
172dt_instance_id_t dt_gpio_instance_id(dt_gpio_t dt);
173
174/**
175 * Get the register base address of an instance.
176 *
177 * @param dt Instance of gpio.
178 * @param reg_block The register block requested.
179 * @return The register base address of the requested block.
180 */
181uint32_t dt_gpio_reg_block(
182 dt_gpio_t dt,
183 dt_gpio_reg_block_t reg_block);
184
185/**
186 * Get the primary register base address of an instance.
187 *
188 * This is just a convenience function, equivalent to
189 * `dt_gpio_reg_block(dt, kDtGpioRegBlockCore)`
190 *
191 * @param dt Instance of gpio.
192 * @return The register base address of the primary register block.
193 */
194static inline uint32_t dt_gpio_primary_reg_block(
195 dt_gpio_t dt) {
196 return dt_gpio_reg_block(dt, kDtGpioRegBlockCore);
197}
198
199/**
200 * Get the PLIC ID of a gpio IRQ for a given instance.
201 *
202 * If the instance is not connected to the PLIC, this function
203 * will return `kDtPlicIrqIdNone`.
204 *
205 * @param dt Instance of gpio.
206 * @param irq A gpio IRQ.
207 * @return The PLIC ID of the IRQ of this instance.
208 */
209dt_plic_irq_id_t dt_gpio_irq_to_plic_id(
210 dt_gpio_t dt,
211 dt_gpio_irq_t irq);
212
213/**
214 * Convert a global IRQ ID to a local gpio IRQ type.
215 *
216 * @param dt Instance of gpio.
217 * @param irq A PLIC ID that belongs to this instance.
218 * @return The gpio IRQ, or `kDtGpioIrqCount`.
219 *
220 * **Note:** This function assumes that the PLIC ID belongs to the instance
221 * of gpio passed in parameter. In other words, it must be the case that
222 * `dt_gpio_instance_id(dt) == dt_plic_id_to_instance_id(irq)`. Otherwise, this function
223 * will return `kDtGpioIrqCount`.
224 */
225dt_gpio_irq_t dt_gpio_irq_from_plic_id(
226 dt_gpio_t dt,
227 dt_plic_irq_id_t irq);
228
229
230
231/**
232 * Get the peripheral I/O description of an instance.
233 *
234 * @param dt Instance of gpio.
235 * @param sig Requested peripheral I/O.
236 * @return Description of the requested peripheral I/O for this instance.
237 */
238dt_periph_io_t dt_gpio_periph_io(
239 dt_gpio_t dt,
240 dt_gpio_periph_io_t sig);
241
242/**
243 * Get the clock signal connected to a clock port of an instance.
244 *
245 * @param dt Instance of gpio.
246 * @param clk Clock port.
247 * @return Clock signal.
248 */
249dt_clock_t dt_gpio_clock(
250 dt_gpio_t dt,
251 dt_gpio_clock_t clk);
252
253/**
254 * Get the reset signal connected to a reset port of an instance.
255 *
256 * @param dt Instance of gpio.
257 * @param rst Reset port.
258 * @return Reset signal.
259 */
260dt_reset_t dt_gpio_reset(
261 dt_gpio_t dt,
262 dt_gpio_reset_t rst);
263
264
265
266/**
267 * Get the number of input period counters.
268 *
269 * @param dt Instance of gpio.
270 * @return number of input period counters.
271 */
272uint8_t dt_gpio_input_period_counter_count(dt_gpio_t dt);
273
274
275
276#endif // OPENTITAN_DT_GPIO_H_