Software APIs
dt_flash_ctrl.h
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Device table API auto-generated by `dtgen`
6
7#ifndef OPENTITAN_DT_FLASH_CTRL_H_
8#define OPENTITAN_DT_FLASH_CTRL_H_
9
10/**
11 * @file
12 * @brief Device Tables (DT) for IP flash_ctrl and top englishbreakfast.
13 *
14 * This file contains the type definitions and global functions of the flash_ctrl.
15 */
16
17#include "dt_api.h"
18#include <stdint.h>
19
20
21
22/**
23 * List of instances.
24 */
25typedef enum dt_flash_ctrl {
26 kDtFlashCtrl = 0, /**< flash_ctrl */
27 kDtFlashCtrlFirst = 0, /**< \internal First instance */
28 kDtFlashCtrlCount = 1, /**< \internal Number of instances */
30
31/**
32 * List of register blocks.
33 *
34 * Register blocks are guaranteed to start at 0 and to be consecutively numbered.
35 */
37 kDtFlashCtrlRegBlockCore = 0, /**< */
38 kDtFlashCtrlRegBlockPrim = 1, /**< */
39 kDtFlashCtrlRegBlockMem = 2, /**< */
40 kDtFlashCtrlRegBlockCount = 3, /**< \internal Number of register blocks */
42
43/** Primary register block (associated with the "primary" set of registers that control the IP). */
44static const dt_flash_ctrl_reg_block_t kDtFlashCtrlRegBlockPrimary = kDtFlashCtrlRegBlockCore;
45
46/**
47 * List of IRQs.
48 *
49 * IRQs are guaranteed to be numbered consecutively from 0.
50 */
51typedef enum dt_flash_ctrl_irq {
52 kDtFlashCtrlIrqProgEmpty = 0, /**< Program FIFO empty */
53 kDtFlashCtrlIrqProgLvl = 1, /**< Program FIFO drained to level */
54 kDtFlashCtrlIrqRdFull = 2, /**< Read FIFO full */
55 kDtFlashCtrlIrqRdLvl = 3, /**< Read FIFO filled to level */
56 kDtFlashCtrlIrqOpDone = 4, /**< Operation complete */
57 kDtFlashCtrlIrqCorrErr = 5, /**< Correctable error encountered */
58 kDtFlashCtrlIrqCount = 6, /**< \internal Number of IRQs */
60
61/**
62 * List of clock ports.
63 *
64 * Clock ports are guaranteed to be numbered consecutively from 0.
65 */
66typedef enum dt_flash_ctrl_clock {
67 kDtFlashCtrlClockClk = 0, /**< Clock port clk_i */
68 kDtFlashCtrlClockOtp = 1, /**< Clock port clk_otp_i */
69 kDtFlashCtrlClockCount = 2, /**< \internal Number of clock ports */
71
72/**
73 * List of reset ports.
74 *
75 * Reset ports are guaranteed to be numbered consecutively from 0.
76 */
77typedef enum dt_flash_ctrl_reset {
78 kDtFlashCtrlResetRst = 0, /**< Reset port rst_ni */
79 kDtFlashCtrlResetOtp = 1, /**< Reset port rst_otp_ni */
80 kDtFlashCtrlResetCount = 2, /**< \internal Number of reset ports */
82
83/**
84 * List of peripheral I/O.
85 *
86 * Peripheral I/O are guaranteed to be numbered consecutively from 0.
87 */
89 kDtFlashCtrlPeriphIoTck = 0, /**< */
90 kDtFlashCtrlPeriphIoTms = 1, /**< */
91 kDtFlashCtrlPeriphIoTdi = 2, /**< */
92 kDtFlashCtrlPeriphIoTdo = 3, /**< */
93 kDtFlashCtrlPeriphIoCount = 4, /**< \internal Number of peripheral I/O */
95
96/**
97 * List of supported hardware features.
98 */
99#define OPENTITAN_FLASH_CTRL_HAS_ESCALATION 1
100#define OPENTITAN_FLASH_CTRL_HAS_FETCH_CODE 1
101#define OPENTITAN_FLASH_CTRL_HAS_INFO_CREATOR_PARTITION 1
102#define OPENTITAN_FLASH_CTRL_HAS_INFO_ISOLATED_PARTITION 1
103#define OPENTITAN_FLASH_CTRL_HAS_INFO_OWNER_PARTITION 1
104#define OPENTITAN_FLASH_CTRL_HAS_INIT_ROOT_SEEDS 1
105#define OPENTITAN_FLASH_CTRL_HAS_INIT_SCRAMBLING_KEYS 1
106#define OPENTITAN_FLASH_CTRL_HAS_MEM_PROTECTION 1
107#define OPENTITAN_FLASH_CTRL_HAS_OP_HOST_READ 1
108#define OPENTITAN_FLASH_CTRL_HAS_OP_PROTOCOL_CTRL 1
109#define OPENTITAN_FLASH_CTRL_HAS_RMA 1
110
111
112
113/**
114 * Get the flash_ctrl instance from an instance ID
115 *
116 * For example, `dt_uart_from_instance_id(kDtInstanceIdUart3) == kDtUart3`.
117 *
118 * @param inst_id Instance ID.
119 * @return A flash_ctrl instance.
120 *
121 * **Note:** This function only makes sense if the instance ID has device type flash_ctrl,
122 * otherwise the returned value is unspecified.
123 */
125
126/**
127 * Get the instance ID of an instance.
128 *
129 * @param dt Instance of flash_ctrl.
130 * @return The instance ID of that instance.
131 */
133
134/**
135 * Get the register base address of an instance.
136 *
137 * @param dt Instance of flash_ctrl.
138 * @param reg_block The register block requested.
139 * @return The register base address of the requested block.
140 */
143 dt_flash_ctrl_reg_block_t reg_block);
144
145/**
146 * Get the primary register base address of an instance.
147 *
148 * This is just a convenience function, equivalent to
149 * `dt_flash_ctrl_reg_block(dt, kDtFlashCtrlRegBlockCore)`
150 *
151 * @param dt Instance of flash_ctrl.
152 * @return The register base address of the primary register block.
153 */
154static inline uint32_t dt_flash_ctrl_primary_reg_block(
155 dt_flash_ctrl_t dt) {
156 return dt_flash_ctrl_reg_block(dt, kDtFlashCtrlRegBlockCore);
157}
158
159/**
160 * Get the PLIC ID of a flash_ctrl IRQ for a given instance.
161 *
162 * If the instance is not connected to the PLIC, this function
163 * will return `kDtPlicIrqIdNone`.
164 *
165 * @param dt Instance of flash_ctrl.
166 * @param irq A flash_ctrl IRQ.
167 * @return The PLIC ID of the IRQ of this instance.
168 */
172
173/**
174 * Convert a global IRQ ID to a local flash_ctrl IRQ type.
175 *
176 * @param dt Instance of flash_ctrl.
177 * @param irq A PLIC ID that belongs to this instance.
178 * @return The flash_ctrl IRQ, or `kDtFlashCtrlIrqCount`.
179 *
180 * **Note:** This function assumes that the PLIC ID belongs to the instance
181 * of flash_ctrl passed in parameter. In other words, it must be the case that
182 * `dt_flash_ctrl_instance_id(dt) == dt_plic_id_to_instance_id(irq)`. Otherwise, this function
183 * will return `kDtFlashCtrlIrqCount`.
184 */
187 dt_plic_irq_id_t irq);
188
189
190
191/**
192 * Get the peripheral I/O description of an instance.
193 *
194 * @param dt Instance of flash_ctrl.
195 * @param sig Requested peripheral I/O.
196 * @return Description of the requested peripheral I/O for this instance.
197 */
201
202/**
203 * Get the clock signal connected to a clock port of an instance.
204 *
205 * @param dt Instance of flash_ctrl.
206 * @param clk Clock port.
207 * @return Clock signal.
208 */
212
213/**
214 * Get the reset signal connected to a reset port of an instance.
215 *
216 * @param dt Instance of flash_ctrl.
217 * @param rst Reset port.
218 * @return Reset signal.
219 */
223
224
225
226#endif // OPENTITAN_DT_FLASH_CTRL_H_