dt_flash_ctrl.h

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// Copyright lowRISC contributors (OpenTitan project).
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Device table API auto-generated by `dtgen`
 
#ifndef OPENTITAN_DT_FLASH_CTRL_H_
#define OPENTITAN_DT_FLASH_CTRL_H_
 
#ifdef __cplusplus
extern "C" {
#endif  // __cplusplus
 
/**
 * @file
 * @brief Device Tables (DT) for IP flash_ctrl and top englishbreakfast.
 *
 * This file contains the type definitions and global functions of the flash_ctrl.
 */
 
#include "hw/top/dt/dt_api.h"
#include <stdint.h>
 
 
 
/**
 * List of instances.
 */
typedef enum dt_flash_ctrl {
  kDtFlashCtrl = 0, /**< flash_ctrl */
  kDtFlashCtrlFirst = 0, /**< \internal First instance */
  kDtFlashCtrlCount = 1, /**< \internal Number of instances */
} dt_flash_ctrl_t;
 
/**
 * List of register blocks.
 *
 * Register blocks are guaranteed to start at 0 and to be consecutively numbered.
 */
typedef enum dt_flash_ctrl_reg_block {
  kDtFlashCtrlRegBlockCore = 0, /**<  */
  kDtFlashCtrlRegBlockPrim = 1, /**<  */
  kDtFlashCtrlRegBlockCount = 2, /**< \internal Number of register blocks */
} dt_flash_ctrl_reg_block_t;
 
/** Primary register block (associated with the "primary" set of registers that control the IP). */
static const dt_flash_ctrl_reg_block_t kDtFlashCtrlRegBlockPrimary = kDtFlashCtrlRegBlockCore;
 
/**
 * List of memories.
 *
 * Memories are guaranteed to start at 0 and to be consecutively numbered.
 */
typedef enum dt_flash_ctrl_memory {
  kDtFlashCtrlMemoryMem = 0, /**<  */
  kDtFlashCtrlMemoryCount = 1, /**< \internal Number of memories */
} dt_flash_ctrl_memory_t;
 
/**
 * List of IRQs.
 *
 * IRQs are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_flash_ctrl_irq {
  kDtFlashCtrlIrqProgEmpty = 0, /**< Program FIFO empty */
  kDtFlashCtrlIrqProgLvl = 1, /**< Program FIFO drained to level */
  kDtFlashCtrlIrqRdFull = 2, /**< Read FIFO full */
  kDtFlashCtrlIrqRdLvl = 3, /**< Read FIFO filled to level */
  kDtFlashCtrlIrqOpDone = 4, /**< Operation complete */
  kDtFlashCtrlIrqCorrErr = 5, /**< Correctable error encountered */
  kDtFlashCtrlIrqCount = 6, /**< \internal Number of IRQs */
} dt_flash_ctrl_irq_t;
 
/**
 * List of clock ports.
 *
 * Clock ports are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_flash_ctrl_clock {
  kDtFlashCtrlClockClk = 0, /**< Clock port clk_i */
  kDtFlashCtrlClockOtp = 1, /**< Clock port clk_otp_i */
  kDtFlashCtrlClockCount = 2, /**< \internal Number of clock ports */
} dt_flash_ctrl_clock_t;
 
/**
 * List of reset ports.
 *
 * Reset ports are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_flash_ctrl_reset {
  kDtFlashCtrlResetRst = 0, /**< Reset port rst_ni */
  kDtFlashCtrlResetOtp = 1, /**< Reset port rst_otp_ni */
  kDtFlashCtrlResetCount = 2, /**< \internal Number of reset ports */
} dt_flash_ctrl_reset_t;
 
/**
 * List of peripheral I/O.
 *
 * Peripheral I/O are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_flash_ctrl_periph_io {
  kDtFlashCtrlPeriphIoTck = 0, /**<  */
  kDtFlashCtrlPeriphIoTms = 1, /**<  */
  kDtFlashCtrlPeriphIoTdi = 2, /**<  */
  kDtFlashCtrlPeriphIoTdo = 3, /**<  */
  kDtFlashCtrlPeriphIoCount = 4, /**< \internal Number of peripheral I/O */
} dt_flash_ctrl_periph_io_t;
 
/**
 * List of supported hardware features.
 */
#define OPENTITAN_FLASH_CTRL_HAS_ESCALATION 1
#define OPENTITAN_FLASH_CTRL_HAS_FETCH_CODE 1
#define OPENTITAN_FLASH_CTRL_HAS_INFO_CREATOR_PARTITION 1
#define OPENTITAN_FLASH_CTRL_HAS_INFO_ISOLATED_PARTITION 1
#define OPENTITAN_FLASH_CTRL_HAS_INFO_OWNER_PARTITION 1
#define OPENTITAN_FLASH_CTRL_HAS_INIT_ROOT_SEEDS 1
#define OPENTITAN_FLASH_CTRL_HAS_INIT_SCRAMBLING_KEYS 1
#define OPENTITAN_FLASH_CTRL_HAS_MEM_PROTECTION 1
#define OPENTITAN_FLASH_CTRL_HAS_OP_HOST_READ 1
#define OPENTITAN_FLASH_CTRL_HAS_OP_PROTOCOL_CTRL 1
#define OPENTITAN_FLASH_CTRL_HAS_RMA 1
 
 
 
/**
 * Get the flash_ctrl instance from an instance ID
 *
 * For example, `dt_uart_from_instance_id(kDtInstanceIdUart3) == kDtUart3`.
 *
 * @param inst_id Instance ID.
 * @return A flash_ctrl instance.
 *
 * **Note:** This function only makes sense if the instance ID has device type flash_ctrl,
 * otherwise the returned value is unspecified.
 */
dt_flash_ctrl_t dt_flash_ctrl_from_instance_id(dt_instance_id_t inst_id);
 
/**
 * Get the instance ID of an instance.
 *
 * @param dt Instance of flash_ctrl.
 * @return The instance ID of that instance.
 */
dt_instance_id_t dt_flash_ctrl_instance_id(dt_flash_ctrl_t dt);
 
/**
 * Get the register base address of an instance.
 *
 * @param dt Instance of flash_ctrl.
 * @param reg_block The register block requested.
 * @return The register base address of the requested block.
 */
uint32_t dt_flash_ctrl_reg_block(
    dt_flash_ctrl_t dt,
    dt_flash_ctrl_reg_block_t reg_block);
 
/**
 * Get the primary register base address of an instance.
 *
 * This is just a convenience function, equivalent to
 * `dt_flash_ctrl_reg_block(dt, kDtFlashCtrlRegBlockCore)`
 *
 * @param dt Instance of flash_ctrl.
 * @return The register base address of the primary register block.
 */
static inline uint32_t dt_flash_ctrl_primary_reg_block(
    dt_flash_ctrl_t dt) {
  return dt_flash_ctrl_reg_block(dt, kDtFlashCtrlRegBlockCore);
}
 
/**
 * Get the base address of a memory.
 *
 * @param dt Instance of flash_ctrl.
 * @param mem The memory requested.
 * @return The base address of the requested memory.
 */
uint32_t dt_flash_ctrl_memory_base(
    dt_flash_ctrl_t dt,
    dt_flash_ctrl_memory_t mem);
 
/**
 * Get the size of a memory.
 *
 * @param dt Instance of flash_ctrl.
 * @param mem The memory requested.
 * @return The size of the requested memory.
 */
uint32_t dt_flash_ctrl_memory_size(
    dt_flash_ctrl_t dt,
    dt_flash_ctrl_memory_t mem);
 
/**
 * Get the PLIC ID of a flash_ctrl IRQ for a given instance.
 *
 * If the instance is not connected to the PLIC, this function
 * will return `kDtPlicIrqIdNone`.
 *
 * @param dt Instance of flash_ctrl.
 * @param irq A flash_ctrl IRQ.
 * @return The PLIC ID of the IRQ of this instance.
 */
dt_plic_irq_id_t dt_flash_ctrl_irq_to_plic_id(
    dt_flash_ctrl_t dt,
    dt_flash_ctrl_irq_t irq);
 
/**
 * Convert a global IRQ ID to a local flash_ctrl IRQ type.
 *
 * @param dt Instance of flash_ctrl.
 * @param irq A PLIC ID that belongs to this instance.
 * @return The flash_ctrl IRQ, or `kDtFlashCtrlIrqCount`.
 *
 * **Note:** This function assumes that the PLIC ID belongs to the instance
 * of flash_ctrl passed in parameter. In other words, it must be the case that
 * `dt_flash_ctrl_instance_id(dt) == dt_plic_id_to_instance_id(irq)`. Otherwise, this function
 * will return `kDtFlashCtrlIrqCount`.
 */
dt_flash_ctrl_irq_t dt_flash_ctrl_irq_from_plic_id(
    dt_flash_ctrl_t dt,
    dt_plic_irq_id_t irq);
 
 
 
/**
 * Get the peripheral I/O description of an instance.
 *
 * @param dt Instance of flash_ctrl.
 * @param sig Requested peripheral I/O.
 * @return Description of the requested peripheral I/O for this instance.
 */
dt_periph_io_t dt_flash_ctrl_periph_io(
    dt_flash_ctrl_t dt,
    dt_flash_ctrl_periph_io_t sig);
 
/**
 * Get the clock signal connected to a clock port of an instance.
 *
 * @param dt Instance of flash_ctrl.
 * @param clk Clock port.
 * @return Clock signal.
 */
dt_clock_t dt_flash_ctrl_clock(
    dt_flash_ctrl_t dt,
    dt_flash_ctrl_clock_t clk);
 
/**
 * Get the reset signal connected to a reset port of an instance.
 *
 * @param dt Instance of flash_ctrl.
 * @param rst Reset port.
 * @return Reset signal.
 */
dt_reset_t dt_flash_ctrl_reset(
    dt_flash_ctrl_t dt,
    dt_flash_ctrl_reset_t rst);
 
 
 
#ifdef __cplusplus
}  // extern "C"
#endif  // __cplusplus
 
#endif  // OPENTITAN_DT_FLASH_CTRL_H_