Software APIs
dt_clkmgr.h
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Device table API auto-generated by `dtgen`
6
7#ifndef OPENTITAN_DT_CLKMGR_H_
8#define OPENTITAN_DT_CLKMGR_H_
9
10#ifdef __cplusplus
11extern "C" {
12#endif // __cplusplus
13
14/**
15 * @file
16 * @brief Device Tables (DT) for IP clkmgr and top englishbreakfast.
17 *
18 * This file contains the type definitions and global functions of the clkmgr.
19 */
20
21#include "dt_api.h"
22#include <stdint.h>
23
24
26
27
28/**
29 * List of instances.
30 */
31typedef enum dt_clkmgr {
32 kDtClkmgrAon = 0, /**< clkmgr_aon */
33 kDtClkmgrFirst = 0, /**< \internal First instance */
34 kDtClkmgrCount = 1, /**< \internal Number of instances */
36
37/**
38 * List of register blocks.
39 *
40 * Register blocks are guaranteed to start at 0 and to be consecutively numbered.
41 */
42typedef enum dt_clkmgr_reg_block {
43 kDtClkmgrRegBlockCore = 0, /**< */
44 kDtClkmgrRegBlockCount = 1, /**< \internal Number of register blocks */
46
47/** Primary register block (associated with the "primary" set of registers that control the IP). */
48static const dt_clkmgr_reg_block_t kDtClkmgrRegBlockPrimary = kDtClkmgrRegBlockCore;
49
50/**
51 * List of clock ports.
52 *
53 * Clock ports are guaranteed to be numbered consecutively from 0.
54 */
55typedef enum dt_clkmgr_clock {
56 kDtClkmgrClockClk = 0, /**< Clock port clk_i */
57 kDtClkmgrClockMain = 1, /**< Clock port clk_main_i */
58 kDtClkmgrClockIo = 2, /**< Clock port clk_io_i */
59 kDtClkmgrClockUsb = 3, /**< Clock port clk_usb_i */
60 kDtClkmgrClockAon = 4, /**< Clock port clk_aon_i */
61 kDtClkmgrClockCount = 5, /**< \internal Number of clock ports */
63
64/**
65 * List of reset ports.
66 *
67 * Reset ports are guaranteed to be numbered consecutively from 0.
68 */
69typedef enum dt_clkmgr_reset {
70 kDtClkmgrResetRst = 0, /**< Reset port rst_ni */
71 kDtClkmgrResetRoot = 1, /**< Reset port rst_root_ni */
72 kDtClkmgrResetMain = 2, /**< Reset port rst_main_ni */
73 kDtClkmgrResetIo = 3, /**< Reset port rst_io_ni */
74 kDtClkmgrResetUsb = 4, /**< Reset port rst_usb_ni */
75 kDtClkmgrResetAon = 5, /**< Reset port rst_aon_ni */
76 kDtClkmgrResetIoDiv2 = 6, /**< Reset port rst_io_div2_ni */
77 kDtClkmgrResetIoDiv4 = 7, /**< Reset port rst_io_div4_ni */
78 kDtClkmgrResetRootMain = 8, /**< Reset port rst_root_main_ni */
79 kDtClkmgrResetRootIo = 9, /**< Reset port rst_root_io_ni */
80 kDtClkmgrResetRootIoDiv2 = 10, /**< Reset port rst_root_io_div2_ni */
81 kDtClkmgrResetRootIoDiv4 = 11, /**< Reset port rst_root_io_div4_ni */
82 kDtClkmgrResetRootUsb = 12, /**< Reset port rst_root_usb_ni */
83 kDtClkmgrResetCount = 13, /**< \internal Number of reset ports */
85
86/**
87 * List of supported hardware features.
88 */
89#define OPENTITAN_CLKMGR_HAS_ENABLE_IO_DIV4 1
90#define OPENTITAN_CLKMGR_HAS_ENABLE_IO_DIV2 1
91#define OPENTITAN_CLKMGR_HAS_ENABLE_IO 1
92#define OPENTITAN_CLKMGR_HAS_ENABLE_USB 1
93#define OPENTITAN_CLKMGR_HAS_HINT_AES 1
94#define OPENTITAN_CLKMGR_HAS_MEAS_CTRL_REGWEN 1
95#define OPENTITAN_CLKMGR_HAS_MEAS_CTRL_IO 1
96#define OPENTITAN_CLKMGR_HAS_MEAS_CTRL_IO_DIV4 1
97#define OPENTITAN_CLKMGR_HAS_MEAS_CTRL_MAIN 1
98#define OPENTITAN_CLKMGR_HAS_MEAS_CTRL_USB 1
99#define OPENTITAN_CLKMGR_HAS_MEAS_CTRL_RECOV_ERR 1
100#define OPENTITAN_CLKMGR_HAS_LC_EXTCLK_SPEED 1
101#define OPENTITAN_CLKMGR_HAS_SW_EXTCLK_REGWEN 1
102#define OPENTITAN_CLKMGR_HAS_SW_EXTCLK_HIGH_SPEED 1
103#define OPENTITAN_CLKMGR_HAS_SW_EXTCLK_LOW_SPEED 1
104#define OPENTITAN_CLKMGR_HAS_JITTER_REGWEN 1
105#define OPENTITAN_CLKMGR_HAS_JITTER_ENABLE 1
106#define OPENTITAN_CLKMGR_HAS_ALERT_HANDLER_CLOCK_STATUS 1
107
108
109
110/**
111 * Get the clkmgr instance from an instance ID
112 *
113 * For example, `dt_uart_from_instance_id(kDtInstanceIdUart3) == kDtUart3`.
114 *
115 * @param inst_id Instance ID.
116 * @return A clkmgr instance.
117 *
118 * **Note:** This function only makes sense if the instance ID has device type clkmgr,
119 * otherwise the returned value is unspecified.
120 */
122
123/**
124 * Get the instance ID of an instance.
125 *
126 * @param dt Instance of clkmgr.
127 * @return The instance ID of that instance.
128 */
130
131/**
132 * Get the register base address of an instance.
133 *
134 * @param dt Instance of clkmgr.
135 * @param reg_block The register block requested.
136 * @return The register base address of the requested block.
137 */
138uint32_t dt_clkmgr_reg_block(
139 dt_clkmgr_t dt,
140 dt_clkmgr_reg_block_t reg_block);
141
142/**
143 * Get the primary register base address of an instance.
144 *
145 * This is just a convenience function, equivalent to
146 * `dt_clkmgr_reg_block(dt, kDtClkmgrRegBlockCore)`
147 *
148 * @param dt Instance of clkmgr.
149 * @return The register base address of the primary register block.
150 */
151static inline uint32_t dt_clkmgr_primary_reg_block(
152 dt_clkmgr_t dt) {
153 return dt_clkmgr_reg_block(dt, kDtClkmgrRegBlockCore);
154}
155
156
157
158
159/**
160 * Get the clock signal connected to a clock port of an instance.
161 *
162 * @param dt Instance of clkmgr.
163 * @param clk Clock port.
164 * @return Clock signal.
165 */
167 dt_clkmgr_t dt,
169
170/**
171 * Get the reset signal connected to a reset port of an instance.
172 *
173 * @param dt Instance of clkmgr.
174 * @param rst Reset port.
175 * @return Reset signal.
176 */
178 dt_clkmgr_t dt,
180
181
182
183/**
184 * Get the number of software gateable clocks.
185 *
186 * @param dt Instance of clkmgr.
187 * @return Number of gateable clocks.
188 */
190
191/**
192 * Get the instance ID of a gateable clock.
193 *
194 * The clocks are ordered as they appear in the registers.
195 *
196 * @param dt Instance of clkmgr.
197 * @param idx Index of the gateable clock, between 0 and `dt_clkmgr_sw_clock_count(dt)-1`.
198 * @return Instance ID of the device whose clock is gateable.
199 */
201
202/**
203 * Get the number of software hintable clocks.
204 *
205 * @param dt Instance of clkmgr.
206 * @return Number of hintable clocks.
207 */
209
210/**
211 * Get the instance ID of a hintable clock.
212 *
213 * The clocks sources are ordered as they appear in the registers.
214 *
215 * @param dt Instance of clkmgr.
216 * @param idx Index of the hintable clock, between 0 and `dt_clkmgr_hint_clock_count(dt)-1`.
217 * @return Instance ID of the device whose clock is hintable.
218 */
220
221/**
222 * Description of a measurable clock.
223 *
224 */
225typedef struct dt_clkmgr_measurable_clk {
226 dt_clock_t clock; /**< Clock */
227 uint32_t meas_ctrl_en_off; /**< MEAS_CTRL_EN register offset */
228 bitfield_field32_t meas_ctrl_en_en_field; /**< MEAS_CTRL_EN_EN bitfield */
229 uint32_t meas_ctrl_shadowed_off; /**< CTRL_SHADOWED register offset */
230 bitfield_field32_t meas_ctrl_shadowed_lo_field; /**< CTRL_SHADOWED_LO bitfield */
231 bitfield_field32_t meas_ctrl_shadowed_hi_field; /**< CTRL_SHADOWED_HI bitfield */
233
234
235/**
236 * Get the number of measurable clocks.
237 *
238 * @param dt Instance of clkmgr.
239 * @return Number of measurable clocks.
240 */
242
243/**
244 * Get the description of a measurable clock.
245 *
246 * @param dt Instance of clkmgr.
247 * @param idx Index of the measurable clock, between 0 and
248 * `dt_clkmgr_measurable_clock_count(dt)-1`.
249 * @return Description of the measurable clock.
250 */
252
253
254
255#ifdef __cplusplus
256} // extern "C"
257#endif // __cplusplus
258
259#endif // OPENTITAN_DT_CLKMGR_H_