Software APIs
dt_clkmgr.h
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Device table API auto-generated by `dtgen`
6
7#ifndef OPENTITAN_DT_CLKMGR_H_
8#define OPENTITAN_DT_CLKMGR_H_
9
10/**
11 * @file
12 * @brief Device Tables (DT) for IP clkmgr and top englishbreakfast.
13 *
14 * This file contains the type definitions and global functions of the clkmgr.
15 */
16
17#include "dt_api.h"
18#include <stdint.h>
19
20
22
23
24/**
25 * List of instances.
26 */
27typedef enum dt_clkmgr {
28 kDtClkmgrAon = 0, /**< clkmgr_aon */
29 kDtClkmgrFirst = 0, /**< \internal First instance */
30 kDtClkmgrCount = 1, /**< \internal Number of instances */
32
33/**
34 * List of register blocks.
35 *
36 * Register blocks are guaranteed to start at 0 and to be consecutively numbered.
37 */
38typedef enum dt_clkmgr_reg_block {
39 kDtClkmgrRegBlockCore = 0, /**< */
40 kDtClkmgrRegBlockCount = 1, /**< \internal Number of register blocks */
42
43/** Primary register block (associated with the "primary" set of registers that control the IP). */
44static const dt_clkmgr_reg_block_t kDtClkmgrRegBlockPrimary = kDtClkmgrRegBlockCore;
45
46/**
47 * List of clock ports.
48 *
49 * Clock ports are guaranteed to be numbered consecutively from 0.
50 */
51typedef enum dt_clkmgr_clock {
52 kDtClkmgrClockClk = 0, /**< Clock port clk_i */
53 kDtClkmgrClockMain = 1, /**< Clock port clk_main_i */
54 kDtClkmgrClockIo = 2, /**< Clock port clk_io_i */
55 kDtClkmgrClockUsb = 3, /**< Clock port clk_usb_i */
56 kDtClkmgrClockAon = 4, /**< Clock port clk_aon_i */
57 kDtClkmgrClockCount = 5, /**< \internal Number of clock ports */
59
60/**
61 * List of reset ports.
62 *
63 * Reset ports are guaranteed to be numbered consecutively from 0.
64 */
65typedef enum dt_clkmgr_reset {
66 kDtClkmgrResetRst = 0, /**< Reset port rst_ni */
67 kDtClkmgrResetRoot = 1, /**< Reset port rst_root_ni */
68 kDtClkmgrResetMain = 2, /**< Reset port rst_main_ni */
69 kDtClkmgrResetIo = 3, /**< Reset port rst_io_ni */
70 kDtClkmgrResetUsb = 4, /**< Reset port rst_usb_ni */
71 kDtClkmgrResetAon = 5, /**< Reset port rst_aon_ni */
72 kDtClkmgrResetIoDiv2 = 6, /**< Reset port rst_io_div2_ni */
73 kDtClkmgrResetIoDiv4 = 7, /**< Reset port rst_io_div4_ni */
74 kDtClkmgrResetRootMain = 8, /**< Reset port rst_root_main_ni */
75 kDtClkmgrResetRootIo = 9, /**< Reset port rst_root_io_ni */
76 kDtClkmgrResetRootIoDiv2 = 10, /**< Reset port rst_root_io_div2_ni */
77 kDtClkmgrResetRootIoDiv4 = 11, /**< Reset port rst_root_io_div4_ni */
78 kDtClkmgrResetRootUsb = 12, /**< Reset port rst_root_usb_ni */
79 kDtClkmgrResetCount = 13, /**< \internal Number of reset ports */
81
82/**
83 * List of supported hardware features.
84 */
85#define OPENTITAN_CLKMGR_HAS_ENABLE_IO_DIV4 1
86#define OPENTITAN_CLKMGR_HAS_ENABLE_IO_DIV2 1
87#define OPENTITAN_CLKMGR_HAS_ENABLE_IO 1
88#define OPENTITAN_CLKMGR_HAS_ENABLE_USB 1
89#define OPENTITAN_CLKMGR_HAS_HINT_AES 1
90#define OPENTITAN_CLKMGR_HAS_MEAS_CTRL_REGWEN 1
91#define OPENTITAN_CLKMGR_HAS_MEAS_CTRL_IO 1
92#define OPENTITAN_CLKMGR_HAS_MEAS_CTRL_IO_DIV4 1
93#define OPENTITAN_CLKMGR_HAS_MEAS_CTRL_MAIN 1
94#define OPENTITAN_CLKMGR_HAS_MEAS_CTRL_USB 1
95#define OPENTITAN_CLKMGR_HAS_MEAS_CTRL_RECOV_ERR 1
96#define OPENTITAN_CLKMGR_HAS_LC_EXTCLK_SPEED 1
97#define OPENTITAN_CLKMGR_HAS_SW_EXTCLK_REGWEN 1
98#define OPENTITAN_CLKMGR_HAS_SW_EXTCLK_HIGH_SPEED 1
99#define OPENTITAN_CLKMGR_HAS_SW_EXTCLK_LOW_SPEED 1
100#define OPENTITAN_CLKMGR_HAS_JITTER_REGWEN 1
101#define OPENTITAN_CLKMGR_HAS_JITTER_ENABLE 1
102#define OPENTITAN_CLKMGR_HAS_ALERT_HANDLER_CLOCK_STATUS 1
103
104
105
106/**
107 * Get the clkmgr instance from an instance ID
108 *
109 * For example, `dt_uart_from_instance_id(kDtInstanceIdUart3) == kDtUart3`.
110 *
111 * @param inst_id Instance ID.
112 * @return A clkmgr instance.
113 *
114 * **Note:** This function only makes sense if the instance ID has device type clkmgr,
115 * otherwise the returned value is unspecified.
116 */
118
119/**
120 * Get the instance ID of an instance.
121 *
122 * @param dt Instance of clkmgr.
123 * @return The instance ID of that instance.
124 */
126
127/**
128 * Get the register base address of an instance.
129 *
130 * @param dt Instance of clkmgr.
131 * @param reg_block The register block requested.
132 * @return The register base address of the requested block.
133 */
134uint32_t dt_clkmgr_reg_block(
135 dt_clkmgr_t dt,
136 dt_clkmgr_reg_block_t reg_block);
137
138/**
139 * Get the primary register base address of an instance.
140 *
141 * This is just a convenience function, equivalent to
142 * `dt_clkmgr_reg_block(dt, kDtClkmgrRegBlockCore)`
143 *
144 * @param dt Instance of clkmgr.
145 * @return The register base address of the primary register block.
146 */
147static inline uint32_t dt_clkmgr_primary_reg_block(
148 dt_clkmgr_t dt) {
149 return dt_clkmgr_reg_block(dt, kDtClkmgrRegBlockCore);
150}
151
152
153
154
155/**
156 * Get the clock signal connected to a clock port of an instance.
157 *
158 * @param dt Instance of clkmgr.
159 * @param clk Clock port.
160 * @return Clock signal.
161 */
163 dt_clkmgr_t dt,
165
166/**
167 * Get the reset signal connected to a reset port of an instance.
168 *
169 * @param dt Instance of clkmgr.
170 * @param rst Reset port.
171 * @return Reset signal.
172 */
174 dt_clkmgr_t dt,
176
177
178
179/**
180 * Get the number of software gateable clocks.
181 *
182 * @param dt Instance of clkmgr.
183 * @return Number of gateable clocks.
184 */
186
187/**
188 * Get the instance ID of a gateable clock.
189 *
190 * The clocks are ordered as they appear in the registers.
191 *
192 * @param dt Instance of clkmgr.
193 * @param idx Index of the gateable clock, between 0 and `dt_clkmgr_sw_clock_count(dt)-1`.
194 * @return Instance ID of the device whose clock is gateable.
195 */
197
198/**
199 * Get the number of software hintable clocks.
200 *
201 * @param dt Instance of clkmgr.
202 * @return Number of hintable clocks.
203 */
205
206/**
207 * Get the instance ID of a hintable clock.
208 *
209 * The clocks sources are ordered as they appear in the registers.
210 *
211 * @param dt Instance of clkmgr.
212 * @param idx Index of the hintable clock, between 0 and `dt_clkmgr_hint_clock_count(dt)-1`.
213 * @return Instance ID of the device whose clock is hintable.
214 */
216
217/**
218 * Description of a measurable clock.
219 *
220 */
221typedef struct dt_clkmgr_measurable_clk {
222 dt_clock_t clock; /**< Clock */
223 uint32_t meas_ctrl_en_off; /**< MEAS_CTRL_EN register offset */
224 bitfield_field32_t meas_ctrl_en_en_field; /**< MEAS_CTRL_EN_EN bitfield */
225 uint32_t meas_ctrl_shadowed_off; /**< CTRL_SHADOWED register offset */
226 bitfield_field32_t meas_ctrl_shadowed_lo_field; /**< CTRL_SHADOWED_LO bitfield */
227 bitfield_field32_t meas_ctrl_shadowed_hi_field; /**< CTRL_SHADOWED_HI bitfield */
229
230
231/**
232 * Get the number of measurable clocks.
233 *
234 * @param dt Instance of clkmgr.
235 * @return Number of measurable clocks.
236 */
238
239/**
240 * Get the description of a measurable clock.
241 *
242 * @param dt Instance of clkmgr.
243 * @param idx Index of the measurable clock, between 0 and
244 * `dt_clkmgr_measurable_clock_count(dt)-1`.
245 * @return Description of the measurable clock.
246 */
248
249
250
251#endif // OPENTITAN_DT_CLKMGR_H_