Software APIs
dt_clkmgr.h
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// Copyright lowRISC contributors (OpenTitan project).
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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//
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// Device table API auto-generated by `dtgen`
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#ifndef OPENTITAN_DT_CLKMGR_H_
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#define OPENTITAN_DT_CLKMGR_H_
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#ifdef __cplusplus
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extern
"C"
{
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#endif
// __cplusplus
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/**
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* @file
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* @brief Device Tables (DT) for IP clkmgr and top englishbreakfast.
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*
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* This file contains the type definitions and global functions of the clkmgr.
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*/
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#include "
dt_api.h
"
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#include <stdint.h>
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#include "
sw/device/lib/base/bitfield.h
"
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/**
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* List of instances.
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*/
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typedef
enum
dt_clkmgr
{
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kDtClkmgrAon
= 0,
/**< clkmgr_aon */
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kDtClkmgrFirst = 0,
/**< \internal First instance */
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kDtClkmgrCount = 1,
/**< \internal Number of instances */
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}
dt_clkmgr_t
;
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/**
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* List of register blocks.
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*
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* Register blocks are guaranteed to start at 0 and to be consecutively numbered.
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*/
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typedef
enum
dt_clkmgr_reg_block
{
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kDtClkmgrRegBlockCore = 0,
/**< */
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kDtClkmgrRegBlockCount = 1,
/**< \internal Number of register blocks */
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}
dt_clkmgr_reg_block_t
;
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/** Primary register block (associated with the "primary" set of registers that control the IP). */
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static
const
dt_clkmgr_reg_block_t
kDtClkmgrRegBlockPrimary = kDtClkmgrRegBlockCore;
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/**
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* List of clock ports.
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*
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* Clock ports are guaranteed to be numbered consecutively from 0.
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*/
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typedef
enum
dt_clkmgr_clock
{
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kDtClkmgrClockClk
= 0,
/**< Clock port clk_i */
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kDtClkmgrClockMain
= 1,
/**< Clock port clk_main_i */
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kDtClkmgrClockIo
= 2,
/**< Clock port clk_io_i */
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kDtClkmgrClockUsb
= 3,
/**< Clock port clk_usb_i */
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kDtClkmgrClockAon
= 4,
/**< Clock port clk_aon_i */
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kDtClkmgrClockCount = 5,
/**< \internal Number of clock ports */
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}
dt_clkmgr_clock_t
;
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/**
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* List of reset ports.
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*
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* Reset ports are guaranteed to be numbered consecutively from 0.
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*/
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typedef
enum
dt_clkmgr_reset
{
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kDtClkmgrResetRst
= 0,
/**< Reset port rst_ni */
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kDtClkmgrResetRoot
= 1,
/**< Reset port rst_root_ni */
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kDtClkmgrResetMain
= 2,
/**< Reset port rst_main_ni */
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kDtClkmgrResetIo
= 3,
/**< Reset port rst_io_ni */
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kDtClkmgrResetUsb
= 4,
/**< Reset port rst_usb_ni */
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kDtClkmgrResetAon
= 5,
/**< Reset port rst_aon_ni */
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kDtClkmgrResetIoDiv2
= 6,
/**< Reset port rst_io_div2_ni */
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kDtClkmgrResetIoDiv4
= 7,
/**< Reset port rst_io_div4_ni */
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kDtClkmgrResetRootMain
= 8,
/**< Reset port rst_root_main_ni */
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kDtClkmgrResetRootIo
= 9,
/**< Reset port rst_root_io_ni */
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kDtClkmgrResetRootIoDiv2
= 10,
/**< Reset port rst_root_io_div2_ni */
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kDtClkmgrResetRootIoDiv4
= 11,
/**< Reset port rst_root_io_div4_ni */
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kDtClkmgrResetRootUsb
= 12,
/**< Reset port rst_root_usb_ni */
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kDtClkmgrResetCount = 13,
/**< \internal Number of reset ports */
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}
dt_clkmgr_reset_t
;
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/**
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* List of supported hardware features.
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*/
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#define OPENTITAN_CLKMGR_HAS_ENABLE_IO_DIV4 1
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#define OPENTITAN_CLKMGR_HAS_ENABLE_IO_DIV2 1
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#define OPENTITAN_CLKMGR_HAS_ENABLE_IO 1
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#define OPENTITAN_CLKMGR_HAS_ENABLE_USB 1
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#define OPENTITAN_CLKMGR_HAS_HINT_AES 1
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#define OPENTITAN_CLKMGR_HAS_MEAS_CTRL_REGWEN 1
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#define OPENTITAN_CLKMGR_HAS_MEAS_CTRL_IO 1
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#define OPENTITAN_CLKMGR_HAS_MEAS_CTRL_IO_DIV4 1
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#define OPENTITAN_CLKMGR_HAS_MEAS_CTRL_MAIN 1
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#define OPENTITAN_CLKMGR_HAS_MEAS_CTRL_USB 1
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#define OPENTITAN_CLKMGR_HAS_MEAS_CTRL_RECOV_ERR 1
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#define OPENTITAN_CLKMGR_HAS_LC_EXTCLK_SPEED 1
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#define OPENTITAN_CLKMGR_HAS_SW_EXTCLK_REGWEN 1
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#define OPENTITAN_CLKMGR_HAS_SW_EXTCLK_HIGH_SPEED 1
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#define OPENTITAN_CLKMGR_HAS_SW_EXTCLK_LOW_SPEED 1
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#define OPENTITAN_CLKMGR_HAS_JITTER_REGWEN 1
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#define OPENTITAN_CLKMGR_HAS_JITTER_ENABLE 1
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#define OPENTITAN_CLKMGR_HAS_ALERT_HANDLER_CLOCK_STATUS 1
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/**
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* Get the clkmgr instance from an instance ID
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*
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* For example, `dt_uart_from_instance_id(kDtInstanceIdUart3) == kDtUart3`.
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*
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* @param inst_id Instance ID.
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* @return A clkmgr instance.
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*
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* **Note:** This function only makes sense if the instance ID has device type clkmgr,
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* otherwise the returned value is unspecified.
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*/
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dt_clkmgr_t
dt_clkmgr_from_instance_id
(
dt_instance_id_t
inst_id);
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/**
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* Get the instance ID of an instance.
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*
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* @param dt Instance of clkmgr.
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* @return The instance ID of that instance.
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*/
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dt_instance_id_t
dt_clkmgr_instance_id
(
dt_clkmgr_t
dt);
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/**
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* Get the register base address of an instance.
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*
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* @param dt Instance of clkmgr.
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* @param reg_block The register block requested.
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* @return The register base address of the requested block.
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*/
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uint32_t
dt_clkmgr_reg_block
(
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dt_clkmgr_t
dt,
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dt_clkmgr_reg_block_t
reg_block);
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/**
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* Get the primary register base address of an instance.
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*
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* This is just a convenience function, equivalent to
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* `dt_clkmgr_reg_block(dt, kDtClkmgrRegBlockCore)`
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*
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* @param dt Instance of clkmgr.
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* @return The register base address of the primary register block.
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*/
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static
inline
uint32_t dt_clkmgr_primary_reg_block(
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dt_clkmgr_t
dt) {
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return
dt_clkmgr_reg_block
(dt, kDtClkmgrRegBlockCore);
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}
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/**
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* Get the clock signal connected to a clock port of an instance.
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*
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* @param dt Instance of clkmgr.
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* @param clk Clock port.
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* @return Clock signal.
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*/
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dt_clock_t
dt_clkmgr_clock
(
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dt_clkmgr_t
dt,
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dt_clkmgr_clock_t
clk);
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/**
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* Get the reset signal connected to a reset port of an instance.
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*
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* @param dt Instance of clkmgr.
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* @param rst Reset port.
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* @return Reset signal.
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*/
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dt_reset_t
dt_clkmgr_reset
(
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dt_clkmgr_t
dt,
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dt_clkmgr_reset_t
rst);
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/**
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* Get the number of software gateable clocks.
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*
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* @param dt Instance of clkmgr.
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* @return Number of gateable clocks.
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*/
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size_t
dt_clkmgr_gateable_clock_count
(
dt_clkmgr_t
dt);
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/**
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* Get the instance ID of a gateable clock.
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*
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* The clocks are ordered as they appear in the registers.
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*
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* @param dt Instance of clkmgr.
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* @param idx Index of the gateable clock, between 0 and `dt_clkmgr_sw_clock_count(dt)-1`.
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* @return Instance ID of the device whose clock is gateable.
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*/
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dt_instance_id_t
dt_clkmgr_gateable_clock
(
dt_clkmgr_t
dt,
size_t
idx);
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/**
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* Get the number of software hintable clocks.
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*
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* @param dt Instance of clkmgr.
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* @return Number of hintable clocks.
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*/
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size_t
dt_clkmgr_hintable_clock_count
(
dt_clkmgr_t
dt);
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/**
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* Get the instance ID of a hintable clock.
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*
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* The clocks sources are ordered as they appear in the registers.
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*
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* @param dt Instance of clkmgr.
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* @param idx Index of the hintable clock, between 0 and `dt_clkmgr_hint_clock_count(dt)-1`.
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* @return Instance ID of the device whose clock is hintable.
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*/
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dt_instance_id_t
dt_clkmgr_hintable_clock
(
dt_clkmgr_t
dt,
size_t
idx);
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/**
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* Description of a measurable clock.
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*
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*/
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typedef
struct
dt_clkmgr_measurable_clk
{
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dt_clock_t
clock
;
/**< Clock */
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uint32_t
meas_ctrl_en_off
;
/**< MEAS_CTRL_EN register offset */
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bitfield_field32_t
meas_ctrl_en_en_field
;
/**< MEAS_CTRL_EN_EN bitfield */
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uint32_t
meas_ctrl_shadowed_off
;
/**< CTRL_SHADOWED register offset */
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bitfield_field32_t
meas_ctrl_shadowed_lo_field
;
/**< CTRL_SHADOWED_LO bitfield */
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bitfield_field32_t
meas_ctrl_shadowed_hi_field
;
/**< CTRL_SHADOWED_HI bitfield */
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}
dt_clkmgr_measurable_clk_t
;
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/**
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* Get the number of measurable clocks.
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*
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* @param dt Instance of clkmgr.
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* @return Number of measurable clocks.
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*/
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size_t
dt_clkmgr_measurable_clock_count
(
dt_clkmgr_t
dt);
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/**
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* Get the description of a measurable clock.
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*
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* @param dt Instance of clkmgr.
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* @param idx Index of the measurable clock, between 0 and
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* `dt_clkmgr_measurable_clock_count(dt)-1`.
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* @return Description of the measurable clock.
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*/
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dt_clkmgr_measurable_clk_t
dt_clkmgr_measurable_clock
(
dt_clkmgr_t
dt,
size_t
idx);
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#ifdef __cplusplus
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}
// extern "C"
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#endif
// __cplusplus
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#endif
// OPENTITAN_DT_CLKMGR_H_
(englishbreakfast)
hw
top
dt
dt_clkmgr.h
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