dt_clkmgr.c

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// Copyright lowRISC contributors (OpenTitan project).
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Device table API auto-generated by `dtgen`
 
/**
 * @file
 * @brief Device Tables (DT) for IP clkmgr and top englishbreakfast.
 */
 
#include "hw/top/dt/dt_clkmgr.h"
 
 
#include "hw/top/clkmgr_regs.h"
 
 
/**
 * Description of instances.
 */
typedef struct dt_desc_clkmgr {
  dt_instance_id_t inst_id; /**< Instance ID */
  uint32_t reg_addr[kDtClkmgrRegBlockCount]; /**< Base address of each register block */
  uint32_t mem_addr[kDtClkmgrMemoryCount]; /**< Base address of each memory */
  uint32_t mem_size[kDtClkmgrMemoryCount]; /**< Size in bytes of each memory */
  dt_clock_t clock[kDtClkmgrClockCount]; /**< Clock signal connected to each clock port */
  dt_reset_t reset[kDtClkmgrResetCount]; /**< Reset signal connected to each reset port */
  struct {
    dt_instance_id_t sw_clks[4]; /**< List of gateable clocks, in the order of the register fields */
    dt_instance_id_t hint_clks[1]; /**< List of hintable clocks, in the order of the register fields */
    dt_clkmgr_measurable_clk_t measurable_clks[4]; /**< List of measurables clocks */
  } clkmgr_ext; /**< Extension */
} dt_desc_clkmgr_t;
 
 
 
 
static const dt_desc_clkmgr_t clkmgr_desc[kDtClkmgrCount] = {
  [kDtClkmgrAon] = {
    .inst_id = kDtInstanceIdClkmgrAon,
    .reg_addr = {
      [kDtClkmgrRegBlockCore] = 0x40420000,
    },
    .mem_addr = {
    },
    .mem_size = {
    },
    .clock = {
      [kDtClkmgrClockClk] = kDtClockIoDiv4,
      [kDtClkmgrClockMain] = kDtClockMain,
      [kDtClkmgrClockIo] = kDtClockIo,
      [kDtClkmgrClockUsb] = kDtClockUsb,
      [kDtClkmgrClockAon] = kDtClockAon,
    },
    .reset = {
      [kDtClkmgrResetRst] = kDtResetPorIoDiv4,
      [kDtClkmgrResetAon] = kDtResetPorAon,
      [kDtClkmgrResetIo] = kDtResetPorIo,
      [kDtClkmgrResetIoDiv2] = kDtResetPorIoDiv2,
      [kDtClkmgrResetIoDiv4] = kDtResetPorIoDiv4,
      [kDtClkmgrResetMain] = kDtResetPor,
      [kDtClkmgrResetUsb] = kDtResetPorUsb,
      [kDtClkmgrResetRoot] = kDtResetPorIoDiv4,
      [kDtClkmgrResetRootIo] = kDtResetPorIo,
      [kDtClkmgrResetRootIoDiv2] = kDtResetPorIoDiv2,
      [kDtClkmgrResetRootIoDiv4] = kDtResetPorIoDiv4,
      [kDtClkmgrResetRootMain] = kDtResetPor,
      [kDtClkmgrResetRootUsb] = kDtResetPorUsb,
    },
    .clkmgr_ext = {
      .sw_clks = {
        [0] = kDtInstanceIdUart0,
        [1] = kDtInstanceIdSpiDevice,
        [2] = kDtInstanceIdSpiHost0,
        [3] = kDtInstanceIdUsbdev,
      },
      .hint_clks = {
        [0] = kDtInstanceIdAes,
      },
      .measurable_clks = {
        [0] = {
          .clock = kDtClockIo,
          .meas_ctrl_en_off = CLKMGR_IO_MEAS_CTRL_EN_REG_OFFSET,
          .meas_ctrl_en_en_field = CLKMGR_IO_MEAS_CTRL_EN_EN_FIELD,
          .meas_ctrl_shadowed_off = CLKMGR_IO_MEAS_CTRL_SHADOWED_REG_OFFSET,
          .meas_ctrl_shadowed_lo_field = CLKMGR_IO_MEAS_CTRL_SHADOWED_LO_FIELD,
          .meas_ctrl_shadowed_hi_field = CLKMGR_IO_MEAS_CTRL_SHADOWED_HI_FIELD,
        },
        [1] = {
          .clock = kDtClockIoDiv4,
          .meas_ctrl_en_off = CLKMGR_IO_DIV4_MEAS_CTRL_EN_REG_OFFSET,
          .meas_ctrl_en_en_field = CLKMGR_IO_DIV4_MEAS_CTRL_EN_EN_FIELD,
          .meas_ctrl_shadowed_off = CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_REG_OFFSET,
          .meas_ctrl_shadowed_lo_field = CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_LO_FIELD,
          .meas_ctrl_shadowed_hi_field = CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_HI_FIELD,
        },
        [2] = {
          .clock = kDtClockMain,
          .meas_ctrl_en_off = CLKMGR_MAIN_MEAS_CTRL_EN_REG_OFFSET,
          .meas_ctrl_en_en_field = CLKMGR_MAIN_MEAS_CTRL_EN_EN_FIELD,
          .meas_ctrl_shadowed_off = CLKMGR_MAIN_MEAS_CTRL_SHADOWED_REG_OFFSET,
          .meas_ctrl_shadowed_lo_field = CLKMGR_MAIN_MEAS_CTRL_SHADOWED_LO_FIELD,
          .meas_ctrl_shadowed_hi_field = CLKMGR_MAIN_MEAS_CTRL_SHADOWED_HI_FIELD,
        },
        [3] = {
          .clock = kDtClockUsb,
          .meas_ctrl_en_off = CLKMGR_USB_MEAS_CTRL_EN_REG_OFFSET,
          .meas_ctrl_en_en_field = CLKMGR_USB_MEAS_CTRL_EN_EN_FIELD,
          .meas_ctrl_shadowed_off = CLKMGR_USB_MEAS_CTRL_SHADOWED_REG_OFFSET,
          .meas_ctrl_shadowed_lo_field = CLKMGR_USB_MEAS_CTRL_SHADOWED_LO_FIELD,
          .meas_ctrl_shadowed_hi_field = CLKMGR_USB_MEAS_CTRL_SHADOWED_HI_FIELD,
        },
      },
    },
  },
};
 
/**
 * Return a pointer to the `dt_clkmgr_desc_t` structure of the requested
 * `dt` if it's a valid index. Otherwise, this macro will `return` (i.e. exit
 * the function) with the provided default value.
 */
#define TRY_GET_DT(dt, default)   ({     if ((dt) < (dt_clkmgr_t)0 || (dt) >= kDtClkmgrCount)       return (default);     &clkmgr_desc[dt];   })
 
dt_clkmgr_t dt_clkmgr_from_instance_id(dt_instance_id_t inst_id) {
  if (inst_id >= kDtInstanceIdClkmgrAon && inst_id <= kDtInstanceIdClkmgrAon) {
    return (dt_clkmgr_t)(inst_id - kDtInstanceIdClkmgrAon);
  }
  return (dt_clkmgr_t)0;
}
 
dt_instance_id_t dt_clkmgr_instance_id(
    dt_clkmgr_t dt) {
  return TRY_GET_DT(dt, kDtInstanceIdUnknown)->inst_id;
}
 
uint32_t dt_clkmgr_reg_block(
    dt_clkmgr_t dt,
    dt_clkmgr_reg_block_t reg_block) {
  // Return a recognizable address in case of wrong argument.
  return TRY_GET_DT(dt, 0xdeadbeef)->reg_addr[reg_block];
}
 
uint32_t dt_clkmgr_memory_base(
    dt_clkmgr_t dt,
    dt_clkmgr_memory_t mem) {
  // Return a recognizable address in case of wrong argument.
  return TRY_GET_DT(dt, 0xdeadbeef)->mem_addr[mem];
}
 
uint32_t dt_clkmgr_memory_size(
    dt_clkmgr_t dt,
    dt_clkmgr_memory_t mem)  {
  // Return an empty size in case of wrong argument.
  return TRY_GET_DT(dt, 0)->mem_size[mem];
}
 
 
 
 
dt_clock_t dt_clkmgr_clock(
    dt_clkmgr_t dt,
    dt_clkmgr_clock_t clk) {
  // Return the first clock in case of invalid argument.
  return TRY_GET_DT(dt, (dt_clock_t)0)->clock[clk];
}
 
dt_reset_t dt_clkmgr_reset(
    dt_clkmgr_t dt,
    dt_clkmgr_reset_t rst) {
  const dt_clkmgr_reset_t count = kDtClkmgrResetCount;
  if (rst >= count) {
    return kDtResetUnknown;
  }
  return TRY_GET_DT(dt, kDtResetUnknown)->reset[rst];
}
 
 
 
size_t dt_clkmgr_gateable_clock_count(dt_clkmgr_t dt) {
  return 4;
}
 
dt_instance_id_t dt_clkmgr_gateable_clock(dt_clkmgr_t dt, size_t idx) {
  return TRY_GET_DT(dt, kDtInstanceIdUnknown)->clkmgr_ext.sw_clks[idx];
}
 
size_t dt_clkmgr_hintable_clock_count(dt_clkmgr_t dt) {
  return 1;
}
 
dt_instance_id_t dt_clkmgr_hintable_clock(dt_clkmgr_t dt, size_t idx) {
  return TRY_GET_DT(dt, kDtInstanceIdUnknown)->clkmgr_ext.hint_clks[idx];
}
 
size_t dt_clkmgr_measurable_clock_count(dt_clkmgr_t dt) {
  return 4;
}
 
dt_clkmgr_measurable_clk_t dt_clkmgr_measurable_clock(dt_clkmgr_t dt, size_t idx) {
  dt_clkmgr_measurable_clk_t invalid_clk =   {
    .clock = kDtClockCount,
    .meas_ctrl_en_off = 0xdead,
    .meas_ctrl_en_en_field = ((bitfield_field32_t) { .mask = 0, .index = 0 }),
    .meas_ctrl_shadowed_off = 0xdead,
    .meas_ctrl_shadowed_lo_field = ((bitfield_field32_t) { .mask = 0, .index = 0 }),
    .meas_ctrl_shadowed_hi_field = ((bitfield_field32_t) { .mask = 0, .index = 0 }),
  };
  return TRY_GET_DT(dt, invalid_clk)->clkmgr_ext.measurable_clks[idx];
}