Software APIs
dt_clkmgr.c
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Device table API auto-generated by `dtgen`
6
7/**
8 * @file
9 * @brief Device Tables (DT) for IP clkmgr and top englishbreakfast.
10 */
11
12#include "dt/dt_clkmgr.h"
13
14
15#include "clkmgr_regs.h"
16
17
18/**
19 * Description of instances.
20 */
21typedef struct dt_desc_clkmgr {
22 dt_instance_id_t inst_id; /**< Instance ID */
23 uint32_t base_addr[kDtClkmgrRegBlockCount]; /**< Base address of each register block */
24 dt_clock_t clock[kDtClkmgrClockCount]; /**< Clock signal connected to each clock port */
25 dt_reset_t reset[kDtClkmgrResetCount]; /**< Reset signal connected to each reset port */
26 struct {
27 dt_instance_id_t sw_clks[4]; /**< List of gateable clocks, in the order of the register fields */
28 dt_instance_id_t hint_clks[1]; /**< List of hintable clocks, in the order of the register fields */
29 dt_clkmgr_measurable_clk_t measurable_clks[4]; /**< List of measurables clocks */
30 } clkmgr_ext; /**< Extension */
32
33
34
35
36static const dt_desc_clkmgr_t clkmgr_desc[kDtClkmgrCount] = {
37 [kDtClkmgrAon] = {
38 .inst_id = kDtInstanceIdClkmgrAon,
39 .base_addr = {
40 [kDtClkmgrRegBlockCore] = 0x40420000,
41 },
42 .clock = {
48 },
49 .reset = {
63 },
64 .clkmgr_ext = {
65 .sw_clks = {
70 },
71 .hint_clks = {
72 [0] = kDtInstanceIdAes,
73 },
74 .measurable_clks = {
75 [0] = {
76 .clock = kDtClockIo,
77 .meas_ctrl_en_off = CLKMGR_IO_MEAS_CTRL_EN_REG_OFFSET,
78 .meas_ctrl_en_en_field = CLKMGR_IO_MEAS_CTRL_EN_EN_FIELD,
79 .meas_ctrl_shadowed_off = CLKMGR_IO_MEAS_CTRL_SHADOWED_REG_OFFSET,
80 .meas_ctrl_shadowed_lo_field = CLKMGR_IO_MEAS_CTRL_SHADOWED_LO_FIELD,
81 .meas_ctrl_shadowed_hi_field = CLKMGR_IO_MEAS_CTRL_SHADOWED_HI_FIELD,
82 },
83 [1] = {
84 .clock = kDtClockIoDiv4,
85 .meas_ctrl_en_off = CLKMGR_IO_DIV4_MEAS_CTRL_EN_REG_OFFSET,
86 .meas_ctrl_en_en_field = CLKMGR_IO_DIV4_MEAS_CTRL_EN_EN_FIELD,
87 .meas_ctrl_shadowed_off = CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_REG_OFFSET,
88 .meas_ctrl_shadowed_lo_field = CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_LO_FIELD,
89 .meas_ctrl_shadowed_hi_field = CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_HI_FIELD,
90 },
91 [2] = {
92 .clock = kDtClockMain,
93 .meas_ctrl_en_off = CLKMGR_MAIN_MEAS_CTRL_EN_REG_OFFSET,
94 .meas_ctrl_en_en_field = CLKMGR_MAIN_MEAS_CTRL_EN_EN_FIELD,
95 .meas_ctrl_shadowed_off = CLKMGR_MAIN_MEAS_CTRL_SHADOWED_REG_OFFSET,
96 .meas_ctrl_shadowed_lo_field = CLKMGR_MAIN_MEAS_CTRL_SHADOWED_LO_FIELD,
97 .meas_ctrl_shadowed_hi_field = CLKMGR_MAIN_MEAS_CTRL_SHADOWED_HI_FIELD,
98 },
99 [3] = {
100 .clock = kDtClockUsb,
101 .meas_ctrl_en_off = CLKMGR_USB_MEAS_CTRL_EN_REG_OFFSET,
102 .meas_ctrl_en_en_field = CLKMGR_USB_MEAS_CTRL_EN_EN_FIELD,
103 .meas_ctrl_shadowed_off = CLKMGR_USB_MEAS_CTRL_SHADOWED_REG_OFFSET,
104 .meas_ctrl_shadowed_lo_field = CLKMGR_USB_MEAS_CTRL_SHADOWED_LO_FIELD,
105 .meas_ctrl_shadowed_hi_field = CLKMGR_USB_MEAS_CTRL_SHADOWED_HI_FIELD,
106 },
107 },
108 },
109 },
110};
111
112/**
113 * Return a pointer to the `dt_clkmgr_desc_t` structure of the requested
114 * `dt` if it's a valid index. Otherwise, this macro will `return` (i.e. exit
115 * the function) with the provided default value.
116 */
117#define TRY_GET_DT(dt, default) ({ if ((dt) < (dt_clkmgr_t)0 || (dt) >= kDtClkmgrCount) return (default); &clkmgr_desc[dt]; })
118
120 if (inst_id >= kDtInstanceIdClkmgrAon && inst_id <= kDtInstanceIdClkmgrAon) {
121 return (dt_clkmgr_t)(inst_id - kDtInstanceIdClkmgrAon);
122 }
123 return (dt_clkmgr_t)0;
124}
125
130
132 dt_clkmgr_t dt,
133 dt_clkmgr_reg_block_t reg_block) {
134 // Return a recognizable address in case of wrong argument.
135 return TRY_GET_DT(dt, 0xdeadbeef)->base_addr[reg_block];
136}
137
138
139
140
142 dt_clkmgr_t dt,
143 dt_clkmgr_clock_t clk) {
144 // Return the first clock in case of invalid argument.
145 return TRY_GET_DT(dt, (dt_clock_t)0)->clock[clk];
146}
147
149 dt_clkmgr_t dt,
150 dt_clkmgr_reset_t rst) {
151 const dt_clkmgr_reset_t count = kDtClkmgrResetCount;
152 if (rst >= count) {
153 return kDtResetUnknown;
154 }
155 return TRY_GET_DT(dt, kDtResetUnknown)->reset[rst];
156}
157
158
159
161 return 4;
162}
163
165 return TRY_GET_DT(dt, kDtInstanceIdUnknown)->clkmgr_ext.sw_clks[idx];
166}
167
169 return 1;
170}
171
173 return TRY_GET_DT(dt, kDtInstanceIdUnknown)->clkmgr_ext.hint_clks[idx];
174}
175
177 return 4;
178}
179
181 dt_clkmgr_measurable_clk_t invalid_clk = {
182 .clock = kDtClockCount,
183 .meas_ctrl_en_off = 0xdead,
184 .meas_ctrl_en_en_field = ((bitfield_field32_t) { .mask = 0, .index = 0 }),
185 .meas_ctrl_shadowed_off = 0xdead,
186 .meas_ctrl_shadowed_lo_field = ((bitfield_field32_t) { .mask = 0, .index = 0 }),
187 .meas_ctrl_shadowed_hi_field = ((bitfield_field32_t) { .mask = 0, .index = 0 }),
188 };
189 return TRY_GET_DT(dt, invalid_clk)->clkmgr_ext.measurable_clks[idx];
190}
191
192