Software APIs
dt_aon_timer.h
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Device table API auto-generated by `dtgen`
6
7#ifndef OPENTITAN_DT_AON_TIMER_H_
8#define OPENTITAN_DT_AON_TIMER_H_
9
10/**
11 * @file
12 * @brief Device Tables (DT) for IP aon_timer and top englishbreakfast.
13 *
14 * This file contains the type definitions and global functions of the aon_timer.
15 */
16
17#include "dt_api.h"
18#include <stdint.h>
19
20
21
22/**
23 * List of instances.
24 */
25typedef enum dt_aon_timer {
26 kDtAonTimerAon = 0, /**< aon_timer_aon */
27 kDtAonTimerFirst = 0, /**< \internal First instance */
28 kDtAonTimerCount = 1, /**< \internal Number of instances */
30
31/**
32 * List of register blocks.
33 *
34 * Register blocks are guaranteed to start at 0 and to be consecutively numbered.
35 */
37 kDtAonTimerRegBlockCore = 0, /**< */
38 kDtAonTimerRegBlockCount = 1, /**< \internal Number of register blocks */
40
41/** Primary register block (associated with the "primary" set of registers that control the IP). */
42static const dt_aon_timer_reg_block_t kDtAonTimerRegBlockPrimary = kDtAonTimerRegBlockCore;
43
44/**
45 * List of IRQs.
46 *
47 * IRQs are guaranteed to be numbered consecutively from 0.
48 */
49typedef enum dt_aon_timer_irq {
50 kDtAonTimerIrqWkupTimerExpired = 0, /**< Raised if the wakeup timer has hit the specified threshold. */
51 kDtAonTimerIrqWdogTimerBark = 1, /**< Raised if the watchdog timer has hit the bark threshold. */
52 kDtAonTimerIrqCount = 2, /**< \internal Number of IRQs */
54
55/**
56 * List of clock ports.
57 *
58 * Clock ports are guaranteed to be numbered consecutively from 0.
59 */
60typedef enum dt_aon_timer_clock {
61 kDtAonTimerClockClk = 0, /**< Clock port clk_i */
62 kDtAonTimerClockAon = 1, /**< Clock port clk_aon_i */
63 kDtAonTimerClockCount = 2, /**< \internal Number of clock ports */
65
66/**
67 * List of reset requests.
68 *
69 * Reset requests are guaranteed to be numbered consecutively from 0.
70 */
72 kDtAonTimerResetReqAonTimer = 0, /**< Watchdog reset request. */
73 kDtAonTimerResetReqCount = 1, /**< \internal Number of reset requests */
75
76/**
77 * List of reset ports.
78 *
79 * Reset ports are guaranteed to be numbered consecutively from 0.
80 */
81typedef enum dt_aon_timer_reset {
82 kDtAonTimerResetRst = 0, /**< Reset port rst_ni */
83 kDtAonTimerResetAon = 1, /**< Reset port rst_aon_ni */
84 kDtAonTimerResetCount = 2, /**< \internal Number of reset ports */
86
87/**
88 * List of wakeups.
89 *
90 * Wakeups are guaranteed to be numbered consecutively from 0.
91 */
92typedef enum dt_aon_timer_wakeup {
93 kDtAonTimerWakeupWkupReq = 0, /**< Raised if the wakeup or watchdog timer has hit the specified threshold. */
94 kDtAonTimerWakeupCount = 1, /**< \internal Number of wakeups */
96
97/**
98 * List of supported hardware features.
99 */
100#define OPENTITAN_AON_TIMER_HAS_WAKEUP_WAKEUP_CONFIG 1
101#define OPENTITAN_AON_TIMER_HAS_WAKEUP_WAKEUP_REQUEST 1
102#define OPENTITAN_AON_TIMER_HAS_WAKEUP_INTERRUPT 1
103#define OPENTITAN_AON_TIMER_HAS_WATCHDOG_BARK 1
104#define OPENTITAN_AON_TIMER_HAS_WATCHDOG_BITE 1
105#define OPENTITAN_AON_TIMER_HAS_WATCHDOG_PAUSE 1
106#define OPENTITAN_AON_TIMER_HAS_WATCHDOG_DISABLE_BY_LC_CTRL 1
107#define OPENTITAN_AON_TIMER_HAS_WATCHDOG_INTERRUPT 1
108
109
110
111/**
112 * Get the aon_timer instance from an instance ID
113 *
114 * For example, `dt_uart_from_instance_id(kDtInstanceIdUart3) == kDtUart3`.
115 *
116 * @param inst_id Instance ID.
117 * @return A aon_timer instance.
118 *
119 * **Note:** This function only makes sense if the instance ID has device type aon_timer,
120 * otherwise the returned value is unspecified.
121 */
123
124/**
125 * Get the instance ID of an instance.
126 *
127 * @param dt Instance of aon_timer.
128 * @return The instance ID of that instance.
129 */
131
132/**
133 * Get the register base address of an instance.
134 *
135 * @param dt Instance of aon_timer.
136 * @param reg_block The register block requested.
137 * @return The register base address of the requested block.
138 */
141 dt_aon_timer_reg_block_t reg_block);
142
143/**
144 * Get the primary register base address of an instance.
145 *
146 * This is just a convenience function, equivalent to
147 * `dt_aon_timer_reg_block(dt, kDtAonTimerRegBlockCore)`
148 *
149 * @param dt Instance of aon_timer.
150 * @return The register base address of the primary register block.
151 */
152static inline uint32_t dt_aon_timer_primary_reg_block(
153 dt_aon_timer_t dt) {
154 return dt_aon_timer_reg_block(dt, kDtAonTimerRegBlockCore);
155}
156
157/**
158 * Get the PLIC ID of a aon_timer IRQ for a given instance.
159 *
160 * If the instance is not connected to the PLIC, this function
161 * will return `kDtPlicIrqIdNone`.
162 *
163 * @param dt Instance of aon_timer.
164 * @param irq A aon_timer IRQ.
165 * @return The PLIC ID of the IRQ of this instance.
166 */
170
171/**
172 * Convert a global IRQ ID to a local aon_timer IRQ type.
173 *
174 * @param dt Instance of aon_timer.
175 * @param irq A PLIC ID that belongs to this instance.
176 * @return The aon_timer IRQ, or `kDtAonTimerIrqCount`.
177 *
178 * **Note:** This function assumes that the PLIC ID belongs to the instance
179 * of aon_timer passed in parameter. In other words, it must be the case that
180 * `dt_aon_timer_instance_id(dt) == dt_plic_id_to_instance_id(irq)`. Otherwise, this function
181 * will return `kDtAonTimerIrqCount`.
182 */
185 dt_plic_irq_id_t irq);
186
187
188
189
190/**
191 * Get the clock signal connected to a clock port of an instance.
192 *
193 * @param dt Instance of aon_timer.
194 * @param clk Clock port.
195 * @return Clock signal.
196 */
200
201/**
202 * Get the reset signal connected to a reset port of an instance.
203 *
204 * @param dt Instance of aon_timer.
205 * @param rst Reset port.
206 * @return Reset signal.
207 */
211
212
213
214#endif // OPENTITAN_DT_AON_TIMER_H_