Software APIs
dt_aon_timer.h
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Device table API auto-generated by `dtgen`
6
7#ifndef OPENTITAN_DT_AON_TIMER_H_
8#define OPENTITAN_DT_AON_TIMER_H_
9
10/**
11 * @file
12 * @brief Device Tables (DT) for IP aon_timer and top englishbreakfast.
13 *
14 * This file contains the type definitions and global functions of the aon_timer.
15 */
16
17#include "dt_api.h"
18#include <stdint.h>
19
20/**
21 * List of instances.
22 */
23typedef enum dt_aon_timer {
24 kDtAonTimerAon = 0, /**< aon_timer_aon */
25 kDtAonTimerFirst = 0, /**< \internal First instance */
26 kDtAonTimerCount = 1, /**< \internal Number of instances */
28
29/**
30 * List of register blocks.
31 *
32 * Register blocks are guaranteed to start at 0 and to be consecutively numbered.
33 */
35 kDtAonTimerRegBlockCore = 0, /**< */
36 kDtAonTimerRegBlockCount = 1, /**< \internal Number of register blocks */
38
39/** Primary register block (associated with the "primary" set of registers that control the IP). */
40static const dt_aon_timer_reg_block_t kDtAonTimerRegBlockPrimary = kDtAonTimerRegBlockCore;
41
42/**
43 * List of IRQs.
44 *
45 * IRQs are guaranteed to be numbered consecutively from 0.
46 */
47typedef enum dt_aon_timer_irq {
48 kDtAonTimerIrqWkupTimerExpired = 0, /**< Raised if the wakeup timer has hit the specified threshold. */
49 kDtAonTimerIrqWdogTimerBark = 1, /**< Raised if the watchdog timer has hit the bark threshold. */
50 kDtAonTimerIrqCount = 2, /**< \internal Number of IRQs */
52
53/**
54 * List of clock ports.
55 *
56 * Clock ports are guaranteed to be numbered consecutively from 0.
57 */
58typedef enum dt_aon_timer_clock {
59 kDtAonTimerClockClk = 0, /**< Clock port clk_i */
60 kDtAonTimerClockAon = 1, /**< Clock port clk_aon_i */
61 kDtAonTimerClockCount = 2, /**< \internal Number of clock ports */
63
64/**
65 * List of reset requests.
66 *
67 * Reset requests are guaranteed to be numbered consecutively from 0.
68 */
70 kDtAonTimerResetReqAonTimer = 0, /**< Watchdog reset request. */
71 kDtAonTimerResetReqCount = 1, /**< \internal Number of reset requests */
73
74/**
75 * List of reset ports.
76 *
77 * Reset ports are guaranteed to be numbered consecutively from 0.
78 */
79typedef enum dt_aon_timer_reset {
80 kDtAonTimerResetRst = 0, /**< Reset port rst_ni */
81 kDtAonTimerResetAon = 1, /**< Reset port rst_aon_ni */
82 kDtAonTimerResetCount = 2, /**< \internal Number of reset ports */
84
85/**
86 * List of wakeups.
87 *
88 * Wakeups are guaranteed to be numbered consecutively from 0.
89 */
90typedef enum dt_aon_timer_wakeup {
91 kDtAonTimerWakeupWkupReq = 0, /**< Raised if the wakeup or watchdog timer has hit the specified threshold. */
92 kDtAonTimerWakeupCount = 1, /**< \internal Number of wakeups */
94
95/**
96 * List of supported hardware features.
97 */
98#define OPENTITAN_AON_TIMER_HAS_WAKEUP_WAKEUP_CONFIG 1
99#define OPENTITAN_AON_TIMER_HAS_WAKEUP_WAKEUP_REQUEST 1
100#define OPENTITAN_AON_TIMER_HAS_WAKEUP_INTERRUPT 1
101#define OPENTITAN_AON_TIMER_HAS_WATCHDOG_BARK 1
102#define OPENTITAN_AON_TIMER_HAS_WATCHDOG_BITE 1
103#define OPENTITAN_AON_TIMER_HAS_WATCHDOG_PAUSE 1
104#define OPENTITAN_AON_TIMER_HAS_WATCHDOG_DISABLE_BY_LC_CTRL 1
105#define OPENTITAN_AON_TIMER_HAS_WATCHDOG_INTERRUPT 1
106
107
108
109/**
110 * Get the aon_timer instance from an instance ID
111 *
112 * For example, `dt_uart_from_instance_id(kDtInstanceIdUart3) == kDtUart3`.
113 *
114 * @param inst_id Instance ID.
115 * @return A aon_timer instance.
116 *
117 * **Note:** This function only makes sense if the instance ID has device type aon_timer,
118 * otherwise the returned value is unspecified.
119 */
121
122/**
123 * Get the instance ID of an instance.
124 *
125 * @param dt Instance of aon_timer.
126 * @return The instance ID of that instance.
127 */
129
130/**
131 * Get the register base address of an instance.
132 *
133 * @param dt Instance of aon_timer.
134 * @param reg_block The register block requested.
135 * @return The register base address of the requested block.
136 */
139 dt_aon_timer_reg_block_t reg_block);
140
141/**
142 * Get the primary register base address of an instance.
143 *
144 * This is just a convenience function, equivalent to
145 * `dt_aon_timer_reg_block(dt, kDtAonTimerRegBlockCore)`
146 *
147 * @param dt Instance of aon_timer.
148 * @return The register base address of the primary register block.
149 */
150static inline uint32_t dt_aon_timer_primary_reg_block(
151 dt_aon_timer_t dt) {
152 return dt_aon_timer_reg_block(dt, kDtAonTimerRegBlockCore);
153}
154
155/**
156 * Get the PLIC ID of a aon_timer IRQ for a given instance.
157 *
158 * If the instance is not connected to the PLIC, this function
159 * will return `kDtPlicIrqIdNone`.
160 *
161 * @param dt Instance of aon_timer.
162 * @param irq A aon_timer IRQ.
163 * @return The PLIC ID of the IRQ of this instance.
164 */
168
169/**
170 * Convert a global IRQ ID to a local aon_timer IRQ type.
171 *
172 * @param dt Instance of aon_timer.
173 * @param irq A PLIC ID that belongs to this instance.
174 * @return The aon_timer IRQ, or `kDtAonTimerIrqCount`.
175 *
176 * **Note:** This function assumes that the PLIC ID belongs to the instance
177 * of aon_timer passed in parameter. In other words, it must be the case that
178 * `dt_aon_timer_instance_id(dt) == dt_plic_id_to_instance_id(irq)`. Otherwise, this function
179 * will return `kDtAonTimerIrqCount`.
180 */
183 dt_plic_irq_id_t irq);
184
185
186
187
188/**
189 * Get the clock signal connected to a clock port of an instance.
190 *
191 * @param dt Instance of aon_timer.
192 * @param clk Clock port.
193 * @return Clock signal.
194 */
198
199/**
200 * Get the reset signal connected to a reset port of an instance.
201 *
202 * @param dt Instance of aon_timer.
203 * @param rst Reset port.
204 * @return Reset signal.
205 */
209
210
211
212#endif // OPENTITAN_DT_AON_TIMER_H_