Software APIs
dif_spi_device_autogen.c
1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
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11// THIS FILE HAS BEEN GENERATED, DO NOT EDIT MANUALLY. COMMAND:
12// util/autogen_dif.py -i hw/ip/spi_device/data/spi_device.hjson -o
13// bazel-out/k8-fastbuild/bin/sw/device/lib/dif/autogen
14
15
16#include <stdint.h>
17
18#include "sw/device/lib/dif/dif_base.h"
19#include "sw/device/lib/dif/autogen/dif_spi_device_autogen.h"
20
21#include "hw/top/spi_device_regs.h" // Generated.
22
23
24OT_WARN_UNUSED_RESULT
25dif_result_t dif_spi_device_init(
26 mmio_region_t base_addr,
27 dif_spi_device_t *spi_device) {
28 if (spi_device == NULL) {
29 return kDifBadArg;
30 }
31
32 spi_device->dt = kDtSpiDeviceCount;
33 spi_device->base_addr = base_addr;
34
35 return kDifOk;
36}
37
38OT_WARN_UNUSED_RESULT
39dif_result_t dif_spi_device_init_from_dt(
40 dt_spi_device_t dt,
41 dif_spi_device_t *spi_device) {
42 if (spi_device == NULL) {
43 return kDifBadArg;
44 }
45
46 spi_device->dt = dt;
47 spi_device->base_addr = mmio_region_from_addr(dt_spi_device_primary_reg_block(dt));
48
49 return kDifOk;
50}
51
52dif_result_t dif_spi_device_get_dt(
53 const dif_spi_device_t *spi_device,
54 dt_spi_device_t *dt) {
55 if ((int)spi_device->dt == kDtSpiDeviceCount || dt == NULL) {
56 return kDifBadArg;
57 }
58 *dt = spi_device->dt;
59 return kDifOk;
60}
61
62 dif_result_t dif_spi_device_alert_force(
63 const dif_spi_device_t *spi_device,
64 dif_spi_device_alert_t alert) {
65 if (spi_device == NULL) {
66 return kDifBadArg;
67 }
68
69 bitfield_bit32_index_t alert_idx;
70 switch (alert) {
71 case kDifSpiDeviceAlertFatalFault:
72 alert_idx = SPI_DEVICE_ALERT_TEST_FATAL_FAULT_BIT;
73 break;
74 default:
75 return kDifBadArg;
76 }
77
78 uint32_t alert_test_reg = bitfield_bit32_write(0, alert_idx, true);
79 mmio_region_write32(
80 spi_device->base_addr,
81 (ptrdiff_t)SPI_DEVICE_ALERT_TEST_REG_OFFSET,
82 alert_test_reg);
83
84
85 return kDifOk;
86}
87
88
89 /**
90 * Get the corresponding interrupt register bit offset of the IRQ.
91 */
92 static bool spi_device_get_irq_bit_index(
93 dif_spi_device_irq_t irq,
94 bitfield_bit32_index_t *index_out) {
95
96 switch (irq) {
97 case kDtSpiDeviceIrqUploadCmdfifoNotEmpty:
98 *index_out = SPI_DEVICE_INTR_COMMON_UPLOAD_CMDFIFO_NOT_EMPTY_BIT;
99 break;
100 case kDtSpiDeviceIrqUploadPayloadNotEmpty:
101 *index_out = SPI_DEVICE_INTR_COMMON_UPLOAD_PAYLOAD_NOT_EMPTY_BIT;
102 break;
103 case kDtSpiDeviceIrqUploadPayloadOverflow:
104 *index_out = SPI_DEVICE_INTR_COMMON_UPLOAD_PAYLOAD_OVERFLOW_BIT;
105 break;
106 case kDtSpiDeviceIrqReadbufWatermark:
107 *index_out = SPI_DEVICE_INTR_COMMON_READBUF_WATERMARK_BIT;
108 break;
109 case kDtSpiDeviceIrqReadbufFlip:
110 *index_out = SPI_DEVICE_INTR_COMMON_READBUF_FLIP_BIT;
111 break;
112 case kDtSpiDeviceIrqTpmHeaderNotEmpty:
113 *index_out = SPI_DEVICE_INTR_COMMON_TPM_HEADER_NOT_EMPTY_BIT;
114 break;
115 case kDtSpiDeviceIrqTpmRdfifoCmdEnd:
116 *index_out = SPI_DEVICE_INTR_COMMON_TPM_RDFIFO_CMD_END_BIT;
117 break;
118 case kDtSpiDeviceIrqTpmRdfifoDrop:
119 *index_out = SPI_DEVICE_INTR_COMMON_TPM_RDFIFO_DROP_BIT;
120 break;
121 default:
122 return false;
123 }
124
125 return true;
126 }
127
128 static dif_irq_type_t irq_types[] = {
129 kDifIrqTypeEvent,
130 kDifIrqTypeEvent,
131 kDifIrqTypeEvent,
132 kDifIrqTypeEvent,
133 kDifIrqTypeEvent,
134 kDifIrqTypeStatus,
135 kDifIrqTypeEvent,
136 kDifIrqTypeEvent,
137 };
138
139 OT_WARN_UNUSED_RESULT
140 dif_result_t dif_spi_device_irq_get_type(
141 const dif_spi_device_t *spi_device,
142 dif_spi_device_irq_t irq,
143 dif_irq_type_t *type) {
144
145
146 if (spi_device == NULL ||
147 type == NULL ||
148 irq < kDifSpiDeviceIrqUploadCmdfifoNotEmpty ||
149 irq > kDifSpiDeviceIrqTpmRdfifoDrop) {
150 return kDifBadArg;
151 }
152
153 *type = irq_types[irq];
154
155 return kDifOk;
156 }
157
158 OT_WARN_UNUSED_RESULT
159 dif_result_t dif_spi_device_irq_get_state(
160 const dif_spi_device_t *spi_device,
161 dif_spi_device_irq_state_snapshot_t *snapshot) {
162
163 if (spi_device == NULL || snapshot == NULL) {
164 return kDifBadArg;
165 }
166
167 *snapshot = mmio_region_read32(
168 spi_device->base_addr,
169 (ptrdiff_t)SPI_DEVICE_INTR_STATE_REG_OFFSET);
170
171
172 return kDifOk;
173 }
174
175 OT_WARN_UNUSED_RESULT
176 dif_result_t dif_spi_device_irq_acknowledge_state(
177 const dif_spi_device_t *spi_device,
178 dif_spi_device_irq_state_snapshot_t snapshot) {
179 if (spi_device == NULL) {
180 return kDifBadArg;
181 }
182
183 mmio_region_write32(
184 spi_device->base_addr,
185 (ptrdiff_t)SPI_DEVICE_INTR_STATE_REG_OFFSET,
186 snapshot);
187
188
189 return kDifOk;
190 }
191
192 OT_WARN_UNUSED_RESULT
193 dif_result_t dif_spi_device_irq_is_pending(
194 const dif_spi_device_t *spi_device,
195 dif_spi_device_irq_t irq,
196 bool *is_pending) {
197
198 if (spi_device == NULL || is_pending == NULL) {
199 return kDifBadArg;
200 }
201
202 bitfield_bit32_index_t index;
203 if (!spi_device_get_irq_bit_index(irq, &index)) {
204 return kDifBadArg;
205 }
206
207 uint32_t intr_state_reg = mmio_region_read32(
208 spi_device->base_addr,
209 (ptrdiff_t)SPI_DEVICE_INTR_STATE_REG_OFFSET);
210
211
212 *is_pending = bitfield_bit32_read(intr_state_reg, index);
213
214 return kDifOk;
215 }
216
217 OT_WARN_UNUSED_RESULT
218 dif_result_t dif_spi_device_irq_acknowledge_all(
219 const dif_spi_device_t *spi_device
220 ) {
221
222 if (spi_device == NULL) {
223 return kDifBadArg;
224 }
225
226 // Writing to the register clears the corresponding bits (Write-one clear).
227 mmio_region_write32(
228 spi_device->base_addr,
229 (ptrdiff_t)SPI_DEVICE_INTR_STATE_REG_OFFSET,
230 UINT32_MAX);
231
232
233 return kDifOk;
234 }
235
236 OT_WARN_UNUSED_RESULT
237 dif_result_t dif_spi_device_irq_acknowledge(
238 const dif_spi_device_t *spi_device,
239 dif_spi_device_irq_t irq) {
240
241 if (spi_device == NULL) {
242 return kDifBadArg;
243 }
244
245 bitfield_bit32_index_t index;
246 if (!spi_device_get_irq_bit_index(irq, &index)) {
247 return kDifBadArg;
248 }
249
250 // Writing to the register clears the corresponding bits (Write-one clear).
251 uint32_t intr_state_reg = bitfield_bit32_write(0, index, true);
252 mmio_region_write32(
253 spi_device->base_addr,
254 (ptrdiff_t)SPI_DEVICE_INTR_STATE_REG_OFFSET,
255 intr_state_reg);
256
257
258 return kDifOk;
259 }
260
261 OT_WARN_UNUSED_RESULT
262 dif_result_t dif_spi_device_irq_force(
263 const dif_spi_device_t *spi_device,
264 dif_spi_device_irq_t irq,
265 const bool val) {
266
267 if (spi_device == NULL) {
268 return kDifBadArg;
269 }
270
271 bitfield_bit32_index_t index;
272 if (!spi_device_get_irq_bit_index(irq, &index)) {
273 return kDifBadArg;
274 }
275
276 uint32_t intr_test_reg = bitfield_bit32_write(0, index, val);
277 mmio_region_write32(
278 spi_device->base_addr,
279 (ptrdiff_t)SPI_DEVICE_INTR_TEST_REG_OFFSET,
280 intr_test_reg);
281
282
283 return kDifOk;
284 }
285
286 OT_WARN_UNUSED_RESULT
287 dif_result_t dif_spi_device_irq_get_enabled(
288 const dif_spi_device_t *spi_device,
289 dif_spi_device_irq_t irq,
290 dif_toggle_t *state) {
291
292 if (spi_device == NULL || state == NULL) {
293 return kDifBadArg;
294 }
295
296 bitfield_bit32_index_t index;
297 if (!spi_device_get_irq_bit_index(irq, &index)) {
298 return kDifBadArg;
299 }
300
301 uint32_t intr_enable_reg = mmio_region_read32(
302 spi_device->base_addr,
303 (ptrdiff_t)SPI_DEVICE_INTR_ENABLE_REG_OFFSET);
304
305
306 bool is_enabled = bitfield_bit32_read(intr_enable_reg, index);
307 *state = is_enabled ?
308 kDifToggleEnabled : kDifToggleDisabled;
309
310 return kDifOk;
311 }
312
313 OT_WARN_UNUSED_RESULT
314 dif_result_t dif_spi_device_irq_set_enabled(
315 const dif_spi_device_t *spi_device,
316 dif_spi_device_irq_t irq,
317 dif_toggle_t state) {
318
319 if (spi_device == NULL) {
320 return kDifBadArg;
321 }
322
323 bitfield_bit32_index_t index;
324 if (!spi_device_get_irq_bit_index(irq, &index)) {
325 return kDifBadArg;
326 }
327
328 uint32_t intr_enable_reg = mmio_region_read32(
329 spi_device->base_addr,
330 (ptrdiff_t)SPI_DEVICE_INTR_ENABLE_REG_OFFSET);
331
332
333 bool enable_bit = (state == kDifToggleEnabled) ? true : false;
334 intr_enable_reg = bitfield_bit32_write(intr_enable_reg, index, enable_bit);
335 mmio_region_write32(
336 spi_device->base_addr,
337 (ptrdiff_t)SPI_DEVICE_INTR_ENABLE_REG_OFFSET,
338 intr_enable_reg);
339
340
341 return kDifOk;
342 }
343
344 OT_WARN_UNUSED_RESULT
345 dif_result_t dif_spi_device_irq_disable_all(
346 const dif_spi_device_t *spi_device,
347 dif_spi_device_irq_enable_snapshot_t *snapshot) {
348
349 if (spi_device == NULL) {
350 return kDifBadArg;
351 }
352
353 // Pass the current interrupt state to the caller, if requested.
354 if (snapshot != NULL) {
355 *snapshot = mmio_region_read32(
356 spi_device->base_addr,
357 (ptrdiff_t)SPI_DEVICE_INTR_ENABLE_REG_OFFSET);
358
359 }
360
361 // Disable all interrupts.
362 mmio_region_write32(
363 spi_device->base_addr,
364 (ptrdiff_t)SPI_DEVICE_INTR_ENABLE_REG_OFFSET,
365 0u);
366
367
368 return kDifOk;
369 }
370
371 OT_WARN_UNUSED_RESULT
372 dif_result_t dif_spi_device_irq_restore_all(
373 const dif_spi_device_t *spi_device,
374 const dif_spi_device_irq_enable_snapshot_t *snapshot) {
375
376 if (spi_device == NULL || snapshot == NULL) {
377 return kDifBadArg;
378 }
379
380 mmio_region_write32(
381 spi_device->base_addr,
382 (ptrdiff_t)SPI_DEVICE_INTR_ENABLE_REG_OFFSET,
383 *snapshot);
384
385
386 return kDifOk;
387 }
388