Software APIs
dif_flash_ctrl_autogen.c
1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
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11// THIS FILE HAS BEEN GENERATED, DO NOT EDIT MANUALLY. COMMAND:
12// util/autogen_dif.py -i
13// hw/top_earlgrey/ip_autogen/flash_ctrl/data/flash_ctrl.hjson -o
14// bazel-out/k8-fastbuild/bin/sw/device/lib/dif/autogen
15
16
17#include <stdint.h>
18
19#include "sw/device/lib/dif/dif_base.h"
20#include "sw/device/lib/dif/autogen/dif_flash_ctrl_autogen.h"
21
22#include "hw/top/flash_ctrl_regs.h" // Generated.
23
24
25OT_WARN_UNUSED_RESULT
26dif_result_t dif_flash_ctrl_init(
27 mmio_region_t base_addr,
28 dif_flash_ctrl_t *flash_ctrl) {
29 if (flash_ctrl == NULL) {
30 return kDifBadArg;
31 }
32
33 flash_ctrl->dt = kDtFlashCtrlCount;
34 flash_ctrl->base_addr = base_addr;
35
36 return kDifOk;
37}
38
39OT_WARN_UNUSED_RESULT
40dif_result_t dif_flash_ctrl_init_from_dt(
41 dt_flash_ctrl_t dt,
42 dif_flash_ctrl_t *flash_ctrl) {
43 if (flash_ctrl == NULL) {
44 return kDifBadArg;
45 }
46
47 flash_ctrl->dt = dt;
48 flash_ctrl->base_addr = mmio_region_from_addr(dt_flash_ctrl_primary_reg_block(dt));
49
50 return kDifOk;
51}
52
53dif_result_t dif_flash_ctrl_get_dt(
54 const dif_flash_ctrl_t *flash_ctrl,
55 dt_flash_ctrl_t *dt) {
56 if (flash_ctrl->dt == kDtFlashCtrlCount || dt == NULL) {
57 return kDifBadArg;
58 }
59 *dt = flash_ctrl->dt;
60 return kDifOk;
61}
62
63 dif_result_t dif_flash_ctrl_alert_force(
64 const dif_flash_ctrl_t *flash_ctrl,
65 dif_flash_ctrl_alert_t alert) {
66 if (flash_ctrl == NULL) {
67 return kDifBadArg;
68 }
69
70 bitfield_bit32_index_t alert_idx;
71 switch (alert) {
72 case kDifFlashCtrlAlertRecovErr:
73 alert_idx = FLASH_CTRL_ALERT_TEST_RECOV_ERR_BIT;
74 break;
75 case kDifFlashCtrlAlertFatalStdErr:
76 alert_idx = FLASH_CTRL_ALERT_TEST_FATAL_STD_ERR_BIT;
77 break;
78 case kDifFlashCtrlAlertFatalErr:
79 alert_idx = FLASH_CTRL_ALERT_TEST_FATAL_ERR_BIT;
80 break;
81 case kDifFlashCtrlAlertFatalPrimFlashAlert:
82 alert_idx = FLASH_CTRL_ALERT_TEST_FATAL_PRIM_FLASH_ALERT_BIT;
83 break;
84 case kDifFlashCtrlAlertRecovPrimFlashAlert:
85 alert_idx = FLASH_CTRL_ALERT_TEST_RECOV_PRIM_FLASH_ALERT_BIT;
86 break;
87 default:
88 return kDifBadArg;
89 }
90
91 uint32_t alert_test_reg = bitfield_bit32_write(0, alert_idx, true);
92 mmio_region_write32(
93 flash_ctrl->base_addr,
94 (ptrdiff_t)FLASH_CTRL_ALERT_TEST_REG_OFFSET,
95 alert_test_reg);
96
97
98 return kDifOk;
99}
100
101
102 /**
103 * Get the corresponding interrupt register bit offset of the IRQ.
104 */
105 static bool flash_ctrl_get_irq_bit_index(
106 dif_flash_ctrl_irq_t irq,
107 bitfield_bit32_index_t *index_out) {
108
109 switch (irq) {
110 case kDtFlashCtrlIrqProgEmpty:
111 *index_out = FLASH_CTRL_INTR_COMMON_PROG_EMPTY_BIT;
112 break;
113 case kDtFlashCtrlIrqProgLvl:
114 *index_out = FLASH_CTRL_INTR_COMMON_PROG_LVL_BIT;
115 break;
116 case kDtFlashCtrlIrqRdFull:
117 *index_out = FLASH_CTRL_INTR_COMMON_RD_FULL_BIT;
118 break;
119 case kDtFlashCtrlIrqRdLvl:
120 *index_out = FLASH_CTRL_INTR_COMMON_RD_LVL_BIT;
121 break;
122 case kDtFlashCtrlIrqOpDone:
123 *index_out = FLASH_CTRL_INTR_COMMON_OP_DONE_BIT;
124 break;
125 case kDtFlashCtrlIrqCorrErr:
126 *index_out = FLASH_CTRL_INTR_COMMON_CORR_ERR_BIT;
127 break;
128 default:
129 return false;
130 }
131
132 return true;
133 }
134
135 static dif_irq_type_t irq_types[] = {
136 kDifIrqTypeStatus,
137 kDifIrqTypeStatus,
138 kDifIrqTypeStatus,
139 kDifIrqTypeStatus,
140 kDifIrqTypeEvent,
141 kDifIrqTypeEvent,
142 };
143
144 OT_WARN_UNUSED_RESULT
145 dif_result_t dif_flash_ctrl_irq_get_type(
146 const dif_flash_ctrl_t *flash_ctrl,
147 dif_flash_ctrl_irq_t irq,
148 dif_irq_type_t *type) {
149
150
151 if (flash_ctrl == NULL ||
152 type == NULL ||
153 irq < kDifFlashCtrlIrqProgEmpty ||
154 irq > kDifFlashCtrlIrqCorrErr) {
155 return kDifBadArg;
156 }
157
158 *type = irq_types[irq];
159
160 return kDifOk;
161 }
162
163 OT_WARN_UNUSED_RESULT
164 dif_result_t dif_flash_ctrl_irq_get_state(
165 const dif_flash_ctrl_t *flash_ctrl,
166 dif_flash_ctrl_irq_state_snapshot_t *snapshot) {
167
168 if (flash_ctrl == NULL || snapshot == NULL) {
169 return kDifBadArg;
170 }
171
172 *snapshot = mmio_region_read32(
173 flash_ctrl->base_addr,
174 (ptrdiff_t)FLASH_CTRL_INTR_STATE_REG_OFFSET);
175
176
177 return kDifOk;
178 }
179
180 OT_WARN_UNUSED_RESULT
181 dif_result_t dif_flash_ctrl_irq_acknowledge_state(
182 const dif_flash_ctrl_t *flash_ctrl,
183 dif_flash_ctrl_irq_state_snapshot_t snapshot) {
184 if (flash_ctrl == NULL) {
185 return kDifBadArg;
186 }
187
188 mmio_region_write32(
189 flash_ctrl->base_addr,
190 (ptrdiff_t)FLASH_CTRL_INTR_STATE_REG_OFFSET,
191 snapshot);
192
193
194 return kDifOk;
195 }
196
197 OT_WARN_UNUSED_RESULT
198 dif_result_t dif_flash_ctrl_irq_is_pending(
199 const dif_flash_ctrl_t *flash_ctrl,
200 dif_flash_ctrl_irq_t irq,
201 bool *is_pending) {
202
203 if (flash_ctrl == NULL || is_pending == NULL) {
204 return kDifBadArg;
205 }
206
207 bitfield_bit32_index_t index;
208 if (!flash_ctrl_get_irq_bit_index(irq, &index)) {
209 return kDifBadArg;
210 }
211
212 uint32_t intr_state_reg = mmio_region_read32(
213 flash_ctrl->base_addr,
214 (ptrdiff_t)FLASH_CTRL_INTR_STATE_REG_OFFSET);
215
216
217 *is_pending = bitfield_bit32_read(intr_state_reg, index);
218
219 return kDifOk;
220 }
221
222 OT_WARN_UNUSED_RESULT
223 dif_result_t dif_flash_ctrl_irq_acknowledge_all(
224 const dif_flash_ctrl_t *flash_ctrl
225 ) {
226
227 if (flash_ctrl == NULL) {
228 return kDifBadArg;
229 }
230
231 // Writing to the register clears the corresponding bits (Write-one clear).
232 mmio_region_write32(
233 flash_ctrl->base_addr,
234 (ptrdiff_t)FLASH_CTRL_INTR_STATE_REG_OFFSET,
235 UINT32_MAX);
236
237
238 return kDifOk;
239 }
240
241 OT_WARN_UNUSED_RESULT
242 dif_result_t dif_flash_ctrl_irq_acknowledge(
243 const dif_flash_ctrl_t *flash_ctrl,
244 dif_flash_ctrl_irq_t irq) {
245
246 if (flash_ctrl == NULL) {
247 return kDifBadArg;
248 }
249
250 bitfield_bit32_index_t index;
251 if (!flash_ctrl_get_irq_bit_index(irq, &index)) {
252 return kDifBadArg;
253 }
254
255 // Writing to the register clears the corresponding bits (Write-one clear).
256 uint32_t intr_state_reg = bitfield_bit32_write(0, index, true);
257 mmio_region_write32(
258 flash_ctrl->base_addr,
259 (ptrdiff_t)FLASH_CTRL_INTR_STATE_REG_OFFSET,
260 intr_state_reg);
261
262
263 return kDifOk;
264 }
265
266 OT_WARN_UNUSED_RESULT
267 dif_result_t dif_flash_ctrl_irq_force(
268 const dif_flash_ctrl_t *flash_ctrl,
269 dif_flash_ctrl_irq_t irq,
270 const bool val) {
271
272 if (flash_ctrl == NULL) {
273 return kDifBadArg;
274 }
275
276 bitfield_bit32_index_t index;
277 if (!flash_ctrl_get_irq_bit_index(irq, &index)) {
278 return kDifBadArg;
279 }
280
281 uint32_t intr_test_reg = bitfield_bit32_write(0, index, val);
282 mmio_region_write32(
283 flash_ctrl->base_addr,
284 (ptrdiff_t)FLASH_CTRL_INTR_TEST_REG_OFFSET,
285 intr_test_reg);
286
287
288 return kDifOk;
289 }
290
291 OT_WARN_UNUSED_RESULT
292 dif_result_t dif_flash_ctrl_irq_get_enabled(
293 const dif_flash_ctrl_t *flash_ctrl,
294 dif_flash_ctrl_irq_t irq,
295 dif_toggle_t *state) {
296
297 if (flash_ctrl == NULL || state == NULL) {
298 return kDifBadArg;
299 }
300
301 bitfield_bit32_index_t index;
302 if (!flash_ctrl_get_irq_bit_index(irq, &index)) {
303 return kDifBadArg;
304 }
305
306 uint32_t intr_enable_reg = mmio_region_read32(
307 flash_ctrl->base_addr,
308 (ptrdiff_t)FLASH_CTRL_INTR_ENABLE_REG_OFFSET);
309
310
311 bool is_enabled = bitfield_bit32_read(intr_enable_reg, index);
312 *state = is_enabled ?
313 kDifToggleEnabled : kDifToggleDisabled;
314
315 return kDifOk;
316 }
317
318 OT_WARN_UNUSED_RESULT
319 dif_result_t dif_flash_ctrl_irq_set_enabled(
320 const dif_flash_ctrl_t *flash_ctrl,
321 dif_flash_ctrl_irq_t irq,
322 dif_toggle_t state) {
323
324 if (flash_ctrl == NULL) {
325 return kDifBadArg;
326 }
327
328 bitfield_bit32_index_t index;
329 if (!flash_ctrl_get_irq_bit_index(irq, &index)) {
330 return kDifBadArg;
331 }
332
333 uint32_t intr_enable_reg = mmio_region_read32(
334 flash_ctrl->base_addr,
335 (ptrdiff_t)FLASH_CTRL_INTR_ENABLE_REG_OFFSET);
336
337
338 bool enable_bit = (state == kDifToggleEnabled) ? true : false;
339 intr_enable_reg = bitfield_bit32_write(intr_enable_reg, index, enable_bit);
340 mmio_region_write32(
341 flash_ctrl->base_addr,
342 (ptrdiff_t)FLASH_CTRL_INTR_ENABLE_REG_OFFSET,
343 intr_enable_reg);
344
345
346 return kDifOk;
347 }
348
349 OT_WARN_UNUSED_RESULT
350 dif_result_t dif_flash_ctrl_irq_disable_all(
351 const dif_flash_ctrl_t *flash_ctrl,
352 dif_flash_ctrl_irq_enable_snapshot_t *snapshot) {
353
354 if (flash_ctrl == NULL) {
355 return kDifBadArg;
356 }
357
358 // Pass the current interrupt state to the caller, if requested.
359 if (snapshot != NULL) {
360 *snapshot = mmio_region_read32(
361 flash_ctrl->base_addr,
362 (ptrdiff_t)FLASH_CTRL_INTR_ENABLE_REG_OFFSET);
363
364 }
365
366 // Disable all interrupts.
367 mmio_region_write32(
368 flash_ctrl->base_addr,
369 (ptrdiff_t)FLASH_CTRL_INTR_ENABLE_REG_OFFSET,
370 0u);
371
372
373 return kDifOk;
374 }
375
376 OT_WARN_UNUSED_RESULT
377 dif_result_t dif_flash_ctrl_irq_restore_all(
378 const dif_flash_ctrl_t *flash_ctrl,
379 const dif_flash_ctrl_irq_enable_snapshot_t *snapshot) {
380
381 if (flash_ctrl == NULL || snapshot == NULL) {
382 return kDifBadArg;
383 }
384
385 mmio_region_write32(
386 flash_ctrl->base_addr,
387 (ptrdiff_t)FLASH_CTRL_INTR_ENABLE_REG_OFFSET,
388 *snapshot);
389
390
391 return kDifOk;
392 }
393