Software APIs
dif_csrng_autogen.c
1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
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11// THIS FILE HAS BEEN GENERATED, DO NOT EDIT MANUALLY. COMMAND:
12// util/autogen_dif.py -i hw/ip/csrng/data/csrng.hjson -o
13// bazel-out/k8-fastbuild/bin/sw/device/lib/dif/autogen
14
15
16#include <stdint.h>
17
18#include "sw/device/lib/dif/dif_base.h"
19#include "sw/device/lib/dif/autogen/dif_csrng_autogen.h"
20
21#include "hw/top/csrng_regs.h" // Generated.
22
23
24OT_WARN_UNUSED_RESULT
25dif_result_t dif_csrng_init(
26 mmio_region_t base_addr,
27 dif_csrng_t *csrng) {
28 if (csrng == NULL) {
29 return kDifBadArg;
30 }
31
32 csrng->dt = kDtCsrngCount;
33 csrng->base_addr = base_addr;
34
35 return kDifOk;
36}
37
38OT_WARN_UNUSED_RESULT
39dif_result_t dif_csrng_init_from_dt(
40 dt_csrng_t dt,
41 dif_csrng_t *csrng) {
42 if (csrng == NULL) {
43 return kDifBadArg;
44 }
45
46 csrng->dt = dt;
47 csrng->base_addr = mmio_region_from_addr(dt_csrng_primary_reg_block(dt));
48
49 return kDifOk;
50}
51
52dif_result_t dif_csrng_get_dt(
53 const dif_csrng_t *csrng,
54 dt_csrng_t *dt) {
55 if ((int)csrng->dt == kDtCsrngCount || dt == NULL) {
56 return kDifBadArg;
57 }
58 *dt = csrng->dt;
59 return kDifOk;
60}
61
62 dif_result_t dif_csrng_alert_force(
63 const dif_csrng_t *csrng,
64 dif_csrng_alert_t alert) {
65 if (csrng == NULL) {
66 return kDifBadArg;
67 }
68
69 bitfield_bit32_index_t alert_idx;
70 switch (alert) {
71 case kDifCsrngAlertRecovAlert:
72 alert_idx = CSRNG_ALERT_TEST_RECOV_ALERT_BIT;
73 break;
74 case kDifCsrngAlertFatalAlert:
75 alert_idx = CSRNG_ALERT_TEST_FATAL_ALERT_BIT;
76 break;
77 default:
78 return kDifBadArg;
79 }
80
81 uint32_t alert_test_reg = bitfield_bit32_write(0, alert_idx, true);
82 mmio_region_write32(
83 csrng->base_addr,
84 (ptrdiff_t)CSRNG_ALERT_TEST_REG_OFFSET,
85 alert_test_reg);
86
87
88 return kDifOk;
89}
90
91
92 /**
93 * Get the corresponding interrupt register bit offset of the IRQ.
94 */
95 static bool csrng_get_irq_bit_index(
96 dif_csrng_irq_t irq,
97 bitfield_bit32_index_t *index_out) {
98
99 switch (irq) {
100 case kDtCsrngIrqCsCmdReqDone:
101 *index_out = CSRNG_INTR_COMMON_CS_CMD_REQ_DONE_BIT;
102 break;
103 case kDtCsrngIrqCsEntropyReq:
104 *index_out = CSRNG_INTR_COMMON_CS_ENTROPY_REQ_BIT;
105 break;
106 case kDtCsrngIrqCsHwInstExc:
107 *index_out = CSRNG_INTR_COMMON_CS_HW_INST_EXC_BIT;
108 break;
109 case kDtCsrngIrqCsFatalErr:
110 *index_out = CSRNG_INTR_COMMON_CS_FATAL_ERR_BIT;
111 break;
112 default:
113 return false;
114 }
115
116 return true;
117 }
118
119 static dif_irq_type_t irq_types[] = {
120 kDifIrqTypeEvent,
121 kDifIrqTypeEvent,
122 kDifIrqTypeEvent,
123 kDifIrqTypeEvent,
124 };
125
126 OT_WARN_UNUSED_RESULT
127 dif_result_t dif_csrng_irq_get_type(
128 const dif_csrng_t *csrng,
129 dif_csrng_irq_t irq,
130 dif_irq_type_t *type) {
131
132
133 if (csrng == NULL ||
134 type == NULL ||
135 irq < kDifCsrngIrqCsCmdReqDone ||
136 irq > kDifCsrngIrqCsFatalErr) {
137 return kDifBadArg;
138 }
139
140 *type = irq_types[irq];
141
142 return kDifOk;
143 }
144
145 OT_WARN_UNUSED_RESULT
146 dif_result_t dif_csrng_irq_get_state(
147 const dif_csrng_t *csrng,
148 dif_csrng_irq_state_snapshot_t *snapshot) {
149
150 if (csrng == NULL || snapshot == NULL) {
151 return kDifBadArg;
152 }
153
154 *snapshot = mmio_region_read32(
155 csrng->base_addr,
156 (ptrdiff_t)CSRNG_INTR_STATE_REG_OFFSET);
157
158
159 return kDifOk;
160 }
161
162 OT_WARN_UNUSED_RESULT
163 dif_result_t dif_csrng_irq_acknowledge_state(
164 const dif_csrng_t *csrng,
165 dif_csrng_irq_state_snapshot_t snapshot) {
166 if (csrng == NULL) {
167 return kDifBadArg;
168 }
169
170 mmio_region_write32(
171 csrng->base_addr,
172 (ptrdiff_t)CSRNG_INTR_STATE_REG_OFFSET,
173 snapshot);
174
175
176 return kDifOk;
177 }
178
179 OT_WARN_UNUSED_RESULT
180 dif_result_t dif_csrng_irq_is_pending(
181 const dif_csrng_t *csrng,
182 dif_csrng_irq_t irq,
183 bool *is_pending) {
184
185 if (csrng == NULL || is_pending == NULL) {
186 return kDifBadArg;
187 }
188
189 bitfield_bit32_index_t index;
190 if (!csrng_get_irq_bit_index(irq, &index)) {
191 return kDifBadArg;
192 }
193
194 uint32_t intr_state_reg = mmio_region_read32(
195 csrng->base_addr,
196 (ptrdiff_t)CSRNG_INTR_STATE_REG_OFFSET);
197
198
199 *is_pending = bitfield_bit32_read(intr_state_reg, index);
200
201 return kDifOk;
202 }
203
204 OT_WARN_UNUSED_RESULT
205 dif_result_t dif_csrng_irq_acknowledge_all(
206 const dif_csrng_t *csrng
207 ) {
208
209 if (csrng == NULL) {
210 return kDifBadArg;
211 }
212
213 // Writing to the register clears the corresponding bits (Write-one clear).
214 mmio_region_write32(
215 csrng->base_addr,
216 (ptrdiff_t)CSRNG_INTR_STATE_REG_OFFSET,
217 UINT32_MAX);
218
219
220 return kDifOk;
221 }
222
223 OT_WARN_UNUSED_RESULT
224 dif_result_t dif_csrng_irq_acknowledge(
225 const dif_csrng_t *csrng,
226 dif_csrng_irq_t irq) {
227
228 if (csrng == NULL) {
229 return kDifBadArg;
230 }
231
232 bitfield_bit32_index_t index;
233 if (!csrng_get_irq_bit_index(irq, &index)) {
234 return kDifBadArg;
235 }
236
237 // Writing to the register clears the corresponding bits (Write-one clear).
238 uint32_t intr_state_reg = bitfield_bit32_write(0, index, true);
239 mmio_region_write32(
240 csrng->base_addr,
241 (ptrdiff_t)CSRNG_INTR_STATE_REG_OFFSET,
242 intr_state_reg);
243
244
245 return kDifOk;
246 }
247
248 OT_WARN_UNUSED_RESULT
249 dif_result_t dif_csrng_irq_force(
250 const dif_csrng_t *csrng,
251 dif_csrng_irq_t irq,
252 const bool val) {
253
254 if (csrng == NULL) {
255 return kDifBadArg;
256 }
257
258 bitfield_bit32_index_t index;
259 if (!csrng_get_irq_bit_index(irq, &index)) {
260 return kDifBadArg;
261 }
262
263 uint32_t intr_test_reg = bitfield_bit32_write(0, index, val);
264 mmio_region_write32(
265 csrng->base_addr,
266 (ptrdiff_t)CSRNG_INTR_TEST_REG_OFFSET,
267 intr_test_reg);
268
269
270 return kDifOk;
271 }
272
273 OT_WARN_UNUSED_RESULT
274 dif_result_t dif_csrng_irq_get_enabled(
275 const dif_csrng_t *csrng,
276 dif_csrng_irq_t irq,
277 dif_toggle_t *state) {
278
279 if (csrng == NULL || state == NULL) {
280 return kDifBadArg;
281 }
282
283 bitfield_bit32_index_t index;
284 if (!csrng_get_irq_bit_index(irq, &index)) {
285 return kDifBadArg;
286 }
287
288 uint32_t intr_enable_reg = mmio_region_read32(
289 csrng->base_addr,
290 (ptrdiff_t)CSRNG_INTR_ENABLE_REG_OFFSET);
291
292
293 bool is_enabled = bitfield_bit32_read(intr_enable_reg, index);
294 *state = is_enabled ?
295 kDifToggleEnabled : kDifToggleDisabled;
296
297 return kDifOk;
298 }
299
300 OT_WARN_UNUSED_RESULT
301 dif_result_t dif_csrng_irq_set_enabled(
302 const dif_csrng_t *csrng,
303 dif_csrng_irq_t irq,
304 dif_toggle_t state) {
305
306 if (csrng == NULL) {
307 return kDifBadArg;
308 }
309
310 bitfield_bit32_index_t index;
311 if (!csrng_get_irq_bit_index(irq, &index)) {
312 return kDifBadArg;
313 }
314
315 uint32_t intr_enable_reg = mmio_region_read32(
316 csrng->base_addr,
317 (ptrdiff_t)CSRNG_INTR_ENABLE_REG_OFFSET);
318
319
320 bool enable_bit = (state == kDifToggleEnabled) ? true : false;
321 intr_enable_reg = bitfield_bit32_write(intr_enable_reg, index, enable_bit);
322 mmio_region_write32(
323 csrng->base_addr,
324 (ptrdiff_t)CSRNG_INTR_ENABLE_REG_OFFSET,
325 intr_enable_reg);
326
327
328 return kDifOk;
329 }
330
331 OT_WARN_UNUSED_RESULT
332 dif_result_t dif_csrng_irq_disable_all(
333 const dif_csrng_t *csrng,
334 dif_csrng_irq_enable_snapshot_t *snapshot) {
335
336 if (csrng == NULL) {
337 return kDifBadArg;
338 }
339
340 // Pass the current interrupt state to the caller, if requested.
341 if (snapshot != NULL) {
342 *snapshot = mmio_region_read32(
343 csrng->base_addr,
344 (ptrdiff_t)CSRNG_INTR_ENABLE_REG_OFFSET);
345
346 }
347
348 // Disable all interrupts.
349 mmio_region_write32(
350 csrng->base_addr,
351 (ptrdiff_t)CSRNG_INTR_ENABLE_REG_OFFSET,
352 0u);
353
354
355 return kDifOk;
356 }
357
358 OT_WARN_UNUSED_RESULT
359 dif_result_t dif_csrng_irq_restore_all(
360 const dif_csrng_t *csrng,
361 const dif_csrng_irq_enable_snapshot_t *snapshot) {
362
363 if (csrng == NULL || snapshot == NULL) {
364 return kDifBadArg;
365 }
366
367 mmio_region_write32(
368 csrng->base_addr,
369 (ptrdiff_t)CSRNG_INTR_ENABLE_REG_OFFSET,
370 *snapshot);
371
372
373 return kDifOk;
374 }
375