Software APIs
dif_alert_handler_autogen.c
1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4
5
6
7
8
9
10
11// THIS FILE HAS BEEN GENERATED, DO NOT EDIT MANUALLY. COMMAND:
12// util/autogen_dif.py -i
13// hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson -o
14// bazel-out/k8-fastbuild/bin/sw/device/lib/dif/autogen
15
16
17#include <stdint.h>
18
20#include "sw/device/lib/dif/autogen/dif_alert_handler_autogen.h"
21
22#include "hw/top/alert_handler_regs.h" // Generated.
23
24
26dif_result_t dif_alert_handler_init(
27 mmio_region_t base_addr,
28 dif_alert_handler_t *alert_handler) {
29 if (alert_handler == NULL) {
30 return kDifBadArg;
31 }
32
33 alert_handler->dt = kDtAlertHandlerCount;
34 alert_handler->base_addr = base_addr;
35
36 return kDifOk;
37}
38
40dif_result_t dif_alert_handler_init_from_dt(
42 dif_alert_handler_t *alert_handler) {
43 if (alert_handler == NULL) {
44 return kDifBadArg;
45 }
46
47 alert_handler->dt = dt;
48 alert_handler->base_addr = mmio_region_from_addr(dt_alert_handler_primary_reg_block(dt));
49
50 return kDifOk;
51}
52
53dif_result_t dif_alert_handler_get_dt(
54 const dif_alert_handler_t *alert_handler,
56 if ((int)alert_handler->dt == kDtAlertHandlerCount || dt == NULL) {
57 return kDifBadArg;
58 }
59 *dt = alert_handler->dt;
60 return kDifOk;
61}
62
63
64
65 /**
66 * Get the corresponding interrupt register bit offset of the IRQ.
67 */
68 static bool alert_handler_get_irq_bit_index(
69 dif_alert_handler_irq_t irq,
70 bitfield_bit32_index_t *index_out) {
71
72 switch (irq) {
74 *index_out = ALERT_HANDLER_INTR_COMMON_CLASSA_BIT;
75 break;
77 *index_out = ALERT_HANDLER_INTR_COMMON_CLASSB_BIT;
78 break;
80 *index_out = ALERT_HANDLER_INTR_COMMON_CLASSC_BIT;
81 break;
83 *index_out = ALERT_HANDLER_INTR_COMMON_CLASSD_BIT;
84 break;
85 default:
86 return false;
87 }
88
89 return true;
90 }
91
92 static dif_irq_type_t irq_types[] = {
97 };
98
100 dif_result_t dif_alert_handler_irq_get_type(
101 const dif_alert_handler_t *alert_handler,
102 dif_alert_handler_irq_t irq,
103 dif_irq_type_t *type) {
104
105
106 if (alert_handler == NULL ||
107 type == NULL ||
110 return kDifBadArg;
111 }
112
113 *type = irq_types[irq];
114
115 return kDifOk;
116 }
117
119 dif_result_t dif_alert_handler_irq_get_state(
120 const dif_alert_handler_t *alert_handler,
122
123 if (alert_handler == NULL || snapshot == NULL) {
124 return kDifBadArg;
125 }
126
127 *snapshot = mmio_region_read32(
128 alert_handler->base_addr,
129 (ptrdiff_t)ALERT_HANDLER_INTR_STATE_REG_OFFSET);
130
131
132 return kDifOk;
133 }
134
136 dif_result_t dif_alert_handler_irq_acknowledge_state(
137 const dif_alert_handler_t *alert_handler,
139 if (alert_handler == NULL) {
140 return kDifBadArg;
141 }
142
143 mmio_region_write32(
144 alert_handler->base_addr,
145 (ptrdiff_t)ALERT_HANDLER_INTR_STATE_REG_OFFSET,
146 snapshot);
147
148
149 return kDifOk;
150 }
151
153 dif_result_t dif_alert_handler_irq_is_pending(
154 const dif_alert_handler_t *alert_handler,
155 dif_alert_handler_irq_t irq,
156 bool *is_pending) {
157
158 if (alert_handler == NULL || is_pending == NULL) {
159 return kDifBadArg;
160 }
161
163 if (!alert_handler_get_irq_bit_index(irq, &index)) {
164 return kDifBadArg;
165 }
166
167 uint32_t intr_state_reg = mmio_region_read32(
168 alert_handler->base_addr,
169 (ptrdiff_t)ALERT_HANDLER_INTR_STATE_REG_OFFSET);
170
171
172 *is_pending = bitfield_bit32_read(intr_state_reg, index);
173
174 return kDifOk;
175 }
176
178 dif_result_t dif_alert_handler_irq_acknowledge_all(
179 const dif_alert_handler_t *alert_handler
180 ) {
181
182 if (alert_handler == NULL) {
183 return kDifBadArg;
184 }
185
186 // Writing to the register clears the corresponding bits (Write-one clear).
187 mmio_region_write32(
188 alert_handler->base_addr,
189 (ptrdiff_t)ALERT_HANDLER_INTR_STATE_REG_OFFSET,
190 UINT32_MAX);
191
192
193 return kDifOk;
194 }
195
197 dif_result_t dif_alert_handler_irq_acknowledge(
198 const dif_alert_handler_t *alert_handler,
199 dif_alert_handler_irq_t irq) {
200
201 if (alert_handler == NULL) {
202 return kDifBadArg;
203 }
204
206 if (!alert_handler_get_irq_bit_index(irq, &index)) {
207 return kDifBadArg;
208 }
209
210 // Writing to the register clears the corresponding bits (Write-one clear).
211 uint32_t intr_state_reg = bitfield_bit32_write(0, index, true);
212 mmio_region_write32(
213 alert_handler->base_addr,
214 (ptrdiff_t)ALERT_HANDLER_INTR_STATE_REG_OFFSET,
215 intr_state_reg);
216
217
218 return kDifOk;
219 }
220
222 dif_result_t dif_alert_handler_irq_force(
223 const dif_alert_handler_t *alert_handler,
224 dif_alert_handler_irq_t irq,
225 const bool val) {
226
227 if (alert_handler == NULL) {
228 return kDifBadArg;
229 }
230
232 if (!alert_handler_get_irq_bit_index(irq, &index)) {
233 return kDifBadArg;
234 }
235
236 uint32_t intr_test_reg = bitfield_bit32_write(0, index, val);
237 mmio_region_write32(
238 alert_handler->base_addr,
239 (ptrdiff_t)ALERT_HANDLER_INTR_TEST_REG_OFFSET,
240 intr_test_reg);
241
242
243 return kDifOk;
244 }
245
247 dif_result_t dif_alert_handler_irq_get_enabled(
248 const dif_alert_handler_t *alert_handler,
249 dif_alert_handler_irq_t irq,
250 dif_toggle_t *state) {
251
252 if (alert_handler == NULL || state == NULL) {
253 return kDifBadArg;
254 }
255
257 if (!alert_handler_get_irq_bit_index(irq, &index)) {
258 return kDifBadArg;
259 }
260
261 uint32_t intr_enable_reg = mmio_region_read32(
262 alert_handler->base_addr,
263 (ptrdiff_t)ALERT_HANDLER_INTR_ENABLE_REG_OFFSET);
264
265
266 bool is_enabled = bitfield_bit32_read(intr_enable_reg, index);
267 *state = is_enabled ?
269
270 return kDifOk;
271 }
272
274 dif_result_t dif_alert_handler_irq_set_enabled(
275 const dif_alert_handler_t *alert_handler,
276 dif_alert_handler_irq_t irq,
277 dif_toggle_t state) {
278
279 if (alert_handler == NULL) {
280 return kDifBadArg;
281 }
282
284 if (!alert_handler_get_irq_bit_index(irq, &index)) {
285 return kDifBadArg;
286 }
287
288 uint32_t intr_enable_reg = mmio_region_read32(
289 alert_handler->base_addr,
290 (ptrdiff_t)ALERT_HANDLER_INTR_ENABLE_REG_OFFSET);
291
292
293 bool enable_bit = (state == kDifToggleEnabled) ? true : false;
294 intr_enable_reg = bitfield_bit32_write(intr_enable_reg, index, enable_bit);
295 mmio_region_write32(
296 alert_handler->base_addr,
297 (ptrdiff_t)ALERT_HANDLER_INTR_ENABLE_REG_OFFSET,
298 intr_enable_reg);
299
300
301 return kDifOk;
302 }
303
305 dif_result_t dif_alert_handler_irq_disable_all(
306 const dif_alert_handler_t *alert_handler,
308
309 if (alert_handler == NULL) {
310 return kDifBadArg;
311 }
312
313 // Pass the current interrupt state to the caller, if requested.
314 if (snapshot != NULL) {
315 *snapshot = mmio_region_read32(
316 alert_handler->base_addr,
317 (ptrdiff_t)ALERT_HANDLER_INTR_ENABLE_REG_OFFSET);
318
319 }
320
321 // Disable all interrupts.
322 mmio_region_write32(
323 alert_handler->base_addr,
324 (ptrdiff_t)ALERT_HANDLER_INTR_ENABLE_REG_OFFSET,
325 0u);
326
327
328 return kDifOk;
329 }
330
332 dif_result_t dif_alert_handler_irq_restore_all(
333 const dif_alert_handler_t *alert_handler,
335
336 if (alert_handler == NULL || snapshot == NULL) {
337 return kDifBadArg;
338 }
339
340 mmio_region_write32(
341 alert_handler->base_addr,
342 (ptrdiff_t)ALERT_HANDLER_INTR_ENABLE_REG_OFFSET,
343 *snapshot);
344
345
346 return kDifOk;
347 }
348