usbdev_regs.h

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/**
 * @file
 * @brief Generated register defines for usbdev
 */
 
// Copyright information found in source file:
// Copyright lowRISC contributors (OpenTitan project).
 
// Licensing information found in source file:
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
 
#ifndef _USBDEV_REG_DEFS_
#define _USBDEV_REG_DEFS_
 
#ifdef __cplusplus
extern "C" {
#endif
// Number of endpoints
#define USBDEV_PARAM_N_ENDPOINTS 12
 
// Number of alerts
#define USBDEV_PARAM_NUM_ALERTS 1
 
// Register width
#define USBDEV_PARAM_REG_WIDTH 32
 
// Common Interrupt Offsets
#define USBDEV_INTR_COMMON_PKT_RECEIVED_BIT 0
#define USBDEV_INTR_COMMON_PKT_SENT_BIT 1
#define USBDEV_INTR_COMMON_DISCONNECTED_BIT 2
#define USBDEV_INTR_COMMON_HOST_LOST_BIT 3
#define USBDEV_INTR_COMMON_LINK_RESET_BIT 4
#define USBDEV_INTR_COMMON_LINK_SUSPEND_BIT 5
#define USBDEV_INTR_COMMON_LINK_RESUME_BIT 6
#define USBDEV_INTR_COMMON_AV_OUT_EMPTY_BIT 7
#define USBDEV_INTR_COMMON_RX_FULL_BIT 8
#define USBDEV_INTR_COMMON_AV_OVERFLOW_BIT 9
#define USBDEV_INTR_COMMON_LINK_IN_ERR_BIT 10
#define USBDEV_INTR_COMMON_RX_CRC_ERR_BIT 11
#define USBDEV_INTR_COMMON_RX_PID_ERR_BIT 12
#define USBDEV_INTR_COMMON_RX_BITSTUFF_ERR_BIT 13
#define USBDEV_INTR_COMMON_FRAME_BIT 14
#define USBDEV_INTR_COMMON_POWERED_BIT 15
#define USBDEV_INTR_COMMON_LINK_OUT_ERR_BIT 16
#define USBDEV_INTR_COMMON_AV_SETUP_EMPTY_BIT 17
 
// Interrupt State Register
#define USBDEV_INTR_STATE_REG_OFFSET 0x0
#define USBDEV_INTR_STATE_REG_RESVAL 0x0u
#define USBDEV_INTR_STATE_PKT_RECEIVED_BIT 0
#define USBDEV_INTR_STATE_PKT_SENT_BIT 1
#define USBDEV_INTR_STATE_DISCONNECTED_BIT 2
#define USBDEV_INTR_STATE_HOST_LOST_BIT 3
#define USBDEV_INTR_STATE_LINK_RESET_BIT 4
#define USBDEV_INTR_STATE_LINK_SUSPEND_BIT 5
#define USBDEV_INTR_STATE_LINK_RESUME_BIT 6
#define USBDEV_INTR_STATE_AV_OUT_EMPTY_BIT 7
#define USBDEV_INTR_STATE_RX_FULL_BIT 8
#define USBDEV_INTR_STATE_AV_OVERFLOW_BIT 9
#define USBDEV_INTR_STATE_LINK_IN_ERR_BIT 10
#define USBDEV_INTR_STATE_RX_CRC_ERR_BIT 11
#define USBDEV_INTR_STATE_RX_PID_ERR_BIT 12
#define USBDEV_INTR_STATE_RX_BITSTUFF_ERR_BIT 13
#define USBDEV_INTR_STATE_FRAME_BIT 14
#define USBDEV_INTR_STATE_POWERED_BIT 15
#define USBDEV_INTR_STATE_LINK_OUT_ERR_BIT 16
#define USBDEV_INTR_STATE_AV_SETUP_EMPTY_BIT 17
 
// Interrupt Enable Register
#define USBDEV_INTR_ENABLE_REG_OFFSET 0x4
#define USBDEV_INTR_ENABLE_REG_RESVAL 0x0u
#define USBDEV_INTR_ENABLE_PKT_RECEIVED_BIT 0
#define USBDEV_INTR_ENABLE_PKT_SENT_BIT 1
#define USBDEV_INTR_ENABLE_DISCONNECTED_BIT 2
#define USBDEV_INTR_ENABLE_HOST_LOST_BIT 3
#define USBDEV_INTR_ENABLE_LINK_RESET_BIT 4
#define USBDEV_INTR_ENABLE_LINK_SUSPEND_BIT 5
#define USBDEV_INTR_ENABLE_LINK_RESUME_BIT 6
#define USBDEV_INTR_ENABLE_AV_OUT_EMPTY_BIT 7
#define USBDEV_INTR_ENABLE_RX_FULL_BIT 8
#define USBDEV_INTR_ENABLE_AV_OVERFLOW_BIT 9
#define USBDEV_INTR_ENABLE_LINK_IN_ERR_BIT 10
#define USBDEV_INTR_ENABLE_RX_CRC_ERR_BIT 11
#define USBDEV_INTR_ENABLE_RX_PID_ERR_BIT 12
#define USBDEV_INTR_ENABLE_RX_BITSTUFF_ERR_BIT 13
#define USBDEV_INTR_ENABLE_FRAME_BIT 14
#define USBDEV_INTR_ENABLE_POWERED_BIT 15
#define USBDEV_INTR_ENABLE_LINK_OUT_ERR_BIT 16
#define USBDEV_INTR_ENABLE_AV_SETUP_EMPTY_BIT 17
 
// Interrupt Test Register
#define USBDEV_INTR_TEST_REG_OFFSET 0x8
#define USBDEV_INTR_TEST_REG_RESVAL 0x0u
#define USBDEV_INTR_TEST_PKT_RECEIVED_BIT 0
#define USBDEV_INTR_TEST_PKT_SENT_BIT 1
#define USBDEV_INTR_TEST_DISCONNECTED_BIT 2
#define USBDEV_INTR_TEST_HOST_LOST_BIT 3
#define USBDEV_INTR_TEST_LINK_RESET_BIT 4
#define USBDEV_INTR_TEST_LINK_SUSPEND_BIT 5
#define USBDEV_INTR_TEST_LINK_RESUME_BIT 6
#define USBDEV_INTR_TEST_AV_OUT_EMPTY_BIT 7
#define USBDEV_INTR_TEST_RX_FULL_BIT 8
#define USBDEV_INTR_TEST_AV_OVERFLOW_BIT 9
#define USBDEV_INTR_TEST_LINK_IN_ERR_BIT 10
#define USBDEV_INTR_TEST_RX_CRC_ERR_BIT 11
#define USBDEV_INTR_TEST_RX_PID_ERR_BIT 12
#define USBDEV_INTR_TEST_RX_BITSTUFF_ERR_BIT 13
#define USBDEV_INTR_TEST_FRAME_BIT 14
#define USBDEV_INTR_TEST_POWERED_BIT 15
#define USBDEV_INTR_TEST_LINK_OUT_ERR_BIT 16
#define USBDEV_INTR_TEST_AV_SETUP_EMPTY_BIT 17
 
// Alert Test Register
#define USBDEV_ALERT_TEST_REG_OFFSET 0xc
#define USBDEV_ALERT_TEST_REG_RESVAL 0x80000000u
#define USBDEV_ALERT_TEST_FATAL_FAULT_BIT 0
#define USBDEV_ALERT_TEST_REGWEN_BIT 31
 
// USB Control
#define USBDEV_USBCTRL_REG_OFFSET 0x10
#define USBDEV_USBCTRL_REG_RESVAL 0x0u
#define USBDEV_USBCTRL_ENABLE_BIT 0
#define USBDEV_USBCTRL_RESUME_LINK_ACTIVE_BIT 1
#define USBDEV_USBCTRL_DEVICE_ADDRESS_MASK 0x7fu
#define USBDEV_USBCTRL_DEVICE_ADDRESS_OFFSET 16
#define USBDEV_USBCTRL_DEVICE_ADDRESS_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_USBCTRL_DEVICE_ADDRESS_MASK, .index = USBDEV_USBCTRL_DEVICE_ADDRESS_OFFSET })
 
// Enable an endpoint to respond to transactions in the downstream direction.
#define USBDEV_EP_OUT_ENABLE_ENABLE_FIELD_WIDTH 1
#define USBDEV_EP_OUT_ENABLE_MULTIREG_COUNT 1
 
// Enable an endpoint to respond to transactions in the downstream direction.
#define USBDEV_EP_OUT_ENABLE_REG_OFFSET 0x14
#define USBDEV_EP_OUT_ENABLE_REG_RESVAL 0x0u
#define USBDEV_EP_OUT_ENABLE_ENABLE_0_BIT 0
#define USBDEV_EP_OUT_ENABLE_ENABLE_1_BIT 1
#define USBDEV_EP_OUT_ENABLE_ENABLE_2_BIT 2
#define USBDEV_EP_OUT_ENABLE_ENABLE_3_BIT 3
#define USBDEV_EP_OUT_ENABLE_ENABLE_4_BIT 4
#define USBDEV_EP_OUT_ENABLE_ENABLE_5_BIT 5
#define USBDEV_EP_OUT_ENABLE_ENABLE_6_BIT 6
#define USBDEV_EP_OUT_ENABLE_ENABLE_7_BIT 7
#define USBDEV_EP_OUT_ENABLE_ENABLE_8_BIT 8
#define USBDEV_EP_OUT_ENABLE_ENABLE_9_BIT 9
#define USBDEV_EP_OUT_ENABLE_ENABLE_10_BIT 10
#define USBDEV_EP_OUT_ENABLE_ENABLE_11_BIT 11
 
// Enable an endpoint to respond to transactions in the upstream direction.
#define USBDEV_EP_IN_ENABLE_ENABLE_FIELD_WIDTH 1
#define USBDEV_EP_IN_ENABLE_MULTIREG_COUNT 1
 
// Enable an endpoint to respond to transactions in the upstream direction.
#define USBDEV_EP_IN_ENABLE_REG_OFFSET 0x18
#define USBDEV_EP_IN_ENABLE_REG_RESVAL 0x0u
#define USBDEV_EP_IN_ENABLE_ENABLE_0_BIT 0
#define USBDEV_EP_IN_ENABLE_ENABLE_1_BIT 1
#define USBDEV_EP_IN_ENABLE_ENABLE_2_BIT 2
#define USBDEV_EP_IN_ENABLE_ENABLE_3_BIT 3
#define USBDEV_EP_IN_ENABLE_ENABLE_4_BIT 4
#define USBDEV_EP_IN_ENABLE_ENABLE_5_BIT 5
#define USBDEV_EP_IN_ENABLE_ENABLE_6_BIT 6
#define USBDEV_EP_IN_ENABLE_ENABLE_7_BIT 7
#define USBDEV_EP_IN_ENABLE_ENABLE_8_BIT 8
#define USBDEV_EP_IN_ENABLE_ENABLE_9_BIT 9
#define USBDEV_EP_IN_ENABLE_ENABLE_10_BIT 10
#define USBDEV_EP_IN_ENABLE_ENABLE_11_BIT 11
 
// USB Status
#define USBDEV_USBSTAT_REG_OFFSET 0x1c
#define USBDEV_USBSTAT_REG_RESVAL 0x80000000u
#define USBDEV_USBSTAT_FRAME_MASK 0x7ffu
#define USBDEV_USBSTAT_FRAME_OFFSET 0
#define USBDEV_USBSTAT_FRAME_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_USBSTAT_FRAME_MASK, .index = USBDEV_USBSTAT_FRAME_OFFSET })
#define USBDEV_USBSTAT_HOST_LOST_BIT 11
#define USBDEV_USBSTAT_LINK_STATE_MASK 0x7u
#define USBDEV_USBSTAT_LINK_STATE_OFFSET 12
#define USBDEV_USBSTAT_LINK_STATE_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_USBSTAT_LINK_STATE_MASK, .index = USBDEV_USBSTAT_LINK_STATE_OFFSET })
#define USBDEV_USBSTAT_LINK_STATE_VALUE_DISCONNECTED 0x0
#define USBDEV_USBSTAT_LINK_STATE_VALUE_POWERED 0x1
#define USBDEV_USBSTAT_LINK_STATE_VALUE_POWERED_SUSPENDED 0x2
#define USBDEV_USBSTAT_LINK_STATE_VALUE_ACTIVE 0x3
#define USBDEV_USBSTAT_LINK_STATE_VALUE_SUSPENDED 0x4
#define USBDEV_USBSTAT_LINK_STATE_VALUE_ACTIVE_NOSOF 0x5
#define USBDEV_USBSTAT_LINK_STATE_VALUE_RESUMING 0x6
#define USBDEV_USBSTAT_SENSE_BIT 15
#define USBDEV_USBSTAT_AV_OUT_DEPTH_MASK 0xfu
#define USBDEV_USBSTAT_AV_OUT_DEPTH_OFFSET 16
#define USBDEV_USBSTAT_AV_OUT_DEPTH_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_USBSTAT_AV_OUT_DEPTH_MASK, .index = USBDEV_USBSTAT_AV_OUT_DEPTH_OFFSET })
#define USBDEV_USBSTAT_AV_SETUP_DEPTH_MASK 0x7u
#define USBDEV_USBSTAT_AV_SETUP_DEPTH_OFFSET 20
#define USBDEV_USBSTAT_AV_SETUP_DEPTH_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_USBSTAT_AV_SETUP_DEPTH_MASK, .index = USBDEV_USBSTAT_AV_SETUP_DEPTH_OFFSET })
#define USBDEV_USBSTAT_AV_OUT_FULL_BIT 23
#define USBDEV_USBSTAT_RX_DEPTH_MASK 0xfu
#define USBDEV_USBSTAT_RX_DEPTH_OFFSET 24
#define USBDEV_USBSTAT_RX_DEPTH_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_USBSTAT_RX_DEPTH_MASK, .index = USBDEV_USBSTAT_RX_DEPTH_OFFSET })
#define USBDEV_USBSTAT_AV_SETUP_FULL_BIT 30
#define USBDEV_USBSTAT_RX_EMPTY_BIT 31
 
// Available OUT Buffer FIFO
#define USBDEV_AVOUTBUFFER_REG_OFFSET 0x20
#define USBDEV_AVOUTBUFFER_REG_RESVAL 0x0u
#define USBDEV_AVOUTBUFFER_BUFFER_MASK 0x1fu
#define USBDEV_AVOUTBUFFER_BUFFER_OFFSET 0
#define USBDEV_AVOUTBUFFER_BUFFER_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_AVOUTBUFFER_BUFFER_MASK, .index = USBDEV_AVOUTBUFFER_BUFFER_OFFSET })
 
// Available SETUP Buffer FIFO
#define USBDEV_AVSETUPBUFFER_REG_OFFSET 0x24
#define USBDEV_AVSETUPBUFFER_REG_RESVAL 0x0u
#define USBDEV_AVSETUPBUFFER_BUFFER_MASK 0x1fu
#define USBDEV_AVSETUPBUFFER_BUFFER_OFFSET 0
#define USBDEV_AVSETUPBUFFER_BUFFER_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_AVSETUPBUFFER_BUFFER_MASK, .index = USBDEV_AVSETUPBUFFER_BUFFER_OFFSET })
 
// Received Buffer FIFO
#define USBDEV_RXFIFO_REG_OFFSET 0x28
#define USBDEV_RXFIFO_REG_RESVAL 0x0u
#define USBDEV_RXFIFO_BUFFER_MASK 0x1fu
#define USBDEV_RXFIFO_BUFFER_OFFSET 0
#define USBDEV_RXFIFO_BUFFER_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_RXFIFO_BUFFER_MASK, .index = USBDEV_RXFIFO_BUFFER_OFFSET })
#define USBDEV_RXFIFO_SIZE_MASK 0x7fu
#define USBDEV_RXFIFO_SIZE_OFFSET 8
#define USBDEV_RXFIFO_SIZE_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_RXFIFO_SIZE_MASK, .index = USBDEV_RXFIFO_SIZE_OFFSET })
#define USBDEV_RXFIFO_SETUP_BIT 19
#define USBDEV_RXFIFO_EP_MASK 0xfu
#define USBDEV_RXFIFO_EP_OFFSET 20
#define USBDEV_RXFIFO_EP_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_RXFIFO_EP_MASK, .index = USBDEV_RXFIFO_EP_OFFSET })
 
// Receive SETUP transaction enable (common parameters)
#define USBDEV_RXENABLE_SETUP_SETUP_FIELD_WIDTH 1
#define USBDEV_RXENABLE_SETUP_MULTIREG_COUNT 1
 
// Receive SETUP transaction enable
#define USBDEV_RXENABLE_SETUP_REG_OFFSET 0x2c
#define USBDEV_RXENABLE_SETUP_REG_RESVAL 0x0u
#define USBDEV_RXENABLE_SETUP_SETUP_0_BIT 0
#define USBDEV_RXENABLE_SETUP_SETUP_1_BIT 1
#define USBDEV_RXENABLE_SETUP_SETUP_2_BIT 2
#define USBDEV_RXENABLE_SETUP_SETUP_3_BIT 3
#define USBDEV_RXENABLE_SETUP_SETUP_4_BIT 4
#define USBDEV_RXENABLE_SETUP_SETUP_5_BIT 5
#define USBDEV_RXENABLE_SETUP_SETUP_6_BIT 6
#define USBDEV_RXENABLE_SETUP_SETUP_7_BIT 7
#define USBDEV_RXENABLE_SETUP_SETUP_8_BIT 8
#define USBDEV_RXENABLE_SETUP_SETUP_9_BIT 9
#define USBDEV_RXENABLE_SETUP_SETUP_10_BIT 10
#define USBDEV_RXENABLE_SETUP_SETUP_11_BIT 11
 
// Receive OUT transaction enable
#define USBDEV_RXENABLE_OUT_REG_OFFSET 0x30
#define USBDEV_RXENABLE_OUT_REG_RESVAL 0x0u
#define USBDEV_RXENABLE_OUT_OUT_MASK 0xfffu
#define USBDEV_RXENABLE_OUT_OUT_OFFSET 0
#define USBDEV_RXENABLE_OUT_OUT_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_RXENABLE_OUT_OUT_MASK, .index = USBDEV_RXENABLE_OUT_OUT_OFFSET })
#define USBDEV_RXENABLE_OUT_PRESERVE_MASK 0xfffu
#define USBDEV_RXENABLE_OUT_PRESERVE_OFFSET 16
#define USBDEV_RXENABLE_OUT_PRESERVE_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_RXENABLE_OUT_PRESERVE_MASK, .index = USBDEV_RXENABLE_OUT_PRESERVE_OFFSET })
 
// Set NAK after OUT transactions (common parameters)
#define USBDEV_SET_NAK_OUT_ENABLE_FIELD_WIDTH 1
#define USBDEV_SET_NAK_OUT_MULTIREG_COUNT 1
 
// Set NAK after OUT transactions
#define USBDEV_SET_NAK_OUT_REG_OFFSET 0x34
#define USBDEV_SET_NAK_OUT_REG_RESVAL 0x0u
#define USBDEV_SET_NAK_OUT_ENABLE_0_BIT 0
#define USBDEV_SET_NAK_OUT_ENABLE_1_BIT 1
#define USBDEV_SET_NAK_OUT_ENABLE_2_BIT 2
#define USBDEV_SET_NAK_OUT_ENABLE_3_BIT 3
#define USBDEV_SET_NAK_OUT_ENABLE_4_BIT 4
#define USBDEV_SET_NAK_OUT_ENABLE_5_BIT 5
#define USBDEV_SET_NAK_OUT_ENABLE_6_BIT 6
#define USBDEV_SET_NAK_OUT_ENABLE_7_BIT 7
#define USBDEV_SET_NAK_OUT_ENABLE_8_BIT 8
#define USBDEV_SET_NAK_OUT_ENABLE_9_BIT 9
#define USBDEV_SET_NAK_OUT_ENABLE_10_BIT 10
#define USBDEV_SET_NAK_OUT_ENABLE_11_BIT 11
 
// IN Transaction Sent (common parameters)
#define USBDEV_IN_SENT_SENT_FIELD_WIDTH 1
#define USBDEV_IN_SENT_MULTIREG_COUNT 1
 
// IN Transaction Sent
#define USBDEV_IN_SENT_REG_OFFSET 0x38
#define USBDEV_IN_SENT_REG_RESVAL 0x0u
#define USBDEV_IN_SENT_SENT_0_BIT 0
#define USBDEV_IN_SENT_SENT_1_BIT 1
#define USBDEV_IN_SENT_SENT_2_BIT 2
#define USBDEV_IN_SENT_SENT_3_BIT 3
#define USBDEV_IN_SENT_SENT_4_BIT 4
#define USBDEV_IN_SENT_SENT_5_BIT 5
#define USBDEV_IN_SENT_SENT_6_BIT 6
#define USBDEV_IN_SENT_SENT_7_BIT 7
#define USBDEV_IN_SENT_SENT_8_BIT 8
#define USBDEV_IN_SENT_SENT_9_BIT 9
#define USBDEV_IN_SENT_SENT_10_BIT 10
#define USBDEV_IN_SENT_SENT_11_BIT 11
 
// OUT Endpoint STALL control (common parameters)
#define USBDEV_OUT_STALL_ENDPOINT_FIELD_WIDTH 1
#define USBDEV_OUT_STALL_MULTIREG_COUNT 1
 
// OUT Endpoint STALL control
#define USBDEV_OUT_STALL_REG_OFFSET 0x3c
#define USBDEV_OUT_STALL_REG_RESVAL 0x0u
#define USBDEV_OUT_STALL_ENDPOINT_0_BIT 0
#define USBDEV_OUT_STALL_ENDPOINT_1_BIT 1
#define USBDEV_OUT_STALL_ENDPOINT_2_BIT 2
#define USBDEV_OUT_STALL_ENDPOINT_3_BIT 3
#define USBDEV_OUT_STALL_ENDPOINT_4_BIT 4
#define USBDEV_OUT_STALL_ENDPOINT_5_BIT 5
#define USBDEV_OUT_STALL_ENDPOINT_6_BIT 6
#define USBDEV_OUT_STALL_ENDPOINT_7_BIT 7
#define USBDEV_OUT_STALL_ENDPOINT_8_BIT 8
#define USBDEV_OUT_STALL_ENDPOINT_9_BIT 9
#define USBDEV_OUT_STALL_ENDPOINT_10_BIT 10
#define USBDEV_OUT_STALL_ENDPOINT_11_BIT 11
 
// IN Endpoint STALL control (common parameters)
#define USBDEV_IN_STALL_ENDPOINT_FIELD_WIDTH 1
#define USBDEV_IN_STALL_MULTIREG_COUNT 1
 
// IN Endpoint STALL control
#define USBDEV_IN_STALL_REG_OFFSET 0x40
#define USBDEV_IN_STALL_REG_RESVAL 0x0u
#define USBDEV_IN_STALL_ENDPOINT_0_BIT 0
#define USBDEV_IN_STALL_ENDPOINT_1_BIT 1
#define USBDEV_IN_STALL_ENDPOINT_2_BIT 2
#define USBDEV_IN_STALL_ENDPOINT_3_BIT 3
#define USBDEV_IN_STALL_ENDPOINT_4_BIT 4
#define USBDEV_IN_STALL_ENDPOINT_5_BIT 5
#define USBDEV_IN_STALL_ENDPOINT_6_BIT 6
#define USBDEV_IN_STALL_ENDPOINT_7_BIT 7
#define USBDEV_IN_STALL_ENDPOINT_8_BIT 8
#define USBDEV_IN_STALL_ENDPOINT_9_BIT 9
#define USBDEV_IN_STALL_ENDPOINT_10_BIT 10
#define USBDEV_IN_STALL_ENDPOINT_11_BIT 11
 
// Configure IN Transaction (common parameters)
#define USBDEV_CONFIGIN_BUFFER_FIELD_WIDTH 5
#define USBDEV_CONFIGIN_SIZE_FIELD_WIDTH 7
#define USBDEV_CONFIGIN_SENDING_FIELD_WIDTH 1
#define USBDEV_CONFIGIN_PEND_FIELD_WIDTH 1
#define USBDEV_CONFIGIN_RDY_FIELD_WIDTH 1
#define USBDEV_CONFIGIN_MULTIREG_COUNT 12
 
// Configure IN Transaction
#define USBDEV_CONFIGIN_0_REG_OFFSET 0x44
#define USBDEV_CONFIGIN_0_REG_RESVAL 0x0u
#define USBDEV_CONFIGIN_0_BUFFER_0_MASK 0x1fu
#define USBDEV_CONFIGIN_0_BUFFER_0_OFFSET 0
#define USBDEV_CONFIGIN_0_BUFFER_0_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_0_BUFFER_0_MASK, .index = USBDEV_CONFIGIN_0_BUFFER_0_OFFSET })
#define USBDEV_CONFIGIN_0_SIZE_0_MASK 0x7fu
#define USBDEV_CONFIGIN_0_SIZE_0_OFFSET 8
#define USBDEV_CONFIGIN_0_SIZE_0_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_0_SIZE_0_MASK, .index = USBDEV_CONFIGIN_0_SIZE_0_OFFSET })
#define USBDEV_CONFIGIN_0_SENDING_0_BIT 29
#define USBDEV_CONFIGIN_0_PEND_0_BIT 30
#define USBDEV_CONFIGIN_0_RDY_0_BIT 31
 
// Configure IN Transaction
#define USBDEV_CONFIGIN_1_REG_OFFSET 0x48
#define USBDEV_CONFIGIN_1_REG_RESVAL 0x0u
#define USBDEV_CONFIGIN_1_BUFFER_1_MASK 0x1fu
#define USBDEV_CONFIGIN_1_BUFFER_1_OFFSET 0
#define USBDEV_CONFIGIN_1_BUFFER_1_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_1_BUFFER_1_MASK, .index = USBDEV_CONFIGIN_1_BUFFER_1_OFFSET })
#define USBDEV_CONFIGIN_1_SIZE_1_MASK 0x7fu
#define USBDEV_CONFIGIN_1_SIZE_1_OFFSET 8
#define USBDEV_CONFIGIN_1_SIZE_1_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_1_SIZE_1_MASK, .index = USBDEV_CONFIGIN_1_SIZE_1_OFFSET })
#define USBDEV_CONFIGIN_1_SENDING_1_BIT 29
#define USBDEV_CONFIGIN_1_PEND_1_BIT 30
#define USBDEV_CONFIGIN_1_RDY_1_BIT 31
 
// Configure IN Transaction
#define USBDEV_CONFIGIN_2_REG_OFFSET 0x4c
#define USBDEV_CONFIGIN_2_REG_RESVAL 0x0u
#define USBDEV_CONFIGIN_2_BUFFER_2_MASK 0x1fu
#define USBDEV_CONFIGIN_2_BUFFER_2_OFFSET 0
#define USBDEV_CONFIGIN_2_BUFFER_2_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_2_BUFFER_2_MASK, .index = USBDEV_CONFIGIN_2_BUFFER_2_OFFSET })
#define USBDEV_CONFIGIN_2_SIZE_2_MASK 0x7fu
#define USBDEV_CONFIGIN_2_SIZE_2_OFFSET 8
#define USBDEV_CONFIGIN_2_SIZE_2_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_2_SIZE_2_MASK, .index = USBDEV_CONFIGIN_2_SIZE_2_OFFSET })
#define USBDEV_CONFIGIN_2_SENDING_2_BIT 29
#define USBDEV_CONFIGIN_2_PEND_2_BIT 30
#define USBDEV_CONFIGIN_2_RDY_2_BIT 31
 
// Configure IN Transaction
#define USBDEV_CONFIGIN_3_REG_OFFSET 0x50
#define USBDEV_CONFIGIN_3_REG_RESVAL 0x0u
#define USBDEV_CONFIGIN_3_BUFFER_3_MASK 0x1fu
#define USBDEV_CONFIGIN_3_BUFFER_3_OFFSET 0
#define USBDEV_CONFIGIN_3_BUFFER_3_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_3_BUFFER_3_MASK, .index = USBDEV_CONFIGIN_3_BUFFER_3_OFFSET })
#define USBDEV_CONFIGIN_3_SIZE_3_MASK 0x7fu
#define USBDEV_CONFIGIN_3_SIZE_3_OFFSET 8
#define USBDEV_CONFIGIN_3_SIZE_3_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_3_SIZE_3_MASK, .index = USBDEV_CONFIGIN_3_SIZE_3_OFFSET })
#define USBDEV_CONFIGIN_3_SENDING_3_BIT 29
#define USBDEV_CONFIGIN_3_PEND_3_BIT 30
#define USBDEV_CONFIGIN_3_RDY_3_BIT 31
 
// Configure IN Transaction
#define USBDEV_CONFIGIN_4_REG_OFFSET 0x54
#define USBDEV_CONFIGIN_4_REG_RESVAL 0x0u
#define USBDEV_CONFIGIN_4_BUFFER_4_MASK 0x1fu
#define USBDEV_CONFIGIN_4_BUFFER_4_OFFSET 0
#define USBDEV_CONFIGIN_4_BUFFER_4_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_4_BUFFER_4_MASK, .index = USBDEV_CONFIGIN_4_BUFFER_4_OFFSET })
#define USBDEV_CONFIGIN_4_SIZE_4_MASK 0x7fu
#define USBDEV_CONFIGIN_4_SIZE_4_OFFSET 8
#define USBDEV_CONFIGIN_4_SIZE_4_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_4_SIZE_4_MASK, .index = USBDEV_CONFIGIN_4_SIZE_4_OFFSET })
#define USBDEV_CONFIGIN_4_SENDING_4_BIT 29
#define USBDEV_CONFIGIN_4_PEND_4_BIT 30
#define USBDEV_CONFIGIN_4_RDY_4_BIT 31
 
// Configure IN Transaction
#define USBDEV_CONFIGIN_5_REG_OFFSET 0x58
#define USBDEV_CONFIGIN_5_REG_RESVAL 0x0u
#define USBDEV_CONFIGIN_5_BUFFER_5_MASK 0x1fu
#define USBDEV_CONFIGIN_5_BUFFER_5_OFFSET 0
#define USBDEV_CONFIGIN_5_BUFFER_5_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_5_BUFFER_5_MASK, .index = USBDEV_CONFIGIN_5_BUFFER_5_OFFSET })
#define USBDEV_CONFIGIN_5_SIZE_5_MASK 0x7fu
#define USBDEV_CONFIGIN_5_SIZE_5_OFFSET 8
#define USBDEV_CONFIGIN_5_SIZE_5_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_5_SIZE_5_MASK, .index = USBDEV_CONFIGIN_5_SIZE_5_OFFSET })
#define USBDEV_CONFIGIN_5_SENDING_5_BIT 29
#define USBDEV_CONFIGIN_5_PEND_5_BIT 30
#define USBDEV_CONFIGIN_5_RDY_5_BIT 31
 
// Configure IN Transaction
#define USBDEV_CONFIGIN_6_REG_OFFSET 0x5c
#define USBDEV_CONFIGIN_6_REG_RESVAL 0x0u
#define USBDEV_CONFIGIN_6_BUFFER_6_MASK 0x1fu
#define USBDEV_CONFIGIN_6_BUFFER_6_OFFSET 0
#define USBDEV_CONFIGIN_6_BUFFER_6_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_6_BUFFER_6_MASK, .index = USBDEV_CONFIGIN_6_BUFFER_6_OFFSET })
#define USBDEV_CONFIGIN_6_SIZE_6_MASK 0x7fu
#define USBDEV_CONFIGIN_6_SIZE_6_OFFSET 8
#define USBDEV_CONFIGIN_6_SIZE_6_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_6_SIZE_6_MASK, .index = USBDEV_CONFIGIN_6_SIZE_6_OFFSET })
#define USBDEV_CONFIGIN_6_SENDING_6_BIT 29
#define USBDEV_CONFIGIN_6_PEND_6_BIT 30
#define USBDEV_CONFIGIN_6_RDY_6_BIT 31
 
// Configure IN Transaction
#define USBDEV_CONFIGIN_7_REG_OFFSET 0x60
#define USBDEV_CONFIGIN_7_REG_RESVAL 0x0u
#define USBDEV_CONFIGIN_7_BUFFER_7_MASK 0x1fu
#define USBDEV_CONFIGIN_7_BUFFER_7_OFFSET 0
#define USBDEV_CONFIGIN_7_BUFFER_7_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_7_BUFFER_7_MASK, .index = USBDEV_CONFIGIN_7_BUFFER_7_OFFSET })
#define USBDEV_CONFIGIN_7_SIZE_7_MASK 0x7fu
#define USBDEV_CONFIGIN_7_SIZE_7_OFFSET 8
#define USBDEV_CONFIGIN_7_SIZE_7_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_7_SIZE_7_MASK, .index = USBDEV_CONFIGIN_7_SIZE_7_OFFSET })
#define USBDEV_CONFIGIN_7_SENDING_7_BIT 29
#define USBDEV_CONFIGIN_7_PEND_7_BIT 30
#define USBDEV_CONFIGIN_7_RDY_7_BIT 31
 
// Configure IN Transaction
#define USBDEV_CONFIGIN_8_REG_OFFSET 0x64
#define USBDEV_CONFIGIN_8_REG_RESVAL 0x0u
#define USBDEV_CONFIGIN_8_BUFFER_8_MASK 0x1fu
#define USBDEV_CONFIGIN_8_BUFFER_8_OFFSET 0
#define USBDEV_CONFIGIN_8_BUFFER_8_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_8_BUFFER_8_MASK, .index = USBDEV_CONFIGIN_8_BUFFER_8_OFFSET })
#define USBDEV_CONFIGIN_8_SIZE_8_MASK 0x7fu
#define USBDEV_CONFIGIN_8_SIZE_8_OFFSET 8
#define USBDEV_CONFIGIN_8_SIZE_8_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_8_SIZE_8_MASK, .index = USBDEV_CONFIGIN_8_SIZE_8_OFFSET })
#define USBDEV_CONFIGIN_8_SENDING_8_BIT 29
#define USBDEV_CONFIGIN_8_PEND_8_BIT 30
#define USBDEV_CONFIGIN_8_RDY_8_BIT 31
 
// Configure IN Transaction
#define USBDEV_CONFIGIN_9_REG_OFFSET 0x68
#define USBDEV_CONFIGIN_9_REG_RESVAL 0x0u
#define USBDEV_CONFIGIN_9_BUFFER_9_MASK 0x1fu
#define USBDEV_CONFIGIN_9_BUFFER_9_OFFSET 0
#define USBDEV_CONFIGIN_9_BUFFER_9_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_9_BUFFER_9_MASK, .index = USBDEV_CONFIGIN_9_BUFFER_9_OFFSET })
#define USBDEV_CONFIGIN_9_SIZE_9_MASK 0x7fu
#define USBDEV_CONFIGIN_9_SIZE_9_OFFSET 8
#define USBDEV_CONFIGIN_9_SIZE_9_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_9_SIZE_9_MASK, .index = USBDEV_CONFIGIN_9_SIZE_9_OFFSET })
#define USBDEV_CONFIGIN_9_SENDING_9_BIT 29
#define USBDEV_CONFIGIN_9_PEND_9_BIT 30
#define USBDEV_CONFIGIN_9_RDY_9_BIT 31
 
// Configure IN Transaction
#define USBDEV_CONFIGIN_10_REG_OFFSET 0x6c
#define USBDEV_CONFIGIN_10_REG_RESVAL 0x0u
#define USBDEV_CONFIGIN_10_BUFFER_10_MASK 0x1fu
#define USBDEV_CONFIGIN_10_BUFFER_10_OFFSET 0
#define USBDEV_CONFIGIN_10_BUFFER_10_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_10_BUFFER_10_MASK, .index = USBDEV_CONFIGIN_10_BUFFER_10_OFFSET })
#define USBDEV_CONFIGIN_10_SIZE_10_MASK 0x7fu
#define USBDEV_CONFIGIN_10_SIZE_10_OFFSET 8
#define USBDEV_CONFIGIN_10_SIZE_10_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_10_SIZE_10_MASK, .index = USBDEV_CONFIGIN_10_SIZE_10_OFFSET })
#define USBDEV_CONFIGIN_10_SENDING_10_BIT 29
#define USBDEV_CONFIGIN_10_PEND_10_BIT 30
#define USBDEV_CONFIGIN_10_RDY_10_BIT 31
 
// Configure IN Transaction
#define USBDEV_CONFIGIN_11_REG_OFFSET 0x70
#define USBDEV_CONFIGIN_11_REG_RESVAL 0x0u
#define USBDEV_CONFIGIN_11_BUFFER_11_MASK 0x1fu
#define USBDEV_CONFIGIN_11_BUFFER_11_OFFSET 0
#define USBDEV_CONFIGIN_11_BUFFER_11_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_11_BUFFER_11_MASK, .index = USBDEV_CONFIGIN_11_BUFFER_11_OFFSET })
#define USBDEV_CONFIGIN_11_SIZE_11_MASK 0x7fu
#define USBDEV_CONFIGIN_11_SIZE_11_OFFSET 8
#define USBDEV_CONFIGIN_11_SIZE_11_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_11_SIZE_11_MASK, .index = USBDEV_CONFIGIN_11_SIZE_11_OFFSET })
#define USBDEV_CONFIGIN_11_SENDING_11_BIT 29
#define USBDEV_CONFIGIN_11_PEND_11_BIT 30
#define USBDEV_CONFIGIN_11_RDY_11_BIT 31
 
// OUT Endpoint isochronous setting (common parameters)
#define USBDEV_OUT_ISO_ISO_FIELD_WIDTH 1
#define USBDEV_OUT_ISO_MULTIREG_COUNT 1
 
// OUT Endpoint isochronous setting
#define USBDEV_OUT_ISO_REG_OFFSET 0x74
#define USBDEV_OUT_ISO_REG_RESVAL 0x0u
#define USBDEV_OUT_ISO_ISO_0_BIT 0
#define USBDEV_OUT_ISO_ISO_1_BIT 1
#define USBDEV_OUT_ISO_ISO_2_BIT 2
#define USBDEV_OUT_ISO_ISO_3_BIT 3
#define USBDEV_OUT_ISO_ISO_4_BIT 4
#define USBDEV_OUT_ISO_ISO_5_BIT 5
#define USBDEV_OUT_ISO_ISO_6_BIT 6
#define USBDEV_OUT_ISO_ISO_7_BIT 7
#define USBDEV_OUT_ISO_ISO_8_BIT 8
#define USBDEV_OUT_ISO_ISO_9_BIT 9
#define USBDEV_OUT_ISO_ISO_10_BIT 10
#define USBDEV_OUT_ISO_ISO_11_BIT 11
 
// IN Endpoint isochronous setting (common parameters)
#define USBDEV_IN_ISO_ISO_FIELD_WIDTH 1
#define USBDEV_IN_ISO_MULTIREG_COUNT 1
 
// IN Endpoint isochronous setting
#define USBDEV_IN_ISO_REG_OFFSET 0x78
#define USBDEV_IN_ISO_REG_RESVAL 0x0u
#define USBDEV_IN_ISO_ISO_0_BIT 0
#define USBDEV_IN_ISO_ISO_1_BIT 1
#define USBDEV_IN_ISO_ISO_2_BIT 2
#define USBDEV_IN_ISO_ISO_3_BIT 3
#define USBDEV_IN_ISO_ISO_4_BIT 4
#define USBDEV_IN_ISO_ISO_5_BIT 5
#define USBDEV_IN_ISO_ISO_6_BIT 6
#define USBDEV_IN_ISO_ISO_7_BIT 7
#define USBDEV_IN_ISO_ISO_8_BIT 8
#define USBDEV_IN_ISO_ISO_9_BIT 9
#define USBDEV_IN_ISO_ISO_10_BIT 10
#define USBDEV_IN_ISO_ISO_11_BIT 11
 
// OUT Endpoints Data Toggles
#define USBDEV_OUT_DATA_TOGGLE_REG_OFFSET 0x7c
#define USBDEV_OUT_DATA_TOGGLE_REG_RESVAL 0x0u
#define USBDEV_OUT_DATA_TOGGLE_STATUS_MASK 0xfffu
#define USBDEV_OUT_DATA_TOGGLE_STATUS_OFFSET 0
#define USBDEV_OUT_DATA_TOGGLE_STATUS_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_OUT_DATA_TOGGLE_STATUS_MASK, .index = USBDEV_OUT_DATA_TOGGLE_STATUS_OFFSET })
#define USBDEV_OUT_DATA_TOGGLE_MASK_MASK 0xfffu
#define USBDEV_OUT_DATA_TOGGLE_MASK_OFFSET 16
#define USBDEV_OUT_DATA_TOGGLE_MASK_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_OUT_DATA_TOGGLE_MASK_MASK, .index = USBDEV_OUT_DATA_TOGGLE_MASK_OFFSET })
 
// IN Endpoints Data Toggles
#define USBDEV_IN_DATA_TOGGLE_REG_OFFSET 0x80
#define USBDEV_IN_DATA_TOGGLE_REG_RESVAL 0x0u
#define USBDEV_IN_DATA_TOGGLE_STATUS_MASK 0xfffu
#define USBDEV_IN_DATA_TOGGLE_STATUS_OFFSET 0
#define USBDEV_IN_DATA_TOGGLE_STATUS_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_IN_DATA_TOGGLE_STATUS_MASK, .index = USBDEV_IN_DATA_TOGGLE_STATUS_OFFSET })
#define USBDEV_IN_DATA_TOGGLE_MASK_MASK 0xfffu
#define USBDEV_IN_DATA_TOGGLE_MASK_OFFSET 16
#define USBDEV_IN_DATA_TOGGLE_MASK_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_IN_DATA_TOGGLE_MASK_MASK, .index = USBDEV_IN_DATA_TOGGLE_MASK_OFFSET })
 
// USB PHY pins sense.
#define USBDEV_PHY_PINS_SENSE_REG_OFFSET 0x84
#define USBDEV_PHY_PINS_SENSE_REG_RESVAL 0x0u
#define USBDEV_PHY_PINS_SENSE_RX_DP_I_BIT 0
#define USBDEV_PHY_PINS_SENSE_RX_DN_I_BIT 1
#define USBDEV_PHY_PINS_SENSE_RX_D_I_BIT 2
#define USBDEV_PHY_PINS_SENSE_TX_DP_O_BIT 8
#define USBDEV_PHY_PINS_SENSE_TX_DN_O_BIT 9
#define USBDEV_PHY_PINS_SENSE_TX_D_O_BIT 10
#define USBDEV_PHY_PINS_SENSE_TX_SE0_O_BIT 11
#define USBDEV_PHY_PINS_SENSE_TX_OE_O_BIT 12
#define USBDEV_PHY_PINS_SENSE_PWR_SENSE_BIT 16
 
// USB PHY pins drive.
#define USBDEV_PHY_PINS_DRIVE_REG_OFFSET 0x88
#define USBDEV_PHY_PINS_DRIVE_REG_RESVAL 0x0u
#define USBDEV_PHY_PINS_DRIVE_DP_O_BIT 0
#define USBDEV_PHY_PINS_DRIVE_DN_O_BIT 1
#define USBDEV_PHY_PINS_DRIVE_D_O_BIT 2
#define USBDEV_PHY_PINS_DRIVE_SE0_O_BIT 3
#define USBDEV_PHY_PINS_DRIVE_OE_O_BIT 4
#define USBDEV_PHY_PINS_DRIVE_RX_ENABLE_O_BIT 5
#define USBDEV_PHY_PINS_DRIVE_DP_PULLUP_EN_O_BIT 6
#define USBDEV_PHY_PINS_DRIVE_DN_PULLUP_EN_O_BIT 7
#define USBDEV_PHY_PINS_DRIVE_EN_BIT 16
 
// USB PHY Configuration
#define USBDEV_PHY_CONFIG_REG_OFFSET 0x8c
#define USBDEV_PHY_CONFIG_REG_RESVAL 0x4u
#define USBDEV_PHY_CONFIG_USE_DIFF_RCVR_BIT 0
#define USBDEV_PHY_CONFIG_TX_USE_D_SE0_BIT 1
#define USBDEV_PHY_CONFIG_EOP_SINGLE_BIT_BIT 2
#define USBDEV_PHY_CONFIG_PINFLIP_BIT 5
#define USBDEV_PHY_CONFIG_USB_REF_DISABLE_BIT 6
#define USBDEV_PHY_CONFIG_TX_OSC_TEST_MODE_BIT 7
 
// USB wake module control for suspend / resume
#define USBDEV_WAKE_CONTROL_REG_OFFSET 0x90
#define USBDEV_WAKE_CONTROL_REG_RESVAL 0x0u
#define USBDEV_WAKE_CONTROL_SUSPEND_REQ_BIT 0
#define USBDEV_WAKE_CONTROL_WAKE_ACK_BIT 1
 
// USB wake module events and debug
#define USBDEV_WAKE_EVENTS_REG_OFFSET 0x94
#define USBDEV_WAKE_EVENTS_REG_RESVAL 0x0u
#define USBDEV_WAKE_EVENTS_MODULE_ACTIVE_BIT 0
#define USBDEV_WAKE_EVENTS_DISCONNECTED_BIT 8
#define USBDEV_WAKE_EVENTS_BUS_RESET_BIT 9
#define USBDEV_WAKE_EVENTS_BUS_NOT_IDLE_BIT 10
 
// FIFO control register
#define USBDEV_FIFO_CTRL_REG_OFFSET 0x98
#define USBDEV_FIFO_CTRL_REG_RESVAL 0x0u
#define USBDEV_FIFO_CTRL_AVOUT_RST_BIT 0
#define USBDEV_FIFO_CTRL_AVSETUP_RST_BIT 1
#define USBDEV_FIFO_CTRL_RX_RST_BIT 2
 
// Counter for OUT side USB events.
#define USBDEV_COUNT_OUT_REG_OFFSET 0x9c
#define USBDEV_COUNT_OUT_REG_RESVAL 0x0u
#define USBDEV_COUNT_OUT_COUNT_MASK 0xffu
#define USBDEV_COUNT_OUT_COUNT_OFFSET 0
#define USBDEV_COUNT_OUT_COUNT_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_COUNT_OUT_COUNT_MASK, .index = USBDEV_COUNT_OUT_COUNT_OFFSET })
#define USBDEV_COUNT_OUT_DATATOG_OUT_BIT 12
#define USBDEV_COUNT_OUT_DROP_RX_BIT 13
#define USBDEV_COUNT_OUT_DROP_AVOUT_BIT 14
#define USBDEV_COUNT_OUT_IGN_AVSETUP_BIT 15
#define USBDEV_COUNT_OUT_ENDPOINTS_MASK 0xfffu
#define USBDEV_COUNT_OUT_ENDPOINTS_OFFSET 16
#define USBDEV_COUNT_OUT_ENDPOINTS_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_COUNT_OUT_ENDPOINTS_MASK, .index = USBDEV_COUNT_OUT_ENDPOINTS_OFFSET })
#define USBDEV_COUNT_OUT_RST_BIT 31
 
// Counter for IN side USB events.
#define USBDEV_COUNT_IN_REG_OFFSET 0xa0
#define USBDEV_COUNT_IN_REG_RESVAL 0x0u
#define USBDEV_COUNT_IN_COUNT_MASK 0xffu
#define USBDEV_COUNT_IN_COUNT_OFFSET 0
#define USBDEV_COUNT_IN_COUNT_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_COUNT_IN_COUNT_MASK, .index = USBDEV_COUNT_IN_COUNT_OFFSET })
#define USBDEV_COUNT_IN_NODATA_BIT 13
#define USBDEV_COUNT_IN_NAK_BIT 14
#define USBDEV_COUNT_IN_TIMEOUT_BIT 15
#define USBDEV_COUNT_IN_ENDPOINTS_MASK 0xfffu
#define USBDEV_COUNT_IN_ENDPOINTS_OFFSET 16
#define USBDEV_COUNT_IN_ENDPOINTS_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_COUNT_IN_ENDPOINTS_MASK, .index = USBDEV_COUNT_IN_ENDPOINTS_OFFSET })
#define USBDEV_COUNT_IN_RST_BIT 31
 
// Count of IN transactions for which no packet data was available.
#define USBDEV_COUNT_NODATA_IN_REG_OFFSET 0xa4
#define USBDEV_COUNT_NODATA_IN_REG_RESVAL 0x0u
#define USBDEV_COUNT_NODATA_IN_COUNT_MASK 0xffu
#define USBDEV_COUNT_NODATA_IN_COUNT_OFFSET 0
#define USBDEV_COUNT_NODATA_IN_COUNT_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_COUNT_NODATA_IN_COUNT_MASK, .index = USBDEV_COUNT_NODATA_IN_COUNT_OFFSET })
#define USBDEV_COUNT_NODATA_IN_ENDPOINTS_MASK 0xfffu
#define USBDEV_COUNT_NODATA_IN_ENDPOINTS_OFFSET 16
#define USBDEV_COUNT_NODATA_IN_ENDPOINTS_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_COUNT_NODATA_IN_ENDPOINTS_MASK, .index = USBDEV_COUNT_NODATA_IN_ENDPOINTS_OFFSET })
#define USBDEV_COUNT_NODATA_IN_RST_BIT 31
 
// Count of error conditions detected on token packets from the host.
#define USBDEV_COUNT_ERRORS_REG_OFFSET 0xa8
#define USBDEV_COUNT_ERRORS_REG_RESVAL 0x0u
#define USBDEV_COUNT_ERRORS_COUNT_MASK 0xffu
#define USBDEV_COUNT_ERRORS_COUNT_OFFSET 0
#define USBDEV_COUNT_ERRORS_COUNT_FIELD \
  ((bitfield_field32_t) { .mask = USBDEV_COUNT_ERRORS_COUNT_MASK, .index = USBDEV_COUNT_ERRORS_COUNT_OFFSET })
#define USBDEV_COUNT_ERRORS_PID_INVALID_BIT 27
#define USBDEV_COUNT_ERRORS_BITSTUFF_BIT 28
#define USBDEV_COUNT_ERRORS_CRC16_BIT 29
#define USBDEV_COUNT_ERRORS_CRC5_BIT 30
#define USBDEV_COUNT_ERRORS_RST_BIT 31
 
// Memory area: 2 KiB packet buffer. Divided into thirty two 64-byte buffers.
#define USBDEV_BUFFER_REG_OFFSET 0x800
#define USBDEV_BUFFER_SIZE_WORDS 512
#define USBDEV_BUFFER_SIZE_BYTES 2048
#ifdef __cplusplus
}  // extern "C"
#endif
#endif  // _USBDEV_REG_DEFS_
// End generated register defines for usbdev