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13#ifndef _USBDEV_REG_DEFS_
14#define _USBDEV_REG_DEFS_
20#define USBDEV_PARAM_N_ENDPOINTS 12
23#define USBDEV_PARAM_NUM_ALERTS 1
26#define USBDEV_PARAM_REG_WIDTH 32
29#define USBDEV_INTR_COMMON_PKT_RECEIVED_BIT 0
30#define USBDEV_INTR_COMMON_PKT_SENT_BIT 1
31#define USBDEV_INTR_COMMON_DISCONNECTED_BIT 2
32#define USBDEV_INTR_COMMON_HOST_LOST_BIT 3
33#define USBDEV_INTR_COMMON_LINK_RESET_BIT 4
34#define USBDEV_INTR_COMMON_LINK_SUSPEND_BIT 5
35#define USBDEV_INTR_COMMON_LINK_RESUME_BIT 6
36#define USBDEV_INTR_COMMON_AV_OUT_EMPTY_BIT 7
37#define USBDEV_INTR_COMMON_RX_FULL_BIT 8
38#define USBDEV_INTR_COMMON_AV_OVERFLOW_BIT 9
39#define USBDEV_INTR_COMMON_LINK_IN_ERR_BIT 10
40#define USBDEV_INTR_COMMON_RX_CRC_ERR_BIT 11
41#define USBDEV_INTR_COMMON_RX_PID_ERR_BIT 12
42#define USBDEV_INTR_COMMON_RX_BITSTUFF_ERR_BIT 13
43#define USBDEV_INTR_COMMON_FRAME_BIT 14
44#define USBDEV_INTR_COMMON_POWERED_BIT 15
45#define USBDEV_INTR_COMMON_LINK_OUT_ERR_BIT 16
46#define USBDEV_INTR_COMMON_AV_SETUP_EMPTY_BIT 17
49#define USBDEV_INTR_STATE_REG_OFFSET 0x0
50#define USBDEV_INTR_STATE_REG_RESVAL 0x0u
51#define USBDEV_INTR_STATE_PKT_RECEIVED_BIT 0
52#define USBDEV_INTR_STATE_PKT_SENT_BIT 1
53#define USBDEV_INTR_STATE_DISCONNECTED_BIT 2
54#define USBDEV_INTR_STATE_HOST_LOST_BIT 3
55#define USBDEV_INTR_STATE_LINK_RESET_BIT 4
56#define USBDEV_INTR_STATE_LINK_SUSPEND_BIT 5
57#define USBDEV_INTR_STATE_LINK_RESUME_BIT 6
58#define USBDEV_INTR_STATE_AV_OUT_EMPTY_BIT 7
59#define USBDEV_INTR_STATE_RX_FULL_BIT 8
60#define USBDEV_INTR_STATE_AV_OVERFLOW_BIT 9
61#define USBDEV_INTR_STATE_LINK_IN_ERR_BIT 10
62#define USBDEV_INTR_STATE_RX_CRC_ERR_BIT 11
63#define USBDEV_INTR_STATE_RX_PID_ERR_BIT 12
64#define USBDEV_INTR_STATE_RX_BITSTUFF_ERR_BIT 13
65#define USBDEV_INTR_STATE_FRAME_BIT 14
66#define USBDEV_INTR_STATE_POWERED_BIT 15
67#define USBDEV_INTR_STATE_LINK_OUT_ERR_BIT 16
68#define USBDEV_INTR_STATE_AV_SETUP_EMPTY_BIT 17
71#define USBDEV_INTR_ENABLE_REG_OFFSET 0x4
72#define USBDEV_INTR_ENABLE_REG_RESVAL 0x0u
73#define USBDEV_INTR_ENABLE_PKT_RECEIVED_BIT 0
74#define USBDEV_INTR_ENABLE_PKT_SENT_BIT 1
75#define USBDEV_INTR_ENABLE_DISCONNECTED_BIT 2
76#define USBDEV_INTR_ENABLE_HOST_LOST_BIT 3
77#define USBDEV_INTR_ENABLE_LINK_RESET_BIT 4
78#define USBDEV_INTR_ENABLE_LINK_SUSPEND_BIT 5
79#define USBDEV_INTR_ENABLE_LINK_RESUME_BIT 6
80#define USBDEV_INTR_ENABLE_AV_OUT_EMPTY_BIT 7
81#define USBDEV_INTR_ENABLE_RX_FULL_BIT 8
82#define USBDEV_INTR_ENABLE_AV_OVERFLOW_BIT 9
83#define USBDEV_INTR_ENABLE_LINK_IN_ERR_BIT 10
84#define USBDEV_INTR_ENABLE_RX_CRC_ERR_BIT 11
85#define USBDEV_INTR_ENABLE_RX_PID_ERR_BIT 12
86#define USBDEV_INTR_ENABLE_RX_BITSTUFF_ERR_BIT 13
87#define USBDEV_INTR_ENABLE_FRAME_BIT 14
88#define USBDEV_INTR_ENABLE_POWERED_BIT 15
89#define USBDEV_INTR_ENABLE_LINK_OUT_ERR_BIT 16
90#define USBDEV_INTR_ENABLE_AV_SETUP_EMPTY_BIT 17
93#define USBDEV_INTR_TEST_REG_OFFSET 0x8
94#define USBDEV_INTR_TEST_REG_RESVAL 0x0u
95#define USBDEV_INTR_TEST_PKT_RECEIVED_BIT 0
96#define USBDEV_INTR_TEST_PKT_SENT_BIT 1
97#define USBDEV_INTR_TEST_DISCONNECTED_BIT 2
98#define USBDEV_INTR_TEST_HOST_LOST_BIT 3
99#define USBDEV_INTR_TEST_LINK_RESET_BIT 4
100#define USBDEV_INTR_TEST_LINK_SUSPEND_BIT 5
101#define USBDEV_INTR_TEST_LINK_RESUME_BIT 6
102#define USBDEV_INTR_TEST_AV_OUT_EMPTY_BIT 7
103#define USBDEV_INTR_TEST_RX_FULL_BIT 8
104#define USBDEV_INTR_TEST_AV_OVERFLOW_BIT 9
105#define USBDEV_INTR_TEST_LINK_IN_ERR_BIT 10
106#define USBDEV_INTR_TEST_RX_CRC_ERR_BIT 11
107#define USBDEV_INTR_TEST_RX_PID_ERR_BIT 12
108#define USBDEV_INTR_TEST_RX_BITSTUFF_ERR_BIT 13
109#define USBDEV_INTR_TEST_FRAME_BIT 14
110#define USBDEV_INTR_TEST_POWERED_BIT 15
111#define USBDEV_INTR_TEST_LINK_OUT_ERR_BIT 16
112#define USBDEV_INTR_TEST_AV_SETUP_EMPTY_BIT 17
115#define USBDEV_ALERT_TEST_REG_OFFSET 0xc
116#define USBDEV_ALERT_TEST_REG_RESVAL 0x0u
117#define USBDEV_ALERT_TEST_FATAL_FAULT_BIT 0
120#define USBDEV_USBCTRL_REG_OFFSET 0x10
121#define USBDEV_USBCTRL_REG_RESVAL 0x0u
122#define USBDEV_USBCTRL_ENABLE_BIT 0
123#define USBDEV_USBCTRL_RESUME_LINK_ACTIVE_BIT 1
124#define USBDEV_USBCTRL_DEVICE_ADDRESS_MASK 0x7fu
125#define USBDEV_USBCTRL_DEVICE_ADDRESS_OFFSET 16
126#define USBDEV_USBCTRL_DEVICE_ADDRESS_FIELD \
127 ((bitfield_field32_t) { .mask = USBDEV_USBCTRL_DEVICE_ADDRESS_MASK, .index = USBDEV_USBCTRL_DEVICE_ADDRESS_OFFSET })
130#define USBDEV_EP_OUT_ENABLE_ENABLE_FIELD_WIDTH 1
131#define USBDEV_EP_OUT_ENABLE_MULTIREG_COUNT 1
134#define USBDEV_EP_OUT_ENABLE_REG_OFFSET 0x14
135#define USBDEV_EP_OUT_ENABLE_REG_RESVAL 0x0u
136#define USBDEV_EP_OUT_ENABLE_ENABLE_0_BIT 0
137#define USBDEV_EP_OUT_ENABLE_ENABLE_1_BIT 1
138#define USBDEV_EP_OUT_ENABLE_ENABLE_2_BIT 2
139#define USBDEV_EP_OUT_ENABLE_ENABLE_3_BIT 3
140#define USBDEV_EP_OUT_ENABLE_ENABLE_4_BIT 4
141#define USBDEV_EP_OUT_ENABLE_ENABLE_5_BIT 5
142#define USBDEV_EP_OUT_ENABLE_ENABLE_6_BIT 6
143#define USBDEV_EP_OUT_ENABLE_ENABLE_7_BIT 7
144#define USBDEV_EP_OUT_ENABLE_ENABLE_8_BIT 8
145#define USBDEV_EP_OUT_ENABLE_ENABLE_9_BIT 9
146#define USBDEV_EP_OUT_ENABLE_ENABLE_10_BIT 10
147#define USBDEV_EP_OUT_ENABLE_ENABLE_11_BIT 11
150#define USBDEV_EP_IN_ENABLE_ENABLE_FIELD_WIDTH 1
151#define USBDEV_EP_IN_ENABLE_MULTIREG_COUNT 1
154#define USBDEV_EP_IN_ENABLE_REG_OFFSET 0x18
155#define USBDEV_EP_IN_ENABLE_REG_RESVAL 0x0u
156#define USBDEV_EP_IN_ENABLE_ENABLE_0_BIT 0
157#define USBDEV_EP_IN_ENABLE_ENABLE_1_BIT 1
158#define USBDEV_EP_IN_ENABLE_ENABLE_2_BIT 2
159#define USBDEV_EP_IN_ENABLE_ENABLE_3_BIT 3
160#define USBDEV_EP_IN_ENABLE_ENABLE_4_BIT 4
161#define USBDEV_EP_IN_ENABLE_ENABLE_5_BIT 5
162#define USBDEV_EP_IN_ENABLE_ENABLE_6_BIT 6
163#define USBDEV_EP_IN_ENABLE_ENABLE_7_BIT 7
164#define USBDEV_EP_IN_ENABLE_ENABLE_8_BIT 8
165#define USBDEV_EP_IN_ENABLE_ENABLE_9_BIT 9
166#define USBDEV_EP_IN_ENABLE_ENABLE_10_BIT 10
167#define USBDEV_EP_IN_ENABLE_ENABLE_11_BIT 11
170#define USBDEV_USBSTAT_REG_OFFSET 0x1c
171#define USBDEV_USBSTAT_REG_RESVAL 0x80000000u
172#define USBDEV_USBSTAT_FRAME_MASK 0x7ffu
173#define USBDEV_USBSTAT_FRAME_OFFSET 0
174#define USBDEV_USBSTAT_FRAME_FIELD \
175 ((bitfield_field32_t) { .mask = USBDEV_USBSTAT_FRAME_MASK, .index = USBDEV_USBSTAT_FRAME_OFFSET })
176#define USBDEV_USBSTAT_HOST_LOST_BIT 11
177#define USBDEV_USBSTAT_LINK_STATE_MASK 0x7u
178#define USBDEV_USBSTAT_LINK_STATE_OFFSET 12
179#define USBDEV_USBSTAT_LINK_STATE_FIELD \
180 ((bitfield_field32_t) { .mask = USBDEV_USBSTAT_LINK_STATE_MASK, .index = USBDEV_USBSTAT_LINK_STATE_OFFSET })
181#define USBDEV_USBSTAT_LINK_STATE_VALUE_DISCONNECTED 0x0
182#define USBDEV_USBSTAT_LINK_STATE_VALUE_POWERED 0x1
183#define USBDEV_USBSTAT_LINK_STATE_VALUE_POWERED_SUSPENDED 0x2
184#define USBDEV_USBSTAT_LINK_STATE_VALUE_ACTIVE 0x3
185#define USBDEV_USBSTAT_LINK_STATE_VALUE_SUSPENDED 0x4
186#define USBDEV_USBSTAT_LINK_STATE_VALUE_ACTIVE_NOSOF 0x5
187#define USBDEV_USBSTAT_LINK_STATE_VALUE_RESUMING 0x6
188#define USBDEV_USBSTAT_SENSE_BIT 15
189#define USBDEV_USBSTAT_AV_OUT_DEPTH_MASK 0xfu
190#define USBDEV_USBSTAT_AV_OUT_DEPTH_OFFSET 16
191#define USBDEV_USBSTAT_AV_OUT_DEPTH_FIELD \
192 ((bitfield_field32_t) { .mask = USBDEV_USBSTAT_AV_OUT_DEPTH_MASK, .index = USBDEV_USBSTAT_AV_OUT_DEPTH_OFFSET })
193#define USBDEV_USBSTAT_AV_SETUP_DEPTH_MASK 0x7u
194#define USBDEV_USBSTAT_AV_SETUP_DEPTH_OFFSET 20
195#define USBDEV_USBSTAT_AV_SETUP_DEPTH_FIELD \
196 ((bitfield_field32_t) { .mask = USBDEV_USBSTAT_AV_SETUP_DEPTH_MASK, .index = USBDEV_USBSTAT_AV_SETUP_DEPTH_OFFSET })
197#define USBDEV_USBSTAT_AV_OUT_FULL_BIT 23
198#define USBDEV_USBSTAT_RX_DEPTH_MASK 0xfu
199#define USBDEV_USBSTAT_RX_DEPTH_OFFSET 24
200#define USBDEV_USBSTAT_RX_DEPTH_FIELD \
201 ((bitfield_field32_t) { .mask = USBDEV_USBSTAT_RX_DEPTH_MASK, .index = USBDEV_USBSTAT_RX_DEPTH_OFFSET })
202#define USBDEV_USBSTAT_AV_SETUP_FULL_BIT 30
203#define USBDEV_USBSTAT_RX_EMPTY_BIT 31
206#define USBDEV_AVOUTBUFFER_REG_OFFSET 0x20
207#define USBDEV_AVOUTBUFFER_REG_RESVAL 0x0u
208#define USBDEV_AVOUTBUFFER_BUFFER_MASK 0x1fu
209#define USBDEV_AVOUTBUFFER_BUFFER_OFFSET 0
210#define USBDEV_AVOUTBUFFER_BUFFER_FIELD \
211 ((bitfield_field32_t) { .mask = USBDEV_AVOUTBUFFER_BUFFER_MASK, .index = USBDEV_AVOUTBUFFER_BUFFER_OFFSET })
214#define USBDEV_AVSETUPBUFFER_REG_OFFSET 0x24
215#define USBDEV_AVSETUPBUFFER_REG_RESVAL 0x0u
216#define USBDEV_AVSETUPBUFFER_BUFFER_MASK 0x1fu
217#define USBDEV_AVSETUPBUFFER_BUFFER_OFFSET 0
218#define USBDEV_AVSETUPBUFFER_BUFFER_FIELD \
219 ((bitfield_field32_t) { .mask = USBDEV_AVSETUPBUFFER_BUFFER_MASK, .index = USBDEV_AVSETUPBUFFER_BUFFER_OFFSET })
222#define USBDEV_RXFIFO_REG_OFFSET 0x28
223#define USBDEV_RXFIFO_REG_RESVAL 0x0u
224#define USBDEV_RXFIFO_BUFFER_MASK 0x1fu
225#define USBDEV_RXFIFO_BUFFER_OFFSET 0
226#define USBDEV_RXFIFO_BUFFER_FIELD \
227 ((bitfield_field32_t) { .mask = USBDEV_RXFIFO_BUFFER_MASK, .index = USBDEV_RXFIFO_BUFFER_OFFSET })
228#define USBDEV_RXFIFO_SIZE_MASK 0x7fu
229#define USBDEV_RXFIFO_SIZE_OFFSET 8
230#define USBDEV_RXFIFO_SIZE_FIELD \
231 ((bitfield_field32_t) { .mask = USBDEV_RXFIFO_SIZE_MASK, .index = USBDEV_RXFIFO_SIZE_OFFSET })
232#define USBDEV_RXFIFO_SETUP_BIT 19
233#define USBDEV_RXFIFO_EP_MASK 0xfu
234#define USBDEV_RXFIFO_EP_OFFSET 20
235#define USBDEV_RXFIFO_EP_FIELD \
236 ((bitfield_field32_t) { .mask = USBDEV_RXFIFO_EP_MASK, .index = USBDEV_RXFIFO_EP_OFFSET })
239#define USBDEV_RXENABLE_SETUP_SETUP_FIELD_WIDTH 1
240#define USBDEV_RXENABLE_SETUP_MULTIREG_COUNT 1
243#define USBDEV_RXENABLE_SETUP_REG_OFFSET 0x2c
244#define USBDEV_RXENABLE_SETUP_REG_RESVAL 0x0u
245#define USBDEV_RXENABLE_SETUP_SETUP_0_BIT 0
246#define USBDEV_RXENABLE_SETUP_SETUP_1_BIT 1
247#define USBDEV_RXENABLE_SETUP_SETUP_2_BIT 2
248#define USBDEV_RXENABLE_SETUP_SETUP_3_BIT 3
249#define USBDEV_RXENABLE_SETUP_SETUP_4_BIT 4
250#define USBDEV_RXENABLE_SETUP_SETUP_5_BIT 5
251#define USBDEV_RXENABLE_SETUP_SETUP_6_BIT 6
252#define USBDEV_RXENABLE_SETUP_SETUP_7_BIT 7
253#define USBDEV_RXENABLE_SETUP_SETUP_8_BIT 8
254#define USBDEV_RXENABLE_SETUP_SETUP_9_BIT 9
255#define USBDEV_RXENABLE_SETUP_SETUP_10_BIT 10
256#define USBDEV_RXENABLE_SETUP_SETUP_11_BIT 11
259#define USBDEV_RXENABLE_OUT_REG_OFFSET 0x30
260#define USBDEV_RXENABLE_OUT_REG_RESVAL 0x0u
261#define USBDEV_RXENABLE_OUT_OUT_MASK 0xfffu
262#define USBDEV_RXENABLE_OUT_OUT_OFFSET 0
263#define USBDEV_RXENABLE_OUT_OUT_FIELD \
264 ((bitfield_field32_t) { .mask = USBDEV_RXENABLE_OUT_OUT_MASK, .index = USBDEV_RXENABLE_OUT_OUT_OFFSET })
265#define USBDEV_RXENABLE_OUT_PRESERVE_MASK 0xfffu
266#define USBDEV_RXENABLE_OUT_PRESERVE_OFFSET 16
267#define USBDEV_RXENABLE_OUT_PRESERVE_FIELD \
268 ((bitfield_field32_t) { .mask = USBDEV_RXENABLE_OUT_PRESERVE_MASK, .index = USBDEV_RXENABLE_OUT_PRESERVE_OFFSET })
271#define USBDEV_SET_NAK_OUT_ENABLE_FIELD_WIDTH 1
272#define USBDEV_SET_NAK_OUT_MULTIREG_COUNT 1
275#define USBDEV_SET_NAK_OUT_REG_OFFSET 0x34
276#define USBDEV_SET_NAK_OUT_REG_RESVAL 0x0u
277#define USBDEV_SET_NAK_OUT_ENABLE_0_BIT 0
278#define USBDEV_SET_NAK_OUT_ENABLE_1_BIT 1
279#define USBDEV_SET_NAK_OUT_ENABLE_2_BIT 2
280#define USBDEV_SET_NAK_OUT_ENABLE_3_BIT 3
281#define USBDEV_SET_NAK_OUT_ENABLE_4_BIT 4
282#define USBDEV_SET_NAK_OUT_ENABLE_5_BIT 5
283#define USBDEV_SET_NAK_OUT_ENABLE_6_BIT 6
284#define USBDEV_SET_NAK_OUT_ENABLE_7_BIT 7
285#define USBDEV_SET_NAK_OUT_ENABLE_8_BIT 8
286#define USBDEV_SET_NAK_OUT_ENABLE_9_BIT 9
287#define USBDEV_SET_NAK_OUT_ENABLE_10_BIT 10
288#define USBDEV_SET_NAK_OUT_ENABLE_11_BIT 11
291#define USBDEV_IN_SENT_SENT_FIELD_WIDTH 1
292#define USBDEV_IN_SENT_MULTIREG_COUNT 1
295#define USBDEV_IN_SENT_REG_OFFSET 0x38
296#define USBDEV_IN_SENT_REG_RESVAL 0x0u
297#define USBDEV_IN_SENT_SENT_0_BIT 0
298#define USBDEV_IN_SENT_SENT_1_BIT 1
299#define USBDEV_IN_SENT_SENT_2_BIT 2
300#define USBDEV_IN_SENT_SENT_3_BIT 3
301#define USBDEV_IN_SENT_SENT_4_BIT 4
302#define USBDEV_IN_SENT_SENT_5_BIT 5
303#define USBDEV_IN_SENT_SENT_6_BIT 6
304#define USBDEV_IN_SENT_SENT_7_BIT 7
305#define USBDEV_IN_SENT_SENT_8_BIT 8
306#define USBDEV_IN_SENT_SENT_9_BIT 9
307#define USBDEV_IN_SENT_SENT_10_BIT 10
308#define USBDEV_IN_SENT_SENT_11_BIT 11
311#define USBDEV_OUT_STALL_ENDPOINT_FIELD_WIDTH 1
312#define USBDEV_OUT_STALL_MULTIREG_COUNT 1
315#define USBDEV_OUT_STALL_REG_OFFSET 0x3c
316#define USBDEV_OUT_STALL_REG_RESVAL 0x0u
317#define USBDEV_OUT_STALL_ENDPOINT_0_BIT 0
318#define USBDEV_OUT_STALL_ENDPOINT_1_BIT 1
319#define USBDEV_OUT_STALL_ENDPOINT_2_BIT 2
320#define USBDEV_OUT_STALL_ENDPOINT_3_BIT 3
321#define USBDEV_OUT_STALL_ENDPOINT_4_BIT 4
322#define USBDEV_OUT_STALL_ENDPOINT_5_BIT 5
323#define USBDEV_OUT_STALL_ENDPOINT_6_BIT 6
324#define USBDEV_OUT_STALL_ENDPOINT_7_BIT 7
325#define USBDEV_OUT_STALL_ENDPOINT_8_BIT 8
326#define USBDEV_OUT_STALL_ENDPOINT_9_BIT 9
327#define USBDEV_OUT_STALL_ENDPOINT_10_BIT 10
328#define USBDEV_OUT_STALL_ENDPOINT_11_BIT 11
331#define USBDEV_IN_STALL_ENDPOINT_FIELD_WIDTH 1
332#define USBDEV_IN_STALL_MULTIREG_COUNT 1
335#define USBDEV_IN_STALL_REG_OFFSET 0x40
336#define USBDEV_IN_STALL_REG_RESVAL 0x0u
337#define USBDEV_IN_STALL_ENDPOINT_0_BIT 0
338#define USBDEV_IN_STALL_ENDPOINT_1_BIT 1
339#define USBDEV_IN_STALL_ENDPOINT_2_BIT 2
340#define USBDEV_IN_STALL_ENDPOINT_3_BIT 3
341#define USBDEV_IN_STALL_ENDPOINT_4_BIT 4
342#define USBDEV_IN_STALL_ENDPOINT_5_BIT 5
343#define USBDEV_IN_STALL_ENDPOINT_6_BIT 6
344#define USBDEV_IN_STALL_ENDPOINT_7_BIT 7
345#define USBDEV_IN_STALL_ENDPOINT_8_BIT 8
346#define USBDEV_IN_STALL_ENDPOINT_9_BIT 9
347#define USBDEV_IN_STALL_ENDPOINT_10_BIT 10
348#define USBDEV_IN_STALL_ENDPOINT_11_BIT 11
351#define USBDEV_CONFIGIN_BUFFER_FIELD_WIDTH 5
352#define USBDEV_CONFIGIN_SIZE_FIELD_WIDTH 7
353#define USBDEV_CONFIGIN_SENDING_FIELD_WIDTH 1
354#define USBDEV_CONFIGIN_PEND_FIELD_WIDTH 1
355#define USBDEV_CONFIGIN_RDY_FIELD_WIDTH 1
356#define USBDEV_CONFIGIN_MULTIREG_COUNT 12
359#define USBDEV_CONFIGIN_0_REG_OFFSET 0x44
360#define USBDEV_CONFIGIN_0_REG_RESVAL 0x0u
361#define USBDEV_CONFIGIN_0_BUFFER_0_MASK 0x1fu
362#define USBDEV_CONFIGIN_0_BUFFER_0_OFFSET 0
363#define USBDEV_CONFIGIN_0_BUFFER_0_FIELD \
364 ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_0_BUFFER_0_MASK, .index = USBDEV_CONFIGIN_0_BUFFER_0_OFFSET })
365#define USBDEV_CONFIGIN_0_SIZE_0_MASK 0x7fu
366#define USBDEV_CONFIGIN_0_SIZE_0_OFFSET 8
367#define USBDEV_CONFIGIN_0_SIZE_0_FIELD \
368 ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_0_SIZE_0_MASK, .index = USBDEV_CONFIGIN_0_SIZE_0_OFFSET })
369#define USBDEV_CONFIGIN_0_SENDING_0_BIT 29
370#define USBDEV_CONFIGIN_0_PEND_0_BIT 30
371#define USBDEV_CONFIGIN_0_RDY_0_BIT 31
374#define USBDEV_CONFIGIN_1_REG_OFFSET 0x48
375#define USBDEV_CONFIGIN_1_REG_RESVAL 0x0u
376#define USBDEV_CONFIGIN_1_BUFFER_1_MASK 0x1fu
377#define USBDEV_CONFIGIN_1_BUFFER_1_OFFSET 0
378#define USBDEV_CONFIGIN_1_BUFFER_1_FIELD \
379 ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_1_BUFFER_1_MASK, .index = USBDEV_CONFIGIN_1_BUFFER_1_OFFSET })
380#define USBDEV_CONFIGIN_1_SIZE_1_MASK 0x7fu
381#define USBDEV_CONFIGIN_1_SIZE_1_OFFSET 8
382#define USBDEV_CONFIGIN_1_SIZE_1_FIELD \
383 ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_1_SIZE_1_MASK, .index = USBDEV_CONFIGIN_1_SIZE_1_OFFSET })
384#define USBDEV_CONFIGIN_1_SENDING_1_BIT 29
385#define USBDEV_CONFIGIN_1_PEND_1_BIT 30
386#define USBDEV_CONFIGIN_1_RDY_1_BIT 31
389#define USBDEV_CONFIGIN_2_REG_OFFSET 0x4c
390#define USBDEV_CONFIGIN_2_REG_RESVAL 0x0u
391#define USBDEV_CONFIGIN_2_BUFFER_2_MASK 0x1fu
392#define USBDEV_CONFIGIN_2_BUFFER_2_OFFSET 0
393#define USBDEV_CONFIGIN_2_BUFFER_2_FIELD \
394 ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_2_BUFFER_2_MASK, .index = USBDEV_CONFIGIN_2_BUFFER_2_OFFSET })
395#define USBDEV_CONFIGIN_2_SIZE_2_MASK 0x7fu
396#define USBDEV_CONFIGIN_2_SIZE_2_OFFSET 8
397#define USBDEV_CONFIGIN_2_SIZE_2_FIELD \
398 ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_2_SIZE_2_MASK, .index = USBDEV_CONFIGIN_2_SIZE_2_OFFSET })
399#define USBDEV_CONFIGIN_2_SENDING_2_BIT 29
400#define USBDEV_CONFIGIN_2_PEND_2_BIT 30
401#define USBDEV_CONFIGIN_2_RDY_2_BIT 31
404#define USBDEV_CONFIGIN_3_REG_OFFSET 0x50
405#define USBDEV_CONFIGIN_3_REG_RESVAL 0x0u
406#define USBDEV_CONFIGIN_3_BUFFER_3_MASK 0x1fu
407#define USBDEV_CONFIGIN_3_BUFFER_3_OFFSET 0
408#define USBDEV_CONFIGIN_3_BUFFER_3_FIELD \
409 ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_3_BUFFER_3_MASK, .index = USBDEV_CONFIGIN_3_BUFFER_3_OFFSET })
410#define USBDEV_CONFIGIN_3_SIZE_3_MASK 0x7fu
411#define USBDEV_CONFIGIN_3_SIZE_3_OFFSET 8
412#define USBDEV_CONFIGIN_3_SIZE_3_FIELD \
413 ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_3_SIZE_3_MASK, .index = USBDEV_CONFIGIN_3_SIZE_3_OFFSET })
414#define USBDEV_CONFIGIN_3_SENDING_3_BIT 29
415#define USBDEV_CONFIGIN_3_PEND_3_BIT 30
416#define USBDEV_CONFIGIN_3_RDY_3_BIT 31
419#define USBDEV_CONFIGIN_4_REG_OFFSET 0x54
420#define USBDEV_CONFIGIN_4_REG_RESVAL 0x0u
421#define USBDEV_CONFIGIN_4_BUFFER_4_MASK 0x1fu
422#define USBDEV_CONFIGIN_4_BUFFER_4_OFFSET 0
423#define USBDEV_CONFIGIN_4_BUFFER_4_FIELD \
424 ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_4_BUFFER_4_MASK, .index = USBDEV_CONFIGIN_4_BUFFER_4_OFFSET })
425#define USBDEV_CONFIGIN_4_SIZE_4_MASK 0x7fu
426#define USBDEV_CONFIGIN_4_SIZE_4_OFFSET 8
427#define USBDEV_CONFIGIN_4_SIZE_4_FIELD \
428 ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_4_SIZE_4_MASK, .index = USBDEV_CONFIGIN_4_SIZE_4_OFFSET })
429#define USBDEV_CONFIGIN_4_SENDING_4_BIT 29
430#define USBDEV_CONFIGIN_4_PEND_4_BIT 30
431#define USBDEV_CONFIGIN_4_RDY_4_BIT 31
434#define USBDEV_CONFIGIN_5_REG_OFFSET 0x58
435#define USBDEV_CONFIGIN_5_REG_RESVAL 0x0u
436#define USBDEV_CONFIGIN_5_BUFFER_5_MASK 0x1fu
437#define USBDEV_CONFIGIN_5_BUFFER_5_OFFSET 0
438#define USBDEV_CONFIGIN_5_BUFFER_5_FIELD \
439 ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_5_BUFFER_5_MASK, .index = USBDEV_CONFIGIN_5_BUFFER_5_OFFSET })
440#define USBDEV_CONFIGIN_5_SIZE_5_MASK 0x7fu
441#define USBDEV_CONFIGIN_5_SIZE_5_OFFSET 8
442#define USBDEV_CONFIGIN_5_SIZE_5_FIELD \
443 ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_5_SIZE_5_MASK, .index = USBDEV_CONFIGIN_5_SIZE_5_OFFSET })
444#define USBDEV_CONFIGIN_5_SENDING_5_BIT 29
445#define USBDEV_CONFIGIN_5_PEND_5_BIT 30
446#define USBDEV_CONFIGIN_5_RDY_5_BIT 31
449#define USBDEV_CONFIGIN_6_REG_OFFSET 0x5c
450#define USBDEV_CONFIGIN_6_REG_RESVAL 0x0u
451#define USBDEV_CONFIGIN_6_BUFFER_6_MASK 0x1fu
452#define USBDEV_CONFIGIN_6_BUFFER_6_OFFSET 0
453#define USBDEV_CONFIGIN_6_BUFFER_6_FIELD \
454 ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_6_BUFFER_6_MASK, .index = USBDEV_CONFIGIN_6_BUFFER_6_OFFSET })
455#define USBDEV_CONFIGIN_6_SIZE_6_MASK 0x7fu
456#define USBDEV_CONFIGIN_6_SIZE_6_OFFSET 8
457#define USBDEV_CONFIGIN_6_SIZE_6_FIELD \
458 ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_6_SIZE_6_MASK, .index = USBDEV_CONFIGIN_6_SIZE_6_OFFSET })
459#define USBDEV_CONFIGIN_6_SENDING_6_BIT 29
460#define USBDEV_CONFIGIN_6_PEND_6_BIT 30
461#define USBDEV_CONFIGIN_6_RDY_6_BIT 31
464#define USBDEV_CONFIGIN_7_REG_OFFSET 0x60
465#define USBDEV_CONFIGIN_7_REG_RESVAL 0x0u
466#define USBDEV_CONFIGIN_7_BUFFER_7_MASK 0x1fu
467#define USBDEV_CONFIGIN_7_BUFFER_7_OFFSET 0
468#define USBDEV_CONFIGIN_7_BUFFER_7_FIELD \
469 ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_7_BUFFER_7_MASK, .index = USBDEV_CONFIGIN_7_BUFFER_7_OFFSET })
470#define USBDEV_CONFIGIN_7_SIZE_7_MASK 0x7fu
471#define USBDEV_CONFIGIN_7_SIZE_7_OFFSET 8
472#define USBDEV_CONFIGIN_7_SIZE_7_FIELD \
473 ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_7_SIZE_7_MASK, .index = USBDEV_CONFIGIN_7_SIZE_7_OFFSET })
474#define USBDEV_CONFIGIN_7_SENDING_7_BIT 29
475#define USBDEV_CONFIGIN_7_PEND_7_BIT 30
476#define USBDEV_CONFIGIN_7_RDY_7_BIT 31
479#define USBDEV_CONFIGIN_8_REG_OFFSET 0x64
480#define USBDEV_CONFIGIN_8_REG_RESVAL 0x0u
481#define USBDEV_CONFIGIN_8_BUFFER_8_MASK 0x1fu
482#define USBDEV_CONFIGIN_8_BUFFER_8_OFFSET 0
483#define USBDEV_CONFIGIN_8_BUFFER_8_FIELD \
484 ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_8_BUFFER_8_MASK, .index = USBDEV_CONFIGIN_8_BUFFER_8_OFFSET })
485#define USBDEV_CONFIGIN_8_SIZE_8_MASK 0x7fu
486#define USBDEV_CONFIGIN_8_SIZE_8_OFFSET 8
487#define USBDEV_CONFIGIN_8_SIZE_8_FIELD \
488 ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_8_SIZE_8_MASK, .index = USBDEV_CONFIGIN_8_SIZE_8_OFFSET })
489#define USBDEV_CONFIGIN_8_SENDING_8_BIT 29
490#define USBDEV_CONFIGIN_8_PEND_8_BIT 30
491#define USBDEV_CONFIGIN_8_RDY_8_BIT 31
494#define USBDEV_CONFIGIN_9_REG_OFFSET 0x68
495#define USBDEV_CONFIGIN_9_REG_RESVAL 0x0u
496#define USBDEV_CONFIGIN_9_BUFFER_9_MASK 0x1fu
497#define USBDEV_CONFIGIN_9_BUFFER_9_OFFSET 0
498#define USBDEV_CONFIGIN_9_BUFFER_9_FIELD \
499 ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_9_BUFFER_9_MASK, .index = USBDEV_CONFIGIN_9_BUFFER_9_OFFSET })
500#define USBDEV_CONFIGIN_9_SIZE_9_MASK 0x7fu
501#define USBDEV_CONFIGIN_9_SIZE_9_OFFSET 8
502#define USBDEV_CONFIGIN_9_SIZE_9_FIELD \
503 ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_9_SIZE_9_MASK, .index = USBDEV_CONFIGIN_9_SIZE_9_OFFSET })
504#define USBDEV_CONFIGIN_9_SENDING_9_BIT 29
505#define USBDEV_CONFIGIN_9_PEND_9_BIT 30
506#define USBDEV_CONFIGIN_9_RDY_9_BIT 31
509#define USBDEV_CONFIGIN_10_REG_OFFSET 0x6c
510#define USBDEV_CONFIGIN_10_REG_RESVAL 0x0u
511#define USBDEV_CONFIGIN_10_BUFFER_10_MASK 0x1fu
512#define USBDEV_CONFIGIN_10_BUFFER_10_OFFSET 0
513#define USBDEV_CONFIGIN_10_BUFFER_10_FIELD \
514 ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_10_BUFFER_10_MASK, .index = USBDEV_CONFIGIN_10_BUFFER_10_OFFSET })
515#define USBDEV_CONFIGIN_10_SIZE_10_MASK 0x7fu
516#define USBDEV_CONFIGIN_10_SIZE_10_OFFSET 8
517#define USBDEV_CONFIGIN_10_SIZE_10_FIELD \
518 ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_10_SIZE_10_MASK, .index = USBDEV_CONFIGIN_10_SIZE_10_OFFSET })
519#define USBDEV_CONFIGIN_10_SENDING_10_BIT 29
520#define USBDEV_CONFIGIN_10_PEND_10_BIT 30
521#define USBDEV_CONFIGIN_10_RDY_10_BIT 31
524#define USBDEV_CONFIGIN_11_REG_OFFSET 0x70
525#define USBDEV_CONFIGIN_11_REG_RESVAL 0x0u
526#define USBDEV_CONFIGIN_11_BUFFER_11_MASK 0x1fu
527#define USBDEV_CONFIGIN_11_BUFFER_11_OFFSET 0
528#define USBDEV_CONFIGIN_11_BUFFER_11_FIELD \
529 ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_11_BUFFER_11_MASK, .index = USBDEV_CONFIGIN_11_BUFFER_11_OFFSET })
530#define USBDEV_CONFIGIN_11_SIZE_11_MASK 0x7fu
531#define USBDEV_CONFIGIN_11_SIZE_11_OFFSET 8
532#define USBDEV_CONFIGIN_11_SIZE_11_FIELD \
533 ((bitfield_field32_t) { .mask = USBDEV_CONFIGIN_11_SIZE_11_MASK, .index = USBDEV_CONFIGIN_11_SIZE_11_OFFSET })
534#define USBDEV_CONFIGIN_11_SENDING_11_BIT 29
535#define USBDEV_CONFIGIN_11_PEND_11_BIT 30
536#define USBDEV_CONFIGIN_11_RDY_11_BIT 31
539#define USBDEV_OUT_ISO_ISO_FIELD_WIDTH 1
540#define USBDEV_OUT_ISO_MULTIREG_COUNT 1
543#define USBDEV_OUT_ISO_REG_OFFSET 0x74
544#define USBDEV_OUT_ISO_REG_RESVAL 0x0u
545#define USBDEV_OUT_ISO_ISO_0_BIT 0
546#define USBDEV_OUT_ISO_ISO_1_BIT 1
547#define USBDEV_OUT_ISO_ISO_2_BIT 2
548#define USBDEV_OUT_ISO_ISO_3_BIT 3
549#define USBDEV_OUT_ISO_ISO_4_BIT 4
550#define USBDEV_OUT_ISO_ISO_5_BIT 5
551#define USBDEV_OUT_ISO_ISO_6_BIT 6
552#define USBDEV_OUT_ISO_ISO_7_BIT 7
553#define USBDEV_OUT_ISO_ISO_8_BIT 8
554#define USBDEV_OUT_ISO_ISO_9_BIT 9
555#define USBDEV_OUT_ISO_ISO_10_BIT 10
556#define USBDEV_OUT_ISO_ISO_11_BIT 11
559#define USBDEV_IN_ISO_ISO_FIELD_WIDTH 1
560#define USBDEV_IN_ISO_MULTIREG_COUNT 1
563#define USBDEV_IN_ISO_REG_OFFSET 0x78
564#define USBDEV_IN_ISO_REG_RESVAL 0x0u
565#define USBDEV_IN_ISO_ISO_0_BIT 0
566#define USBDEV_IN_ISO_ISO_1_BIT 1
567#define USBDEV_IN_ISO_ISO_2_BIT 2
568#define USBDEV_IN_ISO_ISO_3_BIT 3
569#define USBDEV_IN_ISO_ISO_4_BIT 4
570#define USBDEV_IN_ISO_ISO_5_BIT 5
571#define USBDEV_IN_ISO_ISO_6_BIT 6
572#define USBDEV_IN_ISO_ISO_7_BIT 7
573#define USBDEV_IN_ISO_ISO_8_BIT 8
574#define USBDEV_IN_ISO_ISO_9_BIT 9
575#define USBDEV_IN_ISO_ISO_10_BIT 10
576#define USBDEV_IN_ISO_ISO_11_BIT 11
579#define USBDEV_OUT_DATA_TOGGLE_REG_OFFSET 0x7c
580#define USBDEV_OUT_DATA_TOGGLE_REG_RESVAL 0x0u
581#define USBDEV_OUT_DATA_TOGGLE_STATUS_MASK 0xfffu
582#define USBDEV_OUT_DATA_TOGGLE_STATUS_OFFSET 0
583#define USBDEV_OUT_DATA_TOGGLE_STATUS_FIELD \
584 ((bitfield_field32_t) { .mask = USBDEV_OUT_DATA_TOGGLE_STATUS_MASK, .index = USBDEV_OUT_DATA_TOGGLE_STATUS_OFFSET })
585#define USBDEV_OUT_DATA_TOGGLE_MASK_MASK 0xfffu
586#define USBDEV_OUT_DATA_TOGGLE_MASK_OFFSET 16
587#define USBDEV_OUT_DATA_TOGGLE_MASK_FIELD \
588 ((bitfield_field32_t) { .mask = USBDEV_OUT_DATA_TOGGLE_MASK_MASK, .index = USBDEV_OUT_DATA_TOGGLE_MASK_OFFSET })
591#define USBDEV_IN_DATA_TOGGLE_REG_OFFSET 0x80
592#define USBDEV_IN_DATA_TOGGLE_REG_RESVAL 0x0u
593#define USBDEV_IN_DATA_TOGGLE_STATUS_MASK 0xfffu
594#define USBDEV_IN_DATA_TOGGLE_STATUS_OFFSET 0
595#define USBDEV_IN_DATA_TOGGLE_STATUS_FIELD \
596 ((bitfield_field32_t) { .mask = USBDEV_IN_DATA_TOGGLE_STATUS_MASK, .index = USBDEV_IN_DATA_TOGGLE_STATUS_OFFSET })
597#define USBDEV_IN_DATA_TOGGLE_MASK_MASK 0xfffu
598#define USBDEV_IN_DATA_TOGGLE_MASK_OFFSET 16
599#define USBDEV_IN_DATA_TOGGLE_MASK_FIELD \
600 ((bitfield_field32_t) { .mask = USBDEV_IN_DATA_TOGGLE_MASK_MASK, .index = USBDEV_IN_DATA_TOGGLE_MASK_OFFSET })
603#define USBDEV_PHY_PINS_SENSE_REG_OFFSET 0x84
604#define USBDEV_PHY_PINS_SENSE_REG_RESVAL 0x0u
605#define USBDEV_PHY_PINS_SENSE_RX_DP_I_BIT 0
606#define USBDEV_PHY_PINS_SENSE_RX_DN_I_BIT 1
607#define USBDEV_PHY_PINS_SENSE_RX_D_I_BIT 2
608#define USBDEV_PHY_PINS_SENSE_TX_DP_O_BIT 8
609#define USBDEV_PHY_PINS_SENSE_TX_DN_O_BIT 9
610#define USBDEV_PHY_PINS_SENSE_TX_D_O_BIT 10
611#define USBDEV_PHY_PINS_SENSE_TX_SE0_O_BIT 11
612#define USBDEV_PHY_PINS_SENSE_TX_OE_O_BIT 12
613#define USBDEV_PHY_PINS_SENSE_PWR_SENSE_BIT 16
616#define USBDEV_PHY_PINS_DRIVE_REG_OFFSET 0x88
617#define USBDEV_PHY_PINS_DRIVE_REG_RESVAL 0x0u
618#define USBDEV_PHY_PINS_DRIVE_DP_O_BIT 0
619#define USBDEV_PHY_PINS_DRIVE_DN_O_BIT 1
620#define USBDEV_PHY_PINS_DRIVE_D_O_BIT 2
621#define USBDEV_PHY_PINS_DRIVE_SE0_O_BIT 3
622#define USBDEV_PHY_PINS_DRIVE_OE_O_BIT 4
623#define USBDEV_PHY_PINS_DRIVE_RX_ENABLE_O_BIT 5
624#define USBDEV_PHY_PINS_DRIVE_DP_PULLUP_EN_O_BIT 6
625#define USBDEV_PHY_PINS_DRIVE_DN_PULLUP_EN_O_BIT 7
626#define USBDEV_PHY_PINS_DRIVE_EN_BIT 16
629#define USBDEV_PHY_CONFIG_REG_OFFSET 0x8c
630#define USBDEV_PHY_CONFIG_REG_RESVAL 0x4u
631#define USBDEV_PHY_CONFIG_USE_DIFF_RCVR_BIT 0
632#define USBDEV_PHY_CONFIG_TX_USE_D_SE0_BIT 1
633#define USBDEV_PHY_CONFIG_EOP_SINGLE_BIT_BIT 2
634#define USBDEV_PHY_CONFIG_PINFLIP_BIT 5
635#define USBDEV_PHY_CONFIG_USB_REF_DISABLE_BIT 6
636#define USBDEV_PHY_CONFIG_TX_OSC_TEST_MODE_BIT 7
639#define USBDEV_WAKE_CONTROL_REG_OFFSET 0x90
640#define USBDEV_WAKE_CONTROL_REG_RESVAL 0x0u
641#define USBDEV_WAKE_CONTROL_SUSPEND_REQ_BIT 0
642#define USBDEV_WAKE_CONTROL_WAKE_ACK_BIT 1
645#define USBDEV_WAKE_EVENTS_REG_OFFSET 0x94
646#define USBDEV_WAKE_EVENTS_REG_RESVAL 0x0u
647#define USBDEV_WAKE_EVENTS_MODULE_ACTIVE_BIT 0
648#define USBDEV_WAKE_EVENTS_DISCONNECTED_BIT 8
649#define USBDEV_WAKE_EVENTS_BUS_RESET_BIT 9
650#define USBDEV_WAKE_EVENTS_BUS_NOT_IDLE_BIT 10
653#define USBDEV_FIFO_CTRL_REG_OFFSET 0x98
654#define USBDEV_FIFO_CTRL_REG_RESVAL 0x0u
655#define USBDEV_FIFO_CTRL_AVOUT_RST_BIT 0
656#define USBDEV_FIFO_CTRL_AVSETUP_RST_BIT 1
657#define USBDEV_FIFO_CTRL_RX_RST_BIT 2
660#define USBDEV_COUNT_OUT_REG_OFFSET 0x9c
661#define USBDEV_COUNT_OUT_REG_RESVAL 0x0u
662#define USBDEV_COUNT_OUT_COUNT_MASK 0xffu
663#define USBDEV_COUNT_OUT_COUNT_OFFSET 0
664#define USBDEV_COUNT_OUT_COUNT_FIELD \
665 ((bitfield_field32_t) { .mask = USBDEV_COUNT_OUT_COUNT_MASK, .index = USBDEV_COUNT_OUT_COUNT_OFFSET })
666#define USBDEV_COUNT_OUT_DATATOG_OUT_BIT 12
667#define USBDEV_COUNT_OUT_DROP_RX_BIT 13
668#define USBDEV_COUNT_OUT_DROP_AVOUT_BIT 14
669#define USBDEV_COUNT_OUT_IGN_AVSETUP_BIT 15
670#define USBDEV_COUNT_OUT_ENDPOINTS_MASK 0xfffu
671#define USBDEV_COUNT_OUT_ENDPOINTS_OFFSET 16
672#define USBDEV_COUNT_OUT_ENDPOINTS_FIELD \
673 ((bitfield_field32_t) { .mask = USBDEV_COUNT_OUT_ENDPOINTS_MASK, .index = USBDEV_COUNT_OUT_ENDPOINTS_OFFSET })
674#define USBDEV_COUNT_OUT_RST_BIT 31
677#define USBDEV_COUNT_IN_REG_OFFSET 0xa0
678#define USBDEV_COUNT_IN_REG_RESVAL 0x0u
679#define USBDEV_COUNT_IN_COUNT_MASK 0xffu
680#define USBDEV_COUNT_IN_COUNT_OFFSET 0
681#define USBDEV_COUNT_IN_COUNT_FIELD \
682 ((bitfield_field32_t) { .mask = USBDEV_COUNT_IN_COUNT_MASK, .index = USBDEV_COUNT_IN_COUNT_OFFSET })
683#define USBDEV_COUNT_IN_NODATA_BIT 13
684#define USBDEV_COUNT_IN_NAK_BIT 14
685#define USBDEV_COUNT_IN_TIMEOUT_BIT 15
686#define USBDEV_COUNT_IN_ENDPOINTS_MASK 0xfffu
687#define USBDEV_COUNT_IN_ENDPOINTS_OFFSET 16
688#define USBDEV_COUNT_IN_ENDPOINTS_FIELD \
689 ((bitfield_field32_t) { .mask = USBDEV_COUNT_IN_ENDPOINTS_MASK, .index = USBDEV_COUNT_IN_ENDPOINTS_OFFSET })
690#define USBDEV_COUNT_IN_RST_BIT 31
693#define USBDEV_COUNT_NODATA_IN_REG_OFFSET 0xa4
694#define USBDEV_COUNT_NODATA_IN_REG_RESVAL 0x0u
695#define USBDEV_COUNT_NODATA_IN_COUNT_MASK 0xffu
696#define USBDEV_COUNT_NODATA_IN_COUNT_OFFSET 0
697#define USBDEV_COUNT_NODATA_IN_COUNT_FIELD \
698 ((bitfield_field32_t) { .mask = USBDEV_COUNT_NODATA_IN_COUNT_MASK, .index = USBDEV_COUNT_NODATA_IN_COUNT_OFFSET })
699#define USBDEV_COUNT_NODATA_IN_ENDPOINTS_MASK 0xfffu
700#define USBDEV_COUNT_NODATA_IN_ENDPOINTS_OFFSET 16
701#define USBDEV_COUNT_NODATA_IN_ENDPOINTS_FIELD \
702 ((bitfield_field32_t) { .mask = USBDEV_COUNT_NODATA_IN_ENDPOINTS_MASK, .index = USBDEV_COUNT_NODATA_IN_ENDPOINTS_OFFSET })
703#define USBDEV_COUNT_NODATA_IN_RST_BIT 31
706#define USBDEV_COUNT_ERRORS_REG_OFFSET 0xa8
707#define USBDEV_COUNT_ERRORS_REG_RESVAL 0x0u
708#define USBDEV_COUNT_ERRORS_COUNT_MASK 0xffu
709#define USBDEV_COUNT_ERRORS_COUNT_OFFSET 0
710#define USBDEV_COUNT_ERRORS_COUNT_FIELD \
711 ((bitfield_field32_t) { .mask = USBDEV_COUNT_ERRORS_COUNT_MASK, .index = USBDEV_COUNT_ERRORS_COUNT_OFFSET })
712#define USBDEV_COUNT_ERRORS_PID_INVALID_BIT 27
713#define USBDEV_COUNT_ERRORS_BITSTUFF_BIT 28
714#define USBDEV_COUNT_ERRORS_CRC16_BIT 29
715#define USBDEV_COUNT_ERRORS_CRC5_BIT 30
716#define USBDEV_COUNT_ERRORS_RST_BIT 31
719#define USBDEV_BUFFER_REG_OFFSET 0x800
720#define USBDEV_BUFFER_SIZE_WORDS 512
721#define USBDEV_BUFFER_SIZE_BYTES 2048