kmac_regs.h

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/**
 * @file
 * @brief Generated register defines for kmac
 */
 
// Copyright information found in source file:
// Copyright lowRISC contributors (OpenTitan project).
 
// Licensing information found in source file:
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
 
#ifndef _KMAC_REG_DEFS_
#define _KMAC_REG_DEFS_
 
#ifdef __cplusplus
extern "C" {
#endif
// Number of words for the secret key
#define KMAC_PARAM_NUM_WORDS_KEY 16
 
// Number of words for Encoded NsPrefix.
#define KMAC_PARAM_NUM_WORDS_PREFIX 11
 
// Number of entries in the message FIFO. Must match kmac_pkg::MsgFifoDepth.
#define KMAC_PARAM_NUM_ENTRIES_MSG_FIFO 10
 
// Number of bytes in a single entry of the message FIFO. Must match
// kmac_pkg::MsgWidth.
#define KMAC_PARAM_NUM_BYTES_MSG_FIFO_ENTRY 8
 
// Width of the hash counter in the entropy
#define KMAC_PARAM_HASH_CNT_W 10
 
// Number of words for the PRNG seed used for entropy generation
#define KMAC_PARAM_NUM_SEEDS_ENTROPY 6
 
// Number of alerts
#define KMAC_PARAM_NUM_ALERTS 2
 
// Register width
#define KMAC_PARAM_REG_WIDTH 32
 
// Common Interrupt Offsets
#define KMAC_INTR_COMMON_KMAC_DONE_BIT 0
#define KMAC_INTR_COMMON_FIFO_EMPTY_BIT 1
#define KMAC_INTR_COMMON_KMAC_ERR_BIT 2
 
// Interrupt State Register
#define KMAC_INTR_STATE_REG_OFFSET 0x0
#define KMAC_INTR_STATE_REG_RESVAL 0x0u
#define KMAC_INTR_STATE_KMAC_DONE_BIT 0
#define KMAC_INTR_STATE_FIFO_EMPTY_BIT 1
#define KMAC_INTR_STATE_KMAC_ERR_BIT 2
 
// Interrupt Enable Register
#define KMAC_INTR_ENABLE_REG_OFFSET 0x4
#define KMAC_INTR_ENABLE_REG_RESVAL 0x0u
#define KMAC_INTR_ENABLE_KMAC_DONE_BIT 0
#define KMAC_INTR_ENABLE_FIFO_EMPTY_BIT 1
#define KMAC_INTR_ENABLE_KMAC_ERR_BIT 2
 
// Interrupt Test Register
#define KMAC_INTR_TEST_REG_OFFSET 0x8
#define KMAC_INTR_TEST_REG_RESVAL 0x0u
#define KMAC_INTR_TEST_KMAC_DONE_BIT 0
#define KMAC_INTR_TEST_FIFO_EMPTY_BIT 1
#define KMAC_INTR_TEST_KMAC_ERR_BIT 2
 
// Alert Test Register
#define KMAC_ALERT_TEST_REG_OFFSET 0xc
#define KMAC_ALERT_TEST_REG_RESVAL 0x80000000u
#define KMAC_ALERT_TEST_RECOV_OPERATION_ERR_BIT 0
#define KMAC_ALERT_TEST_FATAL_FAULT_ERR_BIT 1
#define KMAC_ALERT_TEST_REGWEN_BIT 31
 
// Controls the configurability of !!CFG_SHADOWED register.
#define KMAC_CFG_REGWEN_REG_OFFSET 0x10
#define KMAC_CFG_REGWEN_REG_RESVAL 0x1u
#define KMAC_CFG_REGWEN_EN_BIT 0
 
// KMAC Configuration register.
#define KMAC_CFG_SHADOWED_REG_OFFSET 0x14
#define KMAC_CFG_SHADOWED_REG_RESVAL 0x0u
#define KMAC_CFG_SHADOWED_KMAC_EN_BIT 0
#define KMAC_CFG_SHADOWED_KSTRENGTH_MASK 0x7u
#define KMAC_CFG_SHADOWED_KSTRENGTH_OFFSET 1
#define KMAC_CFG_SHADOWED_KSTRENGTH_FIELD \
  ((bitfield_field32_t) { .mask = KMAC_CFG_SHADOWED_KSTRENGTH_MASK, .index = KMAC_CFG_SHADOWED_KSTRENGTH_OFFSET })
#define KMAC_CFG_SHADOWED_KSTRENGTH_VALUE_L128 0x0
#define KMAC_CFG_SHADOWED_KSTRENGTH_VALUE_L224 0x1
#define KMAC_CFG_SHADOWED_KSTRENGTH_VALUE_L256 0x2
#define KMAC_CFG_SHADOWED_KSTRENGTH_VALUE_L384 0x3
#define KMAC_CFG_SHADOWED_KSTRENGTH_VALUE_L512 0x4
#define KMAC_CFG_SHADOWED_MODE_MASK 0x3u
#define KMAC_CFG_SHADOWED_MODE_OFFSET 4
#define KMAC_CFG_SHADOWED_MODE_FIELD \
  ((bitfield_field32_t) { .mask = KMAC_CFG_SHADOWED_MODE_MASK, .index = KMAC_CFG_SHADOWED_MODE_OFFSET })
#define KMAC_CFG_SHADOWED_MODE_VALUE_SHA3 0x0
#define KMAC_CFG_SHADOWED_MODE_VALUE_SHAKE 0x2
#define KMAC_CFG_SHADOWED_MODE_VALUE_CSHAKE 0x3
#define KMAC_CFG_SHADOWED_MSG_ENDIANNESS_BIT 8
#define KMAC_CFG_SHADOWED_STATE_ENDIANNESS_BIT 9
#define KMAC_CFG_SHADOWED_SIDELOAD_BIT 12
#define KMAC_CFG_SHADOWED_ENTROPY_MODE_MASK 0x3u
#define KMAC_CFG_SHADOWED_ENTROPY_MODE_OFFSET 16
#define KMAC_CFG_SHADOWED_ENTROPY_MODE_FIELD \
  ((bitfield_field32_t) { .mask = KMAC_CFG_SHADOWED_ENTROPY_MODE_MASK, .index = KMAC_CFG_SHADOWED_ENTROPY_MODE_OFFSET })
#define KMAC_CFG_SHADOWED_ENTROPY_MODE_VALUE_IDLE_MODE 0x0
#define KMAC_CFG_SHADOWED_ENTROPY_MODE_VALUE_EDN_MODE 0x1
#define KMAC_CFG_SHADOWED_ENTROPY_MODE_VALUE_SW_MODE 0x2
#define KMAC_CFG_SHADOWED_ENTROPY_FAST_PROCESS_BIT 19
#define KMAC_CFG_SHADOWED_MSG_MASK_BIT 20
#define KMAC_CFG_SHADOWED_ENTROPY_READY_BIT 24
#define KMAC_CFG_SHADOWED_EN_UNSUPPORTED_MODESTRENGTH_BIT 26
 
// KMAC/ SHA3 command register.
#define KMAC_CMD_REG_OFFSET 0x18
#define KMAC_CMD_REG_RESVAL 0x0u
#define KMAC_CMD_CMD_MASK 0x3fu
#define KMAC_CMD_CMD_OFFSET 0
#define KMAC_CMD_CMD_FIELD \
  ((bitfield_field32_t) { .mask = KMAC_CMD_CMD_MASK, .index = KMAC_CMD_CMD_OFFSET })
#define KMAC_CMD_CMD_VALUE_START 0x7
#define KMAC_CMD_CMD_VALUE_PROCESS 0x32
#define KMAC_CMD_CMD_VALUE_RUN 0x2e
#define KMAC_CMD_CMD_VALUE_DONE 0x35
#define KMAC_CMD_CMD_VALUE_STOP 0x1c
#define KMAC_CMD_CMD_VALUE_STATE_WRITE 0x1b
#define KMAC_CMD_CMD_VALUE_CONTINUE 0x29
#define KMAC_CMD_ENTROPY_REQ_BIT 8
#define KMAC_CMD_HASH_CNT_CLR_BIT 9
#define KMAC_CMD_ERR_PROCESSED_BIT 10
 
// KMAC/SHA3 Status register.
#define KMAC_STATUS_REG_OFFSET 0x1c
#define KMAC_STATUS_REG_RESVAL 0x4001u
#define KMAC_STATUS_SHA3_IDLE_BIT 0
#define KMAC_STATUS_SHA3_ABSORB_BIT 1
#define KMAC_STATUS_SHA3_SQUEEZE_BIT 2
#define KMAC_STATUS_SHA3_STOPPED_BIT 3
#define KMAC_STATUS_STATE_WRITE_BIT 4
#define KMAC_STATUS_FIFO_DEPTH_MASK 0x1fu
#define KMAC_STATUS_FIFO_DEPTH_OFFSET 8
#define KMAC_STATUS_FIFO_DEPTH_FIELD \
  ((bitfield_field32_t) { .mask = KMAC_STATUS_FIFO_DEPTH_MASK, .index = KMAC_STATUS_FIFO_DEPTH_OFFSET })
#define KMAC_STATUS_FIFO_EMPTY_BIT 14
#define KMAC_STATUS_FIFO_FULL_BIT 15
#define KMAC_STATUS_ALERT_FATAL_FAULT_BIT 16
#define KMAC_STATUS_ALERT_RECOV_CTRL_UPDATE_ERR_BIT 17
 
// Entropy Timer Periods.
#define KMAC_ENTROPY_PERIOD_REG_OFFSET 0x20
#define KMAC_ENTROPY_PERIOD_REG_RESVAL 0x0u
#define KMAC_ENTROPY_PERIOD_PRESCALER_MASK 0x3ffu
#define KMAC_ENTROPY_PERIOD_PRESCALER_OFFSET 0
#define KMAC_ENTROPY_PERIOD_PRESCALER_FIELD \
  ((bitfield_field32_t) { .mask = KMAC_ENTROPY_PERIOD_PRESCALER_MASK, .index = KMAC_ENTROPY_PERIOD_PRESCALER_OFFSET })
#define KMAC_ENTROPY_PERIOD_WAIT_TIMER_MASK 0xffffu
#define KMAC_ENTROPY_PERIOD_WAIT_TIMER_OFFSET 16
#define KMAC_ENTROPY_PERIOD_WAIT_TIMER_FIELD \
  ((bitfield_field32_t) { .mask = KMAC_ENTROPY_PERIOD_WAIT_TIMER_MASK, .index = KMAC_ENTROPY_PERIOD_WAIT_TIMER_OFFSET })
 
// Entropy Refresh Counter
#define KMAC_ENTROPY_REFRESH_HASH_CNT_REG_OFFSET 0x24
#define KMAC_ENTROPY_REFRESH_HASH_CNT_REG_RESVAL 0x0u
#define KMAC_ENTROPY_REFRESH_HASH_CNT_HASH_CNT_MASK 0x3ffu
#define KMAC_ENTROPY_REFRESH_HASH_CNT_HASH_CNT_OFFSET 0
#define KMAC_ENTROPY_REFRESH_HASH_CNT_HASH_CNT_FIELD \
  ((bitfield_field32_t) { .mask = KMAC_ENTROPY_REFRESH_HASH_CNT_HASH_CNT_MASK, .index = KMAC_ENTROPY_REFRESH_HASH_CNT_HASH_CNT_OFFSET })
 
// Entropy Refresh Threshold
#define KMAC_ENTROPY_REFRESH_THRESHOLD_SHADOWED_REG_OFFSET 0x28
#define KMAC_ENTROPY_REFRESH_THRESHOLD_SHADOWED_REG_RESVAL 0x0u
#define KMAC_ENTROPY_REFRESH_THRESHOLD_SHADOWED_THRESHOLD_MASK 0x3ffu
#define KMAC_ENTROPY_REFRESH_THRESHOLD_SHADOWED_THRESHOLD_OFFSET 0
#define KMAC_ENTROPY_REFRESH_THRESHOLD_SHADOWED_THRESHOLD_FIELD \
  ((bitfield_field32_t) { .mask = KMAC_ENTROPY_REFRESH_THRESHOLD_SHADOWED_THRESHOLD_MASK, .index = KMAC_ENTROPY_REFRESH_THRESHOLD_SHADOWED_THRESHOLD_OFFSET })
 
// Entropy Seed
#define KMAC_ENTROPY_SEED_REG_OFFSET 0x2c
#define KMAC_ENTROPY_SEED_REG_RESVAL 0x0u
 
// KMAC Secret Key
#define KMAC_KEY_SHARE0_KEY_FIELD_WIDTH 32
#define KMAC_KEY_SHARE0_MULTIREG_COUNT 16
 
// KMAC Secret Key
#define KMAC_KEY_SHARE0_0_REG_OFFSET 0x30
#define KMAC_KEY_SHARE0_0_REG_RESVAL 0x0u
 
// KMAC Secret Key
#define KMAC_KEY_SHARE0_1_REG_OFFSET 0x34
#define KMAC_KEY_SHARE0_1_REG_RESVAL 0x0u
 
// KMAC Secret Key
#define KMAC_KEY_SHARE0_2_REG_OFFSET 0x38
#define KMAC_KEY_SHARE0_2_REG_RESVAL 0x0u
 
// KMAC Secret Key
#define KMAC_KEY_SHARE0_3_REG_OFFSET 0x3c
#define KMAC_KEY_SHARE0_3_REG_RESVAL 0x0u
 
// KMAC Secret Key
#define KMAC_KEY_SHARE0_4_REG_OFFSET 0x40
#define KMAC_KEY_SHARE0_4_REG_RESVAL 0x0u
 
// KMAC Secret Key
#define KMAC_KEY_SHARE0_5_REG_OFFSET 0x44
#define KMAC_KEY_SHARE0_5_REG_RESVAL 0x0u
 
// KMAC Secret Key
#define KMAC_KEY_SHARE0_6_REG_OFFSET 0x48
#define KMAC_KEY_SHARE0_6_REG_RESVAL 0x0u
 
// KMAC Secret Key
#define KMAC_KEY_SHARE0_7_REG_OFFSET 0x4c
#define KMAC_KEY_SHARE0_7_REG_RESVAL 0x0u
 
// KMAC Secret Key
#define KMAC_KEY_SHARE0_8_REG_OFFSET 0x50
#define KMAC_KEY_SHARE0_8_REG_RESVAL 0x0u
 
// KMAC Secret Key
#define KMAC_KEY_SHARE0_9_REG_OFFSET 0x54
#define KMAC_KEY_SHARE0_9_REG_RESVAL 0x0u
 
// KMAC Secret Key
#define KMAC_KEY_SHARE0_10_REG_OFFSET 0x58
#define KMAC_KEY_SHARE0_10_REG_RESVAL 0x0u
 
// KMAC Secret Key
#define KMAC_KEY_SHARE0_11_REG_OFFSET 0x5c
#define KMAC_KEY_SHARE0_11_REG_RESVAL 0x0u
 
// KMAC Secret Key
#define KMAC_KEY_SHARE0_12_REG_OFFSET 0x60
#define KMAC_KEY_SHARE0_12_REG_RESVAL 0x0u
 
// KMAC Secret Key
#define KMAC_KEY_SHARE0_13_REG_OFFSET 0x64
#define KMAC_KEY_SHARE0_13_REG_RESVAL 0x0u
 
// KMAC Secret Key
#define KMAC_KEY_SHARE0_14_REG_OFFSET 0x68
#define KMAC_KEY_SHARE0_14_REG_RESVAL 0x0u
 
// KMAC Secret Key
#define KMAC_KEY_SHARE0_15_REG_OFFSET 0x6c
#define KMAC_KEY_SHARE0_15_REG_RESVAL 0x0u
 
// KMAC Secret Key, 2nd share.
#define KMAC_KEY_SHARE1_KEY_FIELD_WIDTH 32
#define KMAC_KEY_SHARE1_MULTIREG_COUNT 16
 
// KMAC Secret Key, 2nd share.
#define KMAC_KEY_SHARE1_0_REG_OFFSET 0x70
#define KMAC_KEY_SHARE1_0_REG_RESVAL 0x0u
 
// KMAC Secret Key, 2nd share.
#define KMAC_KEY_SHARE1_1_REG_OFFSET 0x74
#define KMAC_KEY_SHARE1_1_REG_RESVAL 0x0u
 
// KMAC Secret Key, 2nd share.
#define KMAC_KEY_SHARE1_2_REG_OFFSET 0x78
#define KMAC_KEY_SHARE1_2_REG_RESVAL 0x0u
 
// KMAC Secret Key, 2nd share.
#define KMAC_KEY_SHARE1_3_REG_OFFSET 0x7c
#define KMAC_KEY_SHARE1_3_REG_RESVAL 0x0u
 
// KMAC Secret Key, 2nd share.
#define KMAC_KEY_SHARE1_4_REG_OFFSET 0x80
#define KMAC_KEY_SHARE1_4_REG_RESVAL 0x0u
 
// KMAC Secret Key, 2nd share.
#define KMAC_KEY_SHARE1_5_REG_OFFSET 0x84
#define KMAC_KEY_SHARE1_5_REG_RESVAL 0x0u
 
// KMAC Secret Key, 2nd share.
#define KMAC_KEY_SHARE1_6_REG_OFFSET 0x88
#define KMAC_KEY_SHARE1_6_REG_RESVAL 0x0u
 
// KMAC Secret Key, 2nd share.
#define KMAC_KEY_SHARE1_7_REG_OFFSET 0x8c
#define KMAC_KEY_SHARE1_7_REG_RESVAL 0x0u
 
// KMAC Secret Key, 2nd share.
#define KMAC_KEY_SHARE1_8_REG_OFFSET 0x90
#define KMAC_KEY_SHARE1_8_REG_RESVAL 0x0u
 
// KMAC Secret Key, 2nd share.
#define KMAC_KEY_SHARE1_9_REG_OFFSET 0x94
#define KMAC_KEY_SHARE1_9_REG_RESVAL 0x0u
 
// KMAC Secret Key, 2nd share.
#define KMAC_KEY_SHARE1_10_REG_OFFSET 0x98
#define KMAC_KEY_SHARE1_10_REG_RESVAL 0x0u
 
// KMAC Secret Key, 2nd share.
#define KMAC_KEY_SHARE1_11_REG_OFFSET 0x9c
#define KMAC_KEY_SHARE1_11_REG_RESVAL 0x0u
 
// KMAC Secret Key, 2nd share.
#define KMAC_KEY_SHARE1_12_REG_OFFSET 0xa0
#define KMAC_KEY_SHARE1_12_REG_RESVAL 0x0u
 
// KMAC Secret Key, 2nd share.
#define KMAC_KEY_SHARE1_13_REG_OFFSET 0xa4
#define KMAC_KEY_SHARE1_13_REG_RESVAL 0x0u
 
// KMAC Secret Key, 2nd share.
#define KMAC_KEY_SHARE1_14_REG_OFFSET 0xa8
#define KMAC_KEY_SHARE1_14_REG_RESVAL 0x0u
 
// KMAC Secret Key, 2nd share.
#define KMAC_KEY_SHARE1_15_REG_OFFSET 0xac
#define KMAC_KEY_SHARE1_15_REG_RESVAL 0x0u
 
// Secret Key length in bit.
#define KMAC_KEY_LEN_REG_OFFSET 0xb0
#define KMAC_KEY_LEN_REG_RESVAL 0x0u
#define KMAC_KEY_LEN_LEN_MASK 0x7u
#define KMAC_KEY_LEN_LEN_OFFSET 0
#define KMAC_KEY_LEN_LEN_FIELD \
  ((bitfield_field32_t) { .mask = KMAC_KEY_LEN_LEN_MASK, .index = KMAC_KEY_LEN_LEN_OFFSET })
#define KMAC_KEY_LEN_LEN_VALUE_KEY128 0x0
#define KMAC_KEY_LEN_LEN_VALUE_KEY192 0x1
#define KMAC_KEY_LEN_LEN_VALUE_KEY256 0x2
#define KMAC_KEY_LEN_LEN_VALUE_KEY384 0x3
#define KMAC_KEY_LEN_LEN_VALUE_KEY512 0x4
 
// cSHAKE Prefix register.
#define KMAC_PREFIX_PREFIX_FIELD_WIDTH 32
#define KMAC_PREFIX_MULTIREG_COUNT 11
 
// cSHAKE Prefix register.
#define KMAC_PREFIX_0_REG_OFFSET 0xb4
#define KMAC_PREFIX_0_REG_RESVAL 0x0u
 
// cSHAKE Prefix register.
#define KMAC_PREFIX_1_REG_OFFSET 0xb8
#define KMAC_PREFIX_1_REG_RESVAL 0x0u
 
// cSHAKE Prefix register.
#define KMAC_PREFIX_2_REG_OFFSET 0xbc
#define KMAC_PREFIX_2_REG_RESVAL 0x0u
 
// cSHAKE Prefix register.
#define KMAC_PREFIX_3_REG_OFFSET 0xc0
#define KMAC_PREFIX_3_REG_RESVAL 0x0u
 
// cSHAKE Prefix register.
#define KMAC_PREFIX_4_REG_OFFSET 0xc4
#define KMAC_PREFIX_4_REG_RESVAL 0x0u
 
// cSHAKE Prefix register.
#define KMAC_PREFIX_5_REG_OFFSET 0xc8
#define KMAC_PREFIX_5_REG_RESVAL 0x0u
 
// cSHAKE Prefix register.
#define KMAC_PREFIX_6_REG_OFFSET 0xcc
#define KMAC_PREFIX_6_REG_RESVAL 0x0u
 
// cSHAKE Prefix register.
#define KMAC_PREFIX_7_REG_OFFSET 0xd0
#define KMAC_PREFIX_7_REG_RESVAL 0x0u
 
// cSHAKE Prefix register.
#define KMAC_PREFIX_8_REG_OFFSET 0xd4
#define KMAC_PREFIX_8_REG_RESVAL 0x0u
 
// cSHAKE Prefix register.
#define KMAC_PREFIX_9_REG_OFFSET 0xd8
#define KMAC_PREFIX_9_REG_RESVAL 0x0u
 
// cSHAKE Prefix register.
#define KMAC_PREFIX_10_REG_OFFSET 0xdc
#define KMAC_PREFIX_10_REG_RESVAL 0x0u
 
// KMAC/SHA3 Error Code
#define KMAC_ERR_CODE_REG_OFFSET 0xe0
#define KMAC_ERR_CODE_REG_RESVAL 0x0u
 
// Memory area: Keccak State (1600 bit) memory.
#define KMAC_STATE_REG_OFFSET 0x400
#define KMAC_STATE_SIZE_WORDS 128
#define KMAC_STATE_SIZE_BYTES 512
// Memory area: Message FIFO.
#define KMAC_MSG_FIFO_REG_OFFSET 0x800
#define KMAC_MSG_FIFO_SIZE_WORDS 512
#define KMAC_MSG_FIFO_SIZE_BYTES 2048
#ifdef __cplusplus
}  // extern "C"
#endif
#endif  // _KMAC_REG_DEFS_
// End generated register defines for kmac