keymgr_dpe_regs.h

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/**
 * @file
 * @brief Generated register defines for keymgr_dpe
 */
 
// Copyright information found in source file:
// Copyright lowRISC contributors (OpenTitan project).
 
// Licensing information found in source file:
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
 
#ifndef _KEYMGR_DPE_REG_DEFS_
#define _KEYMGR_DPE_REG_DEFS_
 
#ifdef __cplusplus
extern "C" {
#endif
// Number of Registers for SW inputs (Salt)
#define KEYMGR_DPE_PARAM_NUM_SALT_REG 8
 
// Number of Registers for SW inputs (SW binding)
#define KEYMGR_DPE_PARAM_NUM_SW_BINDING_REG 8
 
// Number of Registers for SW outputs
#define KEYMGR_DPE_PARAM_NUM_OUT_REG 8
 
// Number of Registers for key version
#define KEYMGR_DPE_PARAM_NUM_KEY_VERSION 1
 
// Number of maximum supported HW slots. If this value is changed then the
#define KEYMGR_DPE_PARAM_NUM_MAX_HW_SLOT 8
 
// Number of alerts
#define KEYMGR_DPE_PARAM_NUM_ALERTS 2
 
// Register width
#define KEYMGR_DPE_PARAM_REG_WIDTH 32
 
// Common Interrupt Offsets
#define KEYMGR_DPE_INTR_COMMON_OP_DONE_BIT 0
 
// Interrupt State Register
#define KEYMGR_DPE_INTR_STATE_REG_OFFSET 0x0
#define KEYMGR_DPE_INTR_STATE_REG_RESVAL 0x0u
#define KEYMGR_DPE_INTR_STATE_OP_DONE_BIT 0
 
// Interrupt Enable Register
#define KEYMGR_DPE_INTR_ENABLE_REG_OFFSET 0x4
#define KEYMGR_DPE_INTR_ENABLE_REG_RESVAL 0x0u
#define KEYMGR_DPE_INTR_ENABLE_OP_DONE_BIT 0
 
// Interrupt Test Register
#define KEYMGR_DPE_INTR_TEST_REG_OFFSET 0x8
#define KEYMGR_DPE_INTR_TEST_REG_RESVAL 0x0u
#define KEYMGR_DPE_INTR_TEST_OP_DONE_BIT 0
 
// Alert Test Register
#define KEYMGR_DPE_ALERT_TEST_REG_OFFSET 0xc
#define KEYMGR_DPE_ALERT_TEST_REG_RESVAL 0x80000000u
#define KEYMGR_DPE_ALERT_TEST_RECOV_OPERATION_ERR_BIT 0
#define KEYMGR_DPE_ALERT_TEST_FATAL_FAULT_ERR_BIT 1
#define KEYMGR_DPE_ALERT_TEST_REGWEN_BIT 31
 
// Key manager configuration enable
#define KEYMGR_DPE_CFG_REGWEN_REG_OFFSET 0x10
#define KEYMGR_DPE_CFG_REGWEN_REG_RESVAL 0x1u
#define KEYMGR_DPE_CFG_REGWEN_EN_BIT 0
 
// Key manager operation start
#define KEYMGR_DPE_START_REG_OFFSET 0x14
#define KEYMGR_DPE_START_REG_RESVAL 0x0u
#define KEYMGR_DPE_START_EN_BIT 0
#define KEYMGR_DPE_START_EN_VALUE_VALID_STATE 0x1
 
// Key manager operation controls
#define KEYMGR_DPE_CONTROL_SHADOWED_REG_OFFSET 0x18
#define KEYMGR_DPE_CONTROL_SHADOWED_REG_RESVAL 0x10u
#define KEYMGR_DPE_CONTROL_SHADOWED_OPERATION_MASK 0x7u
#define KEYMGR_DPE_CONTROL_SHADOWED_OPERATION_OFFSET 4
#define KEYMGR_DPE_CONTROL_SHADOWED_OPERATION_FIELD \
  ((bitfield_field32_t) { .mask = KEYMGR_DPE_CONTROL_SHADOWED_OPERATION_MASK, .index = KEYMGR_DPE_CONTROL_SHADOWED_OPERATION_OFFSET })
#define KEYMGR_DPE_CONTROL_SHADOWED_OPERATION_VALUE_ADVANCE 0x0
#define KEYMGR_DPE_CONTROL_SHADOWED_OPERATION_VALUE_ERASE_SLOT 0x1
#define KEYMGR_DPE_CONTROL_SHADOWED_OPERATION_VALUE_GENERATE_SW_OUTPUT 0x2
#define KEYMGR_DPE_CONTROL_SHADOWED_OPERATION_VALUE_GENERATE_HW_OUTPUT 0x3
#define KEYMGR_DPE_CONTROL_SHADOWED_OPERATION_VALUE_DISABLE 0x4
#define KEYMGR_DPE_CONTROL_SHADOWED_OPERATION_VALUE_LOAD_ROOT_KEY 0x5
#define KEYMGR_DPE_CONTROL_SHADOWED_DEST_SEL_MASK 0x7u
#define KEYMGR_DPE_CONTROL_SHADOWED_DEST_SEL_OFFSET 11
#define KEYMGR_DPE_CONTROL_SHADOWED_DEST_SEL_FIELD \
  ((bitfield_field32_t) { .mask = KEYMGR_DPE_CONTROL_SHADOWED_DEST_SEL_MASK, .index = KEYMGR_DPE_CONTROL_SHADOWED_DEST_SEL_OFFSET })
#define KEYMGR_DPE_CONTROL_SHADOWED_DEST_SEL_VALUE_NONE 0x0
#define KEYMGR_DPE_CONTROL_SHADOWED_DEST_SEL_VALUE_AES 0x1
#define KEYMGR_DPE_CONTROL_SHADOWED_DEST_SEL_VALUE_KMAC 0x2
#define KEYMGR_DPE_CONTROL_SHADOWED_DEST_SEL_VALUE_OTBN 0x3
#define KEYMGR_DPE_CONTROL_SHADOWED_DEST_SEL_VALUE_HMAC 0x4
#define KEYMGR_DPE_CONTROL_SHADOWED_SLOT_SRC_SEL_MASK 0x7u
#define KEYMGR_DPE_CONTROL_SHADOWED_SLOT_SRC_SEL_OFFSET 14
#define KEYMGR_DPE_CONTROL_SHADOWED_SLOT_SRC_SEL_FIELD \
  ((bitfield_field32_t) { .mask = KEYMGR_DPE_CONTROL_SHADOWED_SLOT_SRC_SEL_MASK, .index = KEYMGR_DPE_CONTROL_SHADOWED_SLOT_SRC_SEL_OFFSET })
#define KEYMGR_DPE_CONTROL_SHADOWED_SLOT_DST_SEL_MASK 0x7u
#define KEYMGR_DPE_CONTROL_SHADOWED_SLOT_DST_SEL_OFFSET 18
#define KEYMGR_DPE_CONTROL_SHADOWED_SLOT_DST_SEL_FIELD \
  ((bitfield_field32_t) { .mask = KEYMGR_DPE_CONTROL_SHADOWED_SLOT_DST_SEL_MASK, .index = KEYMGR_DPE_CONTROL_SHADOWED_SLOT_DST_SEL_OFFSET })
#define KEYMGR_DPE_CONTROL_SHADOWED_SW_BINDING_ONLY_BIT 22
 
// sideload key slots clear
#define KEYMGR_DPE_SIDELOAD_CLEAR_REG_OFFSET 0x1c
#define KEYMGR_DPE_SIDELOAD_CLEAR_REG_RESVAL 0x0u
#define KEYMGR_DPE_SIDELOAD_CLEAR_VAL_MASK 0x7u
#define KEYMGR_DPE_SIDELOAD_CLEAR_VAL_OFFSET 0
#define KEYMGR_DPE_SIDELOAD_CLEAR_VAL_FIELD \
  ((bitfield_field32_t) { .mask = KEYMGR_DPE_SIDELOAD_CLEAR_VAL_MASK, .index = KEYMGR_DPE_SIDELOAD_CLEAR_VAL_OFFSET })
#define KEYMGR_DPE_SIDELOAD_CLEAR_VAL_VALUE_NONE 0x0
#define KEYMGR_DPE_SIDELOAD_CLEAR_VAL_VALUE_AES 0x1
#define KEYMGR_DPE_SIDELOAD_CLEAR_VAL_VALUE_KMAC 0x2
#define KEYMGR_DPE_SIDELOAD_CLEAR_VAL_VALUE_OTBN 0x3
#define KEYMGR_DPE_SIDELOAD_CLEAR_VAL_VALUE_HMAC 0x4
 
// regwen for reseed interval
#define KEYMGR_DPE_RESEED_INTERVAL_REGWEN_REG_OFFSET 0x20
#define KEYMGR_DPE_RESEED_INTERVAL_REGWEN_REG_RESVAL 0x1u
#define KEYMGR_DPE_RESEED_INTERVAL_REGWEN_EN_BIT 0
 
// Reseed interval for key manager entropy reseed
#define KEYMGR_DPE_RESEED_INTERVAL_SHADOWED_REG_OFFSET 0x24
#define KEYMGR_DPE_RESEED_INTERVAL_SHADOWED_REG_RESVAL 0x100u
#define KEYMGR_DPE_RESEED_INTERVAL_SHADOWED_VAL_MASK 0xffffu
#define KEYMGR_DPE_RESEED_INTERVAL_SHADOWED_VAL_OFFSET 0
#define KEYMGR_DPE_RESEED_INTERVAL_SHADOWED_VAL_FIELD \
  ((bitfield_field32_t) { .mask = KEYMGR_DPE_RESEED_INTERVAL_SHADOWED_VAL_MASK, .index = KEYMGR_DPE_RESEED_INTERVAL_SHADOWED_VAL_OFFSET })
 
// Register write enable for SLOT_POLICY
#define KEYMGR_DPE_SLOT_POLICY_REGWEN_REG_OFFSET 0x28
#define KEYMGR_DPE_SLOT_POLICY_REGWEN_REG_RESVAL 0x1u
#define KEYMGR_DPE_SLOT_POLICY_REGWEN_EN_BIT 0
 
// Policy bits for the child DPE context
#define KEYMGR_DPE_SLOT_POLICY_REG_OFFSET 0x2c
#define KEYMGR_DPE_SLOT_POLICY_REG_RESVAL 0x0u
#define KEYMGR_DPE_SLOT_POLICY_ALLOW_CHILD_BIT 0
#define KEYMGR_DPE_SLOT_POLICY_EXPORTABLE_BIT 1
#define KEYMGR_DPE_SLOT_POLICY_RETAIN_PARENT_BIT 2
 
// Register write enable for SOFTWARE_BINDING
#define KEYMGR_DPE_SW_BINDING_REGWEN_REG_OFFSET 0x30
#define KEYMGR_DPE_SW_BINDING_REGWEN_REG_RESVAL 0x1u
#define KEYMGR_DPE_SW_BINDING_REGWEN_EN_BIT 0
 
// Software binding input of the key manager.
#define KEYMGR_DPE_SW_BINDING_VAL_FIELD_WIDTH 32
#define KEYMGR_DPE_SW_BINDING_MULTIREG_COUNT 8
 
// Software binding input of the key manager.
#define KEYMGR_DPE_SW_BINDING_0_REG_OFFSET 0x34
#define KEYMGR_DPE_SW_BINDING_0_REG_RESVAL 0x0u
 
// Software binding input of the key manager.
#define KEYMGR_DPE_SW_BINDING_1_REG_OFFSET 0x38
#define KEYMGR_DPE_SW_BINDING_1_REG_RESVAL 0x0u
 
// Software binding input of the key manager.
#define KEYMGR_DPE_SW_BINDING_2_REG_OFFSET 0x3c
#define KEYMGR_DPE_SW_BINDING_2_REG_RESVAL 0x0u
 
// Software binding input of the key manager.
#define KEYMGR_DPE_SW_BINDING_3_REG_OFFSET 0x40
#define KEYMGR_DPE_SW_BINDING_3_REG_RESVAL 0x0u
 
// Software binding input of the key manager.
#define KEYMGR_DPE_SW_BINDING_4_REG_OFFSET 0x44
#define KEYMGR_DPE_SW_BINDING_4_REG_RESVAL 0x0u
 
// Software binding input of the key manager.
#define KEYMGR_DPE_SW_BINDING_5_REG_OFFSET 0x48
#define KEYMGR_DPE_SW_BINDING_5_REG_RESVAL 0x0u
 
// Software binding input of the key manager.
#define KEYMGR_DPE_SW_BINDING_6_REG_OFFSET 0x4c
#define KEYMGR_DPE_SW_BINDING_6_REG_RESVAL 0x0u
 
// Software binding input of the key manager.
#define KEYMGR_DPE_SW_BINDING_7_REG_OFFSET 0x50
#define KEYMGR_DPE_SW_BINDING_7_REG_RESVAL 0x0u
 
// Salt value used as part of output generation (common parameters)
#define KEYMGR_DPE_SALT_VAL_FIELD_WIDTH 32
#define KEYMGR_DPE_SALT_MULTIREG_COUNT 8
 
// Salt value used as part of output generation
#define KEYMGR_DPE_SALT_0_REG_OFFSET 0x54
#define KEYMGR_DPE_SALT_0_REG_RESVAL 0x0u
 
// Salt value used as part of output generation
#define KEYMGR_DPE_SALT_1_REG_OFFSET 0x58
#define KEYMGR_DPE_SALT_1_REG_RESVAL 0x0u
 
// Salt value used as part of output generation
#define KEYMGR_DPE_SALT_2_REG_OFFSET 0x5c
#define KEYMGR_DPE_SALT_2_REG_RESVAL 0x0u
 
// Salt value used as part of output generation
#define KEYMGR_DPE_SALT_3_REG_OFFSET 0x60
#define KEYMGR_DPE_SALT_3_REG_RESVAL 0x0u
 
// Salt value used as part of output generation
#define KEYMGR_DPE_SALT_4_REG_OFFSET 0x64
#define KEYMGR_DPE_SALT_4_REG_RESVAL 0x0u
 
// Salt value used as part of output generation
#define KEYMGR_DPE_SALT_5_REG_OFFSET 0x68
#define KEYMGR_DPE_SALT_5_REG_RESVAL 0x0u
 
// Salt value used as part of output generation
#define KEYMGR_DPE_SALT_6_REG_OFFSET 0x6c
#define KEYMGR_DPE_SALT_6_REG_RESVAL 0x0u
 
// Salt value used as part of output generation
#define KEYMGR_DPE_SALT_7_REG_OFFSET 0x70
#define KEYMGR_DPE_SALT_7_REG_RESVAL 0x0u
 
// Version used as part of output generation (common parameters)
#define KEYMGR_DPE_KEY_VERSION_VAL_FIELD_WIDTH 32
#define KEYMGR_DPE_KEY_VERSION_MULTIREG_COUNT 1
 
// Version used as part of output generation
#define KEYMGR_DPE_KEY_VERSION_REG_OFFSET 0x74
#define KEYMGR_DPE_KEY_VERSION_REG_RESVAL 0x0u
 
// Register write enable for MAX_KEY_VERSION
#define KEYMGR_DPE_MAX_KEY_VER_REGWEN_REG_OFFSET 0x78
#define KEYMGR_DPE_MAX_KEY_VER_REGWEN_REG_RESVAL 0x1u
#define KEYMGR_DPE_MAX_KEY_VER_REGWEN_EN_BIT 0
 
// Max key version
#define KEYMGR_DPE_MAX_KEY_VER_SHADOWED_REG_OFFSET 0x7c
#define KEYMGR_DPE_MAX_KEY_VER_SHADOWED_REG_RESVAL 0x0u
 
// Key manager software output.
#define KEYMGR_DPE_SW_SHARE0_OUTPUT_VAL_FIELD_WIDTH 32
#define KEYMGR_DPE_SW_SHARE0_OUTPUT_MULTIREG_COUNT 8
 
// Key manager software output.
#define KEYMGR_DPE_SW_SHARE0_OUTPUT_0_REG_OFFSET 0x80
#define KEYMGR_DPE_SW_SHARE0_OUTPUT_0_REG_RESVAL 0x0u
 
// Key manager software output.
#define KEYMGR_DPE_SW_SHARE0_OUTPUT_1_REG_OFFSET 0x84
#define KEYMGR_DPE_SW_SHARE0_OUTPUT_1_REG_RESVAL 0x0u
 
// Key manager software output.
#define KEYMGR_DPE_SW_SHARE0_OUTPUT_2_REG_OFFSET 0x88
#define KEYMGR_DPE_SW_SHARE0_OUTPUT_2_REG_RESVAL 0x0u
 
// Key manager software output.
#define KEYMGR_DPE_SW_SHARE0_OUTPUT_3_REG_OFFSET 0x8c
#define KEYMGR_DPE_SW_SHARE0_OUTPUT_3_REG_RESVAL 0x0u
 
// Key manager software output.
#define KEYMGR_DPE_SW_SHARE0_OUTPUT_4_REG_OFFSET 0x90
#define KEYMGR_DPE_SW_SHARE0_OUTPUT_4_REG_RESVAL 0x0u
 
// Key manager software output.
#define KEYMGR_DPE_SW_SHARE0_OUTPUT_5_REG_OFFSET 0x94
#define KEYMGR_DPE_SW_SHARE0_OUTPUT_5_REG_RESVAL 0x0u
 
// Key manager software output.
#define KEYMGR_DPE_SW_SHARE0_OUTPUT_6_REG_OFFSET 0x98
#define KEYMGR_DPE_SW_SHARE0_OUTPUT_6_REG_RESVAL 0x0u
 
// Key manager software output.
#define KEYMGR_DPE_SW_SHARE0_OUTPUT_7_REG_OFFSET 0x9c
#define KEYMGR_DPE_SW_SHARE0_OUTPUT_7_REG_RESVAL 0x0u
 
// Key manager software output.
#define KEYMGR_DPE_SW_SHARE1_OUTPUT_VAL_FIELD_WIDTH 32
#define KEYMGR_DPE_SW_SHARE1_OUTPUT_MULTIREG_COUNT 8
 
// Key manager software output.
#define KEYMGR_DPE_SW_SHARE1_OUTPUT_0_REG_OFFSET 0xa0
#define KEYMGR_DPE_SW_SHARE1_OUTPUT_0_REG_RESVAL 0x0u
 
// Key manager software output.
#define KEYMGR_DPE_SW_SHARE1_OUTPUT_1_REG_OFFSET 0xa4
#define KEYMGR_DPE_SW_SHARE1_OUTPUT_1_REG_RESVAL 0x0u
 
// Key manager software output.
#define KEYMGR_DPE_SW_SHARE1_OUTPUT_2_REG_OFFSET 0xa8
#define KEYMGR_DPE_SW_SHARE1_OUTPUT_2_REG_RESVAL 0x0u
 
// Key manager software output.
#define KEYMGR_DPE_SW_SHARE1_OUTPUT_3_REG_OFFSET 0xac
#define KEYMGR_DPE_SW_SHARE1_OUTPUT_3_REG_RESVAL 0x0u
 
// Key manager software output.
#define KEYMGR_DPE_SW_SHARE1_OUTPUT_4_REG_OFFSET 0xb0
#define KEYMGR_DPE_SW_SHARE1_OUTPUT_4_REG_RESVAL 0x0u
 
// Key manager software output.
#define KEYMGR_DPE_SW_SHARE1_OUTPUT_5_REG_OFFSET 0xb4
#define KEYMGR_DPE_SW_SHARE1_OUTPUT_5_REG_RESVAL 0x0u
 
// Key manager software output.
#define KEYMGR_DPE_SW_SHARE1_OUTPUT_6_REG_OFFSET 0xb8
#define KEYMGR_DPE_SW_SHARE1_OUTPUT_6_REG_RESVAL 0x0u
 
// Key manager software output.
#define KEYMGR_DPE_SW_SHARE1_OUTPUT_7_REG_OFFSET 0xbc
#define KEYMGR_DPE_SW_SHARE1_OUTPUT_7_REG_RESVAL 0x0u
 
// Key manager working state.
#define KEYMGR_DPE_WORKING_STATE_REG_OFFSET 0xc0
#define KEYMGR_DPE_WORKING_STATE_REG_RESVAL 0x0u
#define KEYMGR_DPE_WORKING_STATE_STATE_MASK 0x3u
#define KEYMGR_DPE_WORKING_STATE_STATE_OFFSET 0
#define KEYMGR_DPE_WORKING_STATE_STATE_FIELD \
  ((bitfield_field32_t) { .mask = KEYMGR_DPE_WORKING_STATE_STATE_MASK, .index = KEYMGR_DPE_WORKING_STATE_STATE_OFFSET })
#define KEYMGR_DPE_WORKING_STATE_STATE_VALUE_RESET 0x0
#define KEYMGR_DPE_WORKING_STATE_STATE_VALUE_AVAILABLE 0x1
#define KEYMGR_DPE_WORKING_STATE_STATE_VALUE_DISABLED 0x2
#define KEYMGR_DPE_WORKING_STATE_STATE_VALUE_INVALID 0x3
 
// Key manager status.
#define KEYMGR_DPE_OP_STATUS_REG_OFFSET 0xc4
#define KEYMGR_DPE_OP_STATUS_REG_RESVAL 0x0u
#define KEYMGR_DPE_OP_STATUS_STATUS_MASK 0x3u
#define KEYMGR_DPE_OP_STATUS_STATUS_OFFSET 0
#define KEYMGR_DPE_OP_STATUS_STATUS_FIELD \
  ((bitfield_field32_t) { .mask = KEYMGR_DPE_OP_STATUS_STATUS_MASK, .index = KEYMGR_DPE_OP_STATUS_STATUS_OFFSET })
#define KEYMGR_DPE_OP_STATUS_STATUS_VALUE_IDLE 0x0
#define KEYMGR_DPE_OP_STATUS_STATUS_VALUE_WIP 0x1
#define KEYMGR_DPE_OP_STATUS_STATUS_VALUE_DONE_SUCCESS 0x2
#define KEYMGR_DPE_OP_STATUS_STATUS_VALUE_DONE_ERROR 0x3
 
// Read metadata (low word) for each HW slot.
#define KEYMGR_DPE_METADATA_LOW_MAX_KEY_VERSION_FIELD_WIDTH 32
#define KEYMGR_DPE_METADATA_LOW_MULTIREG_COUNT 8
 
// Read metadata (low word) for each HW slot.
#define KEYMGR_DPE_METADATA_LOW_0_REG_OFFSET 0xc8
#define KEYMGR_DPE_METADATA_LOW_0_REG_RESVAL 0x0u
 
// Read metadata (low word) for each HW slot.
#define KEYMGR_DPE_METADATA_LOW_1_REG_OFFSET 0xcc
#define KEYMGR_DPE_METADATA_LOW_1_REG_RESVAL 0x0u
 
// Read metadata (low word) for each HW slot.
#define KEYMGR_DPE_METADATA_LOW_2_REG_OFFSET 0xd0
#define KEYMGR_DPE_METADATA_LOW_2_REG_RESVAL 0x0u
 
// Read metadata (low word) for each HW slot.
#define KEYMGR_DPE_METADATA_LOW_3_REG_OFFSET 0xd4
#define KEYMGR_DPE_METADATA_LOW_3_REG_RESVAL 0x0u
 
// Read metadata (low word) for each HW slot.
#define KEYMGR_DPE_METADATA_LOW_4_REG_OFFSET 0xd8
#define KEYMGR_DPE_METADATA_LOW_4_REG_RESVAL 0x0u
 
// Read metadata (low word) for each HW slot.
#define KEYMGR_DPE_METADATA_LOW_5_REG_OFFSET 0xdc
#define KEYMGR_DPE_METADATA_LOW_5_REG_RESVAL 0x0u
 
// Read metadata (low word) for each HW slot.
#define KEYMGR_DPE_METADATA_LOW_6_REG_OFFSET 0xe0
#define KEYMGR_DPE_METADATA_LOW_6_REG_RESVAL 0x0u
 
// Read metadata (low word) for each HW slot.
#define KEYMGR_DPE_METADATA_LOW_7_REG_OFFSET 0xe4
#define KEYMGR_DPE_METADATA_LOW_7_REG_RESVAL 0x0u
 
// Read metadata (high word) for each HW slot.
#define KEYMGR_DPE_METADATA_HIGH_VALID_FIELD_WIDTH 1
#define KEYMGR_DPE_METADATA_HIGH_BOOT_STAGE_FIELD_WIDTH 2
#define KEYMGR_DPE_METADATA_HIGH_ALLOW_CHILD_POLICY_FIELD_WIDTH 1
#define KEYMGR_DPE_METADATA_HIGH_EXPORTABLE_POLICY_FIELD_WIDTH 1
#define KEYMGR_DPE_METADATA_HIGH_RETAIN_PARENT_POLICY_FIELD_WIDTH 1
#define KEYMGR_DPE_METADATA_HIGH_MULTIREG_COUNT 8
 
// Read metadata (high word) for each HW slot.
#define KEYMGR_DPE_METADATA_HIGH_0_REG_OFFSET 0xe8
#define KEYMGR_DPE_METADATA_HIGH_0_REG_RESVAL 0x0u
#define KEYMGR_DPE_METADATA_HIGH_0_VALID_0_BIT 0
#define KEYMGR_DPE_METADATA_HIGH_0_BOOT_STAGE_0_MASK 0x3u
#define KEYMGR_DPE_METADATA_HIGH_0_BOOT_STAGE_0_OFFSET 1
#define KEYMGR_DPE_METADATA_HIGH_0_BOOT_STAGE_0_FIELD \
  ((bitfield_field32_t) { .mask = KEYMGR_DPE_METADATA_HIGH_0_BOOT_STAGE_0_MASK, .index = KEYMGR_DPE_METADATA_HIGH_0_BOOT_STAGE_0_OFFSET })
#define KEYMGR_DPE_METADATA_HIGH_0_ALLOW_CHILD_POLICY_0_BIT 3
#define KEYMGR_DPE_METADATA_HIGH_0_EXPORTABLE_POLICY_0_BIT 4
#define KEYMGR_DPE_METADATA_HIGH_0_RETAIN_PARENT_POLICY_0_BIT 5
 
// Read metadata (high word) for each HW slot.
#define KEYMGR_DPE_METADATA_HIGH_1_REG_OFFSET 0xec
#define KEYMGR_DPE_METADATA_HIGH_1_REG_RESVAL 0x0u
#define KEYMGR_DPE_METADATA_HIGH_1_VALID_1_BIT 0
#define KEYMGR_DPE_METADATA_HIGH_1_BOOT_STAGE_1_MASK 0x3u
#define KEYMGR_DPE_METADATA_HIGH_1_BOOT_STAGE_1_OFFSET 1
#define KEYMGR_DPE_METADATA_HIGH_1_BOOT_STAGE_1_FIELD \
  ((bitfield_field32_t) { .mask = KEYMGR_DPE_METADATA_HIGH_1_BOOT_STAGE_1_MASK, .index = KEYMGR_DPE_METADATA_HIGH_1_BOOT_STAGE_1_OFFSET })
#define KEYMGR_DPE_METADATA_HIGH_1_ALLOW_CHILD_POLICY_1_BIT 3
#define KEYMGR_DPE_METADATA_HIGH_1_EXPORTABLE_POLICY_1_BIT 4
#define KEYMGR_DPE_METADATA_HIGH_1_RETAIN_PARENT_POLICY_1_BIT 5
 
// Read metadata (high word) for each HW slot.
#define KEYMGR_DPE_METADATA_HIGH_2_REG_OFFSET 0xf0
#define KEYMGR_DPE_METADATA_HIGH_2_REG_RESVAL 0x0u
#define KEYMGR_DPE_METADATA_HIGH_2_VALID_2_BIT 0
#define KEYMGR_DPE_METADATA_HIGH_2_BOOT_STAGE_2_MASK 0x3u
#define KEYMGR_DPE_METADATA_HIGH_2_BOOT_STAGE_2_OFFSET 1
#define KEYMGR_DPE_METADATA_HIGH_2_BOOT_STAGE_2_FIELD \
  ((bitfield_field32_t) { .mask = KEYMGR_DPE_METADATA_HIGH_2_BOOT_STAGE_2_MASK, .index = KEYMGR_DPE_METADATA_HIGH_2_BOOT_STAGE_2_OFFSET })
#define KEYMGR_DPE_METADATA_HIGH_2_ALLOW_CHILD_POLICY_2_BIT 3
#define KEYMGR_DPE_METADATA_HIGH_2_EXPORTABLE_POLICY_2_BIT 4
#define KEYMGR_DPE_METADATA_HIGH_2_RETAIN_PARENT_POLICY_2_BIT 5
 
// Read metadata (high word) for each HW slot.
#define KEYMGR_DPE_METADATA_HIGH_3_REG_OFFSET 0xf4
#define KEYMGR_DPE_METADATA_HIGH_3_REG_RESVAL 0x0u
#define KEYMGR_DPE_METADATA_HIGH_3_VALID_3_BIT 0
#define KEYMGR_DPE_METADATA_HIGH_3_BOOT_STAGE_3_MASK 0x3u
#define KEYMGR_DPE_METADATA_HIGH_3_BOOT_STAGE_3_OFFSET 1
#define KEYMGR_DPE_METADATA_HIGH_3_BOOT_STAGE_3_FIELD \
  ((bitfield_field32_t) { .mask = KEYMGR_DPE_METADATA_HIGH_3_BOOT_STAGE_3_MASK, .index = KEYMGR_DPE_METADATA_HIGH_3_BOOT_STAGE_3_OFFSET })
#define KEYMGR_DPE_METADATA_HIGH_3_ALLOW_CHILD_POLICY_3_BIT 3
#define KEYMGR_DPE_METADATA_HIGH_3_EXPORTABLE_POLICY_3_BIT 4
#define KEYMGR_DPE_METADATA_HIGH_3_RETAIN_PARENT_POLICY_3_BIT 5
 
// Read metadata (high word) for each HW slot.
#define KEYMGR_DPE_METADATA_HIGH_4_REG_OFFSET 0xf8
#define KEYMGR_DPE_METADATA_HIGH_4_REG_RESVAL 0x0u
#define KEYMGR_DPE_METADATA_HIGH_4_VALID_4_BIT 0
#define KEYMGR_DPE_METADATA_HIGH_4_BOOT_STAGE_4_MASK 0x3u
#define KEYMGR_DPE_METADATA_HIGH_4_BOOT_STAGE_4_OFFSET 1
#define KEYMGR_DPE_METADATA_HIGH_4_BOOT_STAGE_4_FIELD \
  ((bitfield_field32_t) { .mask = KEYMGR_DPE_METADATA_HIGH_4_BOOT_STAGE_4_MASK, .index = KEYMGR_DPE_METADATA_HIGH_4_BOOT_STAGE_4_OFFSET })
#define KEYMGR_DPE_METADATA_HIGH_4_ALLOW_CHILD_POLICY_4_BIT 3
#define KEYMGR_DPE_METADATA_HIGH_4_EXPORTABLE_POLICY_4_BIT 4
#define KEYMGR_DPE_METADATA_HIGH_4_RETAIN_PARENT_POLICY_4_BIT 5
 
// Read metadata (high word) for each HW slot.
#define KEYMGR_DPE_METADATA_HIGH_5_REG_OFFSET 0xfc
#define KEYMGR_DPE_METADATA_HIGH_5_REG_RESVAL 0x0u
#define KEYMGR_DPE_METADATA_HIGH_5_VALID_5_BIT 0
#define KEYMGR_DPE_METADATA_HIGH_5_BOOT_STAGE_5_MASK 0x3u
#define KEYMGR_DPE_METADATA_HIGH_5_BOOT_STAGE_5_OFFSET 1
#define KEYMGR_DPE_METADATA_HIGH_5_BOOT_STAGE_5_FIELD \
  ((bitfield_field32_t) { .mask = KEYMGR_DPE_METADATA_HIGH_5_BOOT_STAGE_5_MASK, .index = KEYMGR_DPE_METADATA_HIGH_5_BOOT_STAGE_5_OFFSET })
#define KEYMGR_DPE_METADATA_HIGH_5_ALLOW_CHILD_POLICY_5_BIT 3
#define KEYMGR_DPE_METADATA_HIGH_5_EXPORTABLE_POLICY_5_BIT 4
#define KEYMGR_DPE_METADATA_HIGH_5_RETAIN_PARENT_POLICY_5_BIT 5
 
// Read metadata (high word) for each HW slot.
#define KEYMGR_DPE_METADATA_HIGH_6_REG_OFFSET 0x100
#define KEYMGR_DPE_METADATA_HIGH_6_REG_RESVAL 0x0u
#define KEYMGR_DPE_METADATA_HIGH_6_VALID_6_BIT 0
#define KEYMGR_DPE_METADATA_HIGH_6_BOOT_STAGE_6_MASK 0x3u
#define KEYMGR_DPE_METADATA_HIGH_6_BOOT_STAGE_6_OFFSET 1
#define KEYMGR_DPE_METADATA_HIGH_6_BOOT_STAGE_6_FIELD \
  ((bitfield_field32_t) { .mask = KEYMGR_DPE_METADATA_HIGH_6_BOOT_STAGE_6_MASK, .index = KEYMGR_DPE_METADATA_HIGH_6_BOOT_STAGE_6_OFFSET })
#define KEYMGR_DPE_METADATA_HIGH_6_ALLOW_CHILD_POLICY_6_BIT 3
#define KEYMGR_DPE_METADATA_HIGH_6_EXPORTABLE_POLICY_6_BIT 4
#define KEYMGR_DPE_METADATA_HIGH_6_RETAIN_PARENT_POLICY_6_BIT 5
 
// Read metadata (high word) for each HW slot.
#define KEYMGR_DPE_METADATA_HIGH_7_REG_OFFSET 0x104
#define KEYMGR_DPE_METADATA_HIGH_7_REG_RESVAL 0x0u
#define KEYMGR_DPE_METADATA_HIGH_7_VALID_7_BIT 0
#define KEYMGR_DPE_METADATA_HIGH_7_BOOT_STAGE_7_MASK 0x3u
#define KEYMGR_DPE_METADATA_HIGH_7_BOOT_STAGE_7_OFFSET 1
#define KEYMGR_DPE_METADATA_HIGH_7_BOOT_STAGE_7_FIELD \
  ((bitfield_field32_t) { .mask = KEYMGR_DPE_METADATA_HIGH_7_BOOT_STAGE_7_MASK, .index = KEYMGR_DPE_METADATA_HIGH_7_BOOT_STAGE_7_OFFSET })
#define KEYMGR_DPE_METADATA_HIGH_7_ALLOW_CHILD_POLICY_7_BIT 3
#define KEYMGR_DPE_METADATA_HIGH_7_EXPORTABLE_POLICY_7_BIT 4
#define KEYMGR_DPE_METADATA_HIGH_7_RETAIN_PARENT_POLICY_7_BIT 5
 
// Key manager error code.
#define KEYMGR_DPE_ERR_CODE_REG_OFFSET 0x108
#define KEYMGR_DPE_ERR_CODE_REG_RESVAL 0x0u
#define KEYMGR_DPE_ERR_CODE_INVALID_OP_BIT 0
#define KEYMGR_DPE_ERR_CODE_INVALID_KMAC_INPUT_BIT 1
#define KEYMGR_DPE_ERR_CODE_INVALID_SHADOW_UPDATE_BIT 2
 
// This register represents both synchronous and asynchronous fatal faults.
#define KEYMGR_DPE_FAULT_STATUS_REG_OFFSET 0x10c
#define KEYMGR_DPE_FAULT_STATUS_REG_RESVAL 0x0u
#define KEYMGR_DPE_FAULT_STATUS_CMD_BIT 0
#define KEYMGR_DPE_FAULT_STATUS_KMAC_FSM_BIT 1
#define KEYMGR_DPE_FAULT_STATUS_KMAC_DONE_BIT 2
#define KEYMGR_DPE_FAULT_STATUS_KMAC_OP_BIT 3
#define KEYMGR_DPE_FAULT_STATUS_KMAC_OUT_BIT 4
#define KEYMGR_DPE_FAULT_STATUS_REGFILE_INTG_BIT 5
#define KEYMGR_DPE_FAULT_STATUS_SHADOW_BIT 6
#define KEYMGR_DPE_FAULT_STATUS_CTRL_FSM_INTG_BIT 7
#define KEYMGR_DPE_FAULT_STATUS_CTRL_FSM_CHK_BIT 8
#define KEYMGR_DPE_FAULT_STATUS_CTRL_FSM_CNT_BIT 9
#define KEYMGR_DPE_FAULT_STATUS_RESEED_CNT_BIT 10
#define KEYMGR_DPE_FAULT_STATUS_SIDE_CTRL_FSM_BIT 11
#define KEYMGR_DPE_FAULT_STATUS_SIDE_CTRL_SEL_BIT 12
#define KEYMGR_DPE_FAULT_STATUS_KEY_ECC_BIT 13
 
// The register holds some debug information that may be convenient if keymgr
#define KEYMGR_DPE_DEBUG_REG_OFFSET 0x110
#define KEYMGR_DPE_DEBUG_REG_RESVAL 0x0u
#define KEYMGR_DPE_DEBUG_INVALID_CREATOR_SEED_BIT 0
#define KEYMGR_DPE_DEBUG_INVALID_OWNER_SEED_BIT 1
#define KEYMGR_DPE_DEBUG_INVALID_DEV_ID_BIT 2
#define KEYMGR_DPE_DEBUG_INVALID_HEALTH_STATE_BIT 3
#define KEYMGR_DPE_DEBUG_INVALID_KEY_VERSION_BIT 4
#define KEYMGR_DPE_DEBUG_INVALID_KEY_BIT 5
#define KEYMGR_DPE_DEBUG_INVALID_DIGEST_BIT 6
#define KEYMGR_DPE_DEBUG_INVALID_ROOT_KEY_BIT 7
#define KEYMGR_DPE_DEBUG_INACTIVE_LC_EN_BIT 8
 
// Register write lock for the LOAD_KEY command
#define KEYMGR_DPE_LOAD_KEY_LOCK_REG_OFFSET 0x114
#define KEYMGR_DPE_LOAD_KEY_LOCK_REG_RESVAL 0x0u
#define KEYMGR_DPE_LOAD_KEY_LOCK_LOCK_BIT 0
 
// Enforce the software binding value as the only advance input message until
// the next reset
#define KEYMGR_DPE_ENFORCE_SW_BINDING_REG_OFFSET 0x118
#define KEYMGR_DPE_ENFORCE_SW_BINDING_REG_RESVAL 0x9u
#define KEYMGR_DPE_ENFORCE_SW_BINDING_ENFORCE_MASK 0xfu
#define KEYMGR_DPE_ENFORCE_SW_BINDING_ENFORCE_OFFSET 0
#define KEYMGR_DPE_ENFORCE_SW_BINDING_ENFORCE_FIELD \
  ((bitfield_field32_t) { .mask = KEYMGR_DPE_ENFORCE_SW_BINDING_ENFORCE_MASK, .index = KEYMGR_DPE_ENFORCE_SW_BINDING_ENFORCE_OFFSET })
 
#ifdef __cplusplus
}  // extern "C"
#endif
#endif  // _KEYMGR_DPE_REG_DEFS_
// End generated register defines for keymgr_dpe