gpio_regs.h

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/**
 * @file
 * @brief Generated register defines for gpio
 */
 
// Copyright information found in source file:
// Copyright lowRISC contributors (OpenTitan project).
 
// Licensing information found in source file:
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
 
#ifndef _GPIO_REG_DEFS_
#define _GPIO_REG_DEFS_
 
#ifdef __cplusplus
extern "C" {
#endif
// Number of I/Os.
#define GPIO_PARAM_NUM_I_OS 32
 
// Number of input period counters.
#define GPIO_PARAM_NUM_INP_PERIOD_COUNTERS 0
 
// Number of alerts
#define GPIO_PARAM_NUM_ALERTS 1
 
// Register width
#define GPIO_PARAM_REG_WIDTH 32
 
// Common Interrupt Offsets
 
// Interrupt State Register
#define GPIO_INTR_STATE_REG_OFFSET 0x0
#define GPIO_INTR_STATE_REG_RESVAL 0x0u
 
// Interrupt Enable Register
#define GPIO_INTR_ENABLE_REG_OFFSET 0x4
#define GPIO_INTR_ENABLE_REG_RESVAL 0x0u
 
// Interrupt Test Register
#define GPIO_INTR_TEST_REG_OFFSET 0x8
#define GPIO_INTR_TEST_REG_RESVAL 0x0u
 
// Alert Test Register
#define GPIO_ALERT_TEST_REG_OFFSET 0xc
#define GPIO_ALERT_TEST_REG_RESVAL 0x80000000u
#define GPIO_ALERT_TEST_FATAL_FAULT_BIT 0
#define GPIO_ALERT_TEST_REGWEN_BIT 31
 
// GPIO Input data read value
#define GPIO_DATA_IN_REG_OFFSET 0x10
#define GPIO_DATA_IN_REG_RESVAL 0x0u
 
// GPIO direct output data write value
#define GPIO_DIRECT_OUT_REG_OFFSET 0x14
#define GPIO_DIRECT_OUT_REG_RESVAL 0x0u
 
// GPIO write data lower with mask.
#define GPIO_MASKED_OUT_LOWER_REG_OFFSET 0x18
#define GPIO_MASKED_OUT_LOWER_REG_RESVAL 0x0u
#define GPIO_MASKED_OUT_LOWER_DATA_MASK 0xffffu
#define GPIO_MASKED_OUT_LOWER_DATA_OFFSET 0
#define GPIO_MASKED_OUT_LOWER_DATA_FIELD \
  ((bitfield_field32_t) { .mask = GPIO_MASKED_OUT_LOWER_DATA_MASK, .index = GPIO_MASKED_OUT_LOWER_DATA_OFFSET })
#define GPIO_MASKED_OUT_LOWER_MASK_MASK 0xffffu
#define GPIO_MASKED_OUT_LOWER_MASK_OFFSET 16
#define GPIO_MASKED_OUT_LOWER_MASK_FIELD \
  ((bitfield_field32_t) { .mask = GPIO_MASKED_OUT_LOWER_MASK_MASK, .index = GPIO_MASKED_OUT_LOWER_MASK_OFFSET })
 
// GPIO write data upper with mask.
#define GPIO_MASKED_OUT_UPPER_REG_OFFSET 0x1c
#define GPIO_MASKED_OUT_UPPER_REG_RESVAL 0x0u
#define GPIO_MASKED_OUT_UPPER_DATA_MASK 0xffffu
#define GPIO_MASKED_OUT_UPPER_DATA_OFFSET 0
#define GPIO_MASKED_OUT_UPPER_DATA_FIELD \
  ((bitfield_field32_t) { .mask = GPIO_MASKED_OUT_UPPER_DATA_MASK, .index = GPIO_MASKED_OUT_UPPER_DATA_OFFSET })
#define GPIO_MASKED_OUT_UPPER_MASK_MASK 0xffffu
#define GPIO_MASKED_OUT_UPPER_MASK_OFFSET 16
#define GPIO_MASKED_OUT_UPPER_MASK_FIELD \
  ((bitfield_field32_t) { .mask = GPIO_MASKED_OUT_UPPER_MASK_MASK, .index = GPIO_MASKED_OUT_UPPER_MASK_OFFSET })
 
// GPIO Output Enable.
#define GPIO_DIRECT_OE_REG_OFFSET 0x20
#define GPIO_DIRECT_OE_REG_RESVAL 0x0u
 
// GPIO write Output Enable lower with mask.
#define GPIO_MASKED_OE_LOWER_REG_OFFSET 0x24
#define GPIO_MASKED_OE_LOWER_REG_RESVAL 0x0u
#define GPIO_MASKED_OE_LOWER_DATA_MASK 0xffffu
#define GPIO_MASKED_OE_LOWER_DATA_OFFSET 0
#define GPIO_MASKED_OE_LOWER_DATA_FIELD \
  ((bitfield_field32_t) { .mask = GPIO_MASKED_OE_LOWER_DATA_MASK, .index = GPIO_MASKED_OE_LOWER_DATA_OFFSET })
#define GPIO_MASKED_OE_LOWER_MASK_MASK 0xffffu
#define GPIO_MASKED_OE_LOWER_MASK_OFFSET 16
#define GPIO_MASKED_OE_LOWER_MASK_FIELD \
  ((bitfield_field32_t) { .mask = GPIO_MASKED_OE_LOWER_MASK_MASK, .index = GPIO_MASKED_OE_LOWER_MASK_OFFSET })
 
// GPIO write Output Enable upper with mask.
#define GPIO_MASKED_OE_UPPER_REG_OFFSET 0x28
#define GPIO_MASKED_OE_UPPER_REG_RESVAL 0x0u
#define GPIO_MASKED_OE_UPPER_DATA_MASK 0xffffu
#define GPIO_MASKED_OE_UPPER_DATA_OFFSET 0
#define GPIO_MASKED_OE_UPPER_DATA_FIELD \
  ((bitfield_field32_t) { .mask = GPIO_MASKED_OE_UPPER_DATA_MASK, .index = GPIO_MASKED_OE_UPPER_DATA_OFFSET })
#define GPIO_MASKED_OE_UPPER_MASK_MASK 0xffffu
#define GPIO_MASKED_OE_UPPER_MASK_OFFSET 16
#define GPIO_MASKED_OE_UPPER_MASK_FIELD \
  ((bitfield_field32_t) { .mask = GPIO_MASKED_OE_UPPER_MASK_MASK, .index = GPIO_MASKED_OE_UPPER_MASK_OFFSET })
 
// GPIO interrupt enable for GPIO, rising edge.
#define GPIO_INTR_CTRL_EN_RISING_REG_OFFSET 0x2c
#define GPIO_INTR_CTRL_EN_RISING_REG_RESVAL 0x0u
 
// GPIO interrupt enable for GPIO, falling edge.
#define GPIO_INTR_CTRL_EN_FALLING_REG_OFFSET 0x30
#define GPIO_INTR_CTRL_EN_FALLING_REG_RESVAL 0x0u
 
// GPIO interrupt enable for GPIO, level high.
#define GPIO_INTR_CTRL_EN_LVLHIGH_REG_OFFSET 0x34
#define GPIO_INTR_CTRL_EN_LVLHIGH_REG_RESVAL 0x0u
 
// GPIO interrupt enable for GPIO, level low.
#define GPIO_INTR_CTRL_EN_LVLLOW_REG_OFFSET 0x38
#define GPIO_INTR_CTRL_EN_LVLLOW_REG_RESVAL 0x0u
 
// filter enable for GPIO input bits.
#define GPIO_CTRL_EN_INPUT_FILTER_REG_OFFSET 0x3c
#define GPIO_CTRL_EN_INPUT_FILTER_REG_RESVAL 0x0u
 
// Indicates whether the data in !!HW_STRAPS_DATA_IN is valid.
#define GPIO_HW_STRAPS_DATA_IN_VALID_REG_OFFSET 0x40
#define GPIO_HW_STRAPS_DATA_IN_VALID_REG_RESVAL 0x0u
#define GPIO_HW_STRAPS_DATA_IN_VALID_HW_STRAPS_DATA_IN_VALID_BIT 0
 
// GPIO input data that was sampled as straps at most once after the block
#define GPIO_HW_STRAPS_DATA_IN_REG_OFFSET 0x44
#define GPIO_HW_STRAPS_DATA_IN_REG_RESVAL 0x0u
 
// Per-pin view of the output and input data of one GPIO.
#define GPIO_PER_PIN_IO_DATA_OUT_FIELD_WIDTH 1
#define GPIO_PER_PIN_IO_DATA_IN_FIELD_WIDTH 1
#define GPIO_PER_PIN_IO_MULTIREG_COUNT 32
 
// Per-pin view of the output and input data of one GPIO.
#define GPIO_PER_PIN_IO_0_REG_OFFSET 0x100
#define GPIO_PER_PIN_IO_0_REG_RESVAL 0x0u
#define GPIO_PER_PIN_IO_0_DATA_OUT_0_BIT 0
#define GPIO_PER_PIN_IO_0_DATA_IN_0_BIT 8
 
// Per-pin view of the output and input data of one GPIO.
#define GPIO_PER_PIN_IO_1_REG_OFFSET 0x104
#define GPIO_PER_PIN_IO_1_REG_RESVAL 0x0u
#define GPIO_PER_PIN_IO_1_DATA_OUT_1_BIT 0
#define GPIO_PER_PIN_IO_1_DATA_IN_1_BIT 8
 
// Per-pin view of the output and input data of one GPIO.
#define GPIO_PER_PIN_IO_2_REG_OFFSET 0x108
#define GPIO_PER_PIN_IO_2_REG_RESVAL 0x0u
#define GPIO_PER_PIN_IO_2_DATA_OUT_2_BIT 0
#define GPIO_PER_PIN_IO_2_DATA_IN_2_BIT 8
 
// Per-pin view of the output and input data of one GPIO.
#define GPIO_PER_PIN_IO_3_REG_OFFSET 0x10c
#define GPIO_PER_PIN_IO_3_REG_RESVAL 0x0u
#define GPIO_PER_PIN_IO_3_DATA_OUT_3_BIT 0
#define GPIO_PER_PIN_IO_3_DATA_IN_3_BIT 8
 
// Per-pin view of the output and input data of one GPIO.
#define GPIO_PER_PIN_IO_4_REG_OFFSET 0x110
#define GPIO_PER_PIN_IO_4_REG_RESVAL 0x0u
#define GPIO_PER_PIN_IO_4_DATA_OUT_4_BIT 0
#define GPIO_PER_PIN_IO_4_DATA_IN_4_BIT 8
 
// Per-pin view of the output and input data of one GPIO.
#define GPIO_PER_PIN_IO_5_REG_OFFSET 0x114
#define GPIO_PER_PIN_IO_5_REG_RESVAL 0x0u
#define GPIO_PER_PIN_IO_5_DATA_OUT_5_BIT 0
#define GPIO_PER_PIN_IO_5_DATA_IN_5_BIT 8
 
// Per-pin view of the output and input data of one GPIO.
#define GPIO_PER_PIN_IO_6_REG_OFFSET 0x118
#define GPIO_PER_PIN_IO_6_REG_RESVAL 0x0u
#define GPIO_PER_PIN_IO_6_DATA_OUT_6_BIT 0
#define GPIO_PER_PIN_IO_6_DATA_IN_6_BIT 8
 
// Per-pin view of the output and input data of one GPIO.
#define GPIO_PER_PIN_IO_7_REG_OFFSET 0x11c
#define GPIO_PER_PIN_IO_7_REG_RESVAL 0x0u
#define GPIO_PER_PIN_IO_7_DATA_OUT_7_BIT 0
#define GPIO_PER_PIN_IO_7_DATA_IN_7_BIT 8
 
// Per-pin view of the output and input data of one GPIO.
#define GPIO_PER_PIN_IO_8_REG_OFFSET 0x120
#define GPIO_PER_PIN_IO_8_REG_RESVAL 0x0u
#define GPIO_PER_PIN_IO_8_DATA_OUT_8_BIT 0
#define GPIO_PER_PIN_IO_8_DATA_IN_8_BIT 8
 
// Per-pin view of the output and input data of one GPIO.
#define GPIO_PER_PIN_IO_9_REG_OFFSET 0x124
#define GPIO_PER_PIN_IO_9_REG_RESVAL 0x0u
#define GPIO_PER_PIN_IO_9_DATA_OUT_9_BIT 0
#define GPIO_PER_PIN_IO_9_DATA_IN_9_BIT 8
 
// Per-pin view of the output and input data of one GPIO.
#define GPIO_PER_PIN_IO_10_REG_OFFSET 0x128
#define GPIO_PER_PIN_IO_10_REG_RESVAL 0x0u
#define GPIO_PER_PIN_IO_10_DATA_OUT_10_BIT 0
#define GPIO_PER_PIN_IO_10_DATA_IN_10_BIT 8
 
// Per-pin view of the output and input data of one GPIO.
#define GPIO_PER_PIN_IO_11_REG_OFFSET 0x12c
#define GPIO_PER_PIN_IO_11_REG_RESVAL 0x0u
#define GPIO_PER_PIN_IO_11_DATA_OUT_11_BIT 0
#define GPIO_PER_PIN_IO_11_DATA_IN_11_BIT 8
 
// Per-pin view of the output and input data of one GPIO.
#define GPIO_PER_PIN_IO_12_REG_OFFSET 0x130
#define GPIO_PER_PIN_IO_12_REG_RESVAL 0x0u
#define GPIO_PER_PIN_IO_12_DATA_OUT_12_BIT 0
#define GPIO_PER_PIN_IO_12_DATA_IN_12_BIT 8
 
// Per-pin view of the output and input data of one GPIO.
#define GPIO_PER_PIN_IO_13_REG_OFFSET 0x134
#define GPIO_PER_PIN_IO_13_REG_RESVAL 0x0u
#define GPIO_PER_PIN_IO_13_DATA_OUT_13_BIT 0
#define GPIO_PER_PIN_IO_13_DATA_IN_13_BIT 8
 
// Per-pin view of the output and input data of one GPIO.
#define GPIO_PER_PIN_IO_14_REG_OFFSET 0x138
#define GPIO_PER_PIN_IO_14_REG_RESVAL 0x0u
#define GPIO_PER_PIN_IO_14_DATA_OUT_14_BIT 0
#define GPIO_PER_PIN_IO_14_DATA_IN_14_BIT 8
 
// Per-pin view of the output and input data of one GPIO.
#define GPIO_PER_PIN_IO_15_REG_OFFSET 0x13c
#define GPIO_PER_PIN_IO_15_REG_RESVAL 0x0u
#define GPIO_PER_PIN_IO_15_DATA_OUT_15_BIT 0
#define GPIO_PER_PIN_IO_15_DATA_IN_15_BIT 8
 
// Per-pin view of the output and input data of one GPIO.
#define GPIO_PER_PIN_IO_16_REG_OFFSET 0x140
#define GPIO_PER_PIN_IO_16_REG_RESVAL 0x0u
#define GPIO_PER_PIN_IO_16_DATA_OUT_16_BIT 0
#define GPIO_PER_PIN_IO_16_DATA_IN_16_BIT 8
 
// Per-pin view of the output and input data of one GPIO.
#define GPIO_PER_PIN_IO_17_REG_OFFSET 0x144
#define GPIO_PER_PIN_IO_17_REG_RESVAL 0x0u
#define GPIO_PER_PIN_IO_17_DATA_OUT_17_BIT 0
#define GPIO_PER_PIN_IO_17_DATA_IN_17_BIT 8
 
// Per-pin view of the output and input data of one GPIO.
#define GPIO_PER_PIN_IO_18_REG_OFFSET 0x148
#define GPIO_PER_PIN_IO_18_REG_RESVAL 0x0u
#define GPIO_PER_PIN_IO_18_DATA_OUT_18_BIT 0
#define GPIO_PER_PIN_IO_18_DATA_IN_18_BIT 8
 
// Per-pin view of the output and input data of one GPIO.
#define GPIO_PER_PIN_IO_19_REG_OFFSET 0x14c
#define GPIO_PER_PIN_IO_19_REG_RESVAL 0x0u
#define GPIO_PER_PIN_IO_19_DATA_OUT_19_BIT 0
#define GPIO_PER_PIN_IO_19_DATA_IN_19_BIT 8
 
// Per-pin view of the output and input data of one GPIO.
#define GPIO_PER_PIN_IO_20_REG_OFFSET 0x150
#define GPIO_PER_PIN_IO_20_REG_RESVAL 0x0u
#define GPIO_PER_PIN_IO_20_DATA_OUT_20_BIT 0
#define GPIO_PER_PIN_IO_20_DATA_IN_20_BIT 8
 
// Per-pin view of the output and input data of one GPIO.
#define GPIO_PER_PIN_IO_21_REG_OFFSET 0x154
#define GPIO_PER_PIN_IO_21_REG_RESVAL 0x0u
#define GPIO_PER_PIN_IO_21_DATA_OUT_21_BIT 0
#define GPIO_PER_PIN_IO_21_DATA_IN_21_BIT 8
 
// Per-pin view of the output and input data of one GPIO.
#define GPIO_PER_PIN_IO_22_REG_OFFSET 0x158
#define GPIO_PER_PIN_IO_22_REG_RESVAL 0x0u
#define GPIO_PER_PIN_IO_22_DATA_OUT_22_BIT 0
#define GPIO_PER_PIN_IO_22_DATA_IN_22_BIT 8
 
// Per-pin view of the output and input data of one GPIO.
#define GPIO_PER_PIN_IO_23_REG_OFFSET 0x15c
#define GPIO_PER_PIN_IO_23_REG_RESVAL 0x0u
#define GPIO_PER_PIN_IO_23_DATA_OUT_23_BIT 0
#define GPIO_PER_PIN_IO_23_DATA_IN_23_BIT 8
 
// Per-pin view of the output and input data of one GPIO.
#define GPIO_PER_PIN_IO_24_REG_OFFSET 0x160
#define GPIO_PER_PIN_IO_24_REG_RESVAL 0x0u
#define GPIO_PER_PIN_IO_24_DATA_OUT_24_BIT 0
#define GPIO_PER_PIN_IO_24_DATA_IN_24_BIT 8
 
// Per-pin view of the output and input data of one GPIO.
#define GPIO_PER_PIN_IO_25_REG_OFFSET 0x164
#define GPIO_PER_PIN_IO_25_REG_RESVAL 0x0u
#define GPIO_PER_PIN_IO_25_DATA_OUT_25_BIT 0
#define GPIO_PER_PIN_IO_25_DATA_IN_25_BIT 8
 
// Per-pin view of the output and input data of one GPIO.
#define GPIO_PER_PIN_IO_26_REG_OFFSET 0x168
#define GPIO_PER_PIN_IO_26_REG_RESVAL 0x0u
#define GPIO_PER_PIN_IO_26_DATA_OUT_26_BIT 0
#define GPIO_PER_PIN_IO_26_DATA_IN_26_BIT 8
 
// Per-pin view of the output and input data of one GPIO.
#define GPIO_PER_PIN_IO_27_REG_OFFSET 0x16c
#define GPIO_PER_PIN_IO_27_REG_RESVAL 0x0u
#define GPIO_PER_PIN_IO_27_DATA_OUT_27_BIT 0
#define GPIO_PER_PIN_IO_27_DATA_IN_27_BIT 8
 
// Per-pin view of the output and input data of one GPIO.
#define GPIO_PER_PIN_IO_28_REG_OFFSET 0x170
#define GPIO_PER_PIN_IO_28_REG_RESVAL 0x0u
#define GPIO_PER_PIN_IO_28_DATA_OUT_28_BIT 0
#define GPIO_PER_PIN_IO_28_DATA_IN_28_BIT 8
 
// Per-pin view of the output and input data of one GPIO.
#define GPIO_PER_PIN_IO_29_REG_OFFSET 0x174
#define GPIO_PER_PIN_IO_29_REG_RESVAL 0x0u
#define GPIO_PER_PIN_IO_29_DATA_OUT_29_BIT 0
#define GPIO_PER_PIN_IO_29_DATA_IN_29_BIT 8
 
// Per-pin view of the output and input data of one GPIO.
#define GPIO_PER_PIN_IO_30_REG_OFFSET 0x178
#define GPIO_PER_PIN_IO_30_REG_RESVAL 0x0u
#define GPIO_PER_PIN_IO_30_DATA_OUT_30_BIT 0
#define GPIO_PER_PIN_IO_30_DATA_IN_30_BIT 8
 
// Per-pin view of the output and input data of one GPIO.
#define GPIO_PER_PIN_IO_31_REG_OFFSET 0x17c
#define GPIO_PER_PIN_IO_31_REG_RESVAL 0x0u
#define GPIO_PER_PIN_IO_31_DATA_OUT_31_BIT 0
#define GPIO_PER_PIN_IO_31_DATA_IN_31_BIT 8
 
// Per-pin view of the output enable of GPIO[0].
#define GPIO_PER_PIN_OE_0_REG_OFFSET 0x200
#define GPIO_PER_PIN_OE_0_REG_RESVAL 0x0u
#define GPIO_PER_PIN_OE_0_OE_BIT 0
 
// Per-pin view of the interrupt control and input filter configuration of
// GPIO[0].
#define GPIO_PER_PIN_INTR_CTRL_0_REG_OFFSET 0x204
#define GPIO_PER_PIN_INTR_CTRL_0_REG_RESVAL 0x0u
#define GPIO_PER_PIN_INTR_CTRL_0_INTR_CTRL_EN_RISING_BIT 0
#define GPIO_PER_PIN_INTR_CTRL_0_INTR_CTRL_EN_FALLING_BIT 1
#define GPIO_PER_PIN_INTR_CTRL_0_INTR_CTRL_EN_LVLHIGH_BIT 2
#define GPIO_PER_PIN_INTR_CTRL_0_INTR_CTRL_EN_LVLLOW_BIT 3
#define GPIO_PER_PIN_INTR_CTRL_0_CTRL_EN_INPUT_FILTER_BIT 4
 
// Per-pin view of the output enable of GPIO[1].
#define GPIO_PER_PIN_OE_1_REG_OFFSET 0x208
#define GPIO_PER_PIN_OE_1_REG_RESVAL 0x0u
#define GPIO_PER_PIN_OE_1_OE_BIT 0
 
// Per-pin view of the interrupt control and input filter configuration of
// GPIO[1].
#define GPIO_PER_PIN_INTR_CTRL_1_REG_OFFSET 0x20c
#define GPIO_PER_PIN_INTR_CTRL_1_REG_RESVAL 0x0u
#define GPIO_PER_PIN_INTR_CTRL_1_INTR_CTRL_EN_RISING_BIT 0
#define GPIO_PER_PIN_INTR_CTRL_1_INTR_CTRL_EN_FALLING_BIT 1
#define GPIO_PER_PIN_INTR_CTRL_1_INTR_CTRL_EN_LVLHIGH_BIT 2
#define GPIO_PER_PIN_INTR_CTRL_1_INTR_CTRL_EN_LVLLOW_BIT 3
#define GPIO_PER_PIN_INTR_CTRL_1_CTRL_EN_INPUT_FILTER_BIT 4
 
// Per-pin view of the output enable of GPIO[2].
#define GPIO_PER_PIN_OE_2_REG_OFFSET 0x210
#define GPIO_PER_PIN_OE_2_REG_RESVAL 0x0u
#define GPIO_PER_PIN_OE_2_OE_BIT 0
 
// Per-pin view of the interrupt control and input filter configuration of
// GPIO[2].
#define GPIO_PER_PIN_INTR_CTRL_2_REG_OFFSET 0x214
#define GPIO_PER_PIN_INTR_CTRL_2_REG_RESVAL 0x0u
#define GPIO_PER_PIN_INTR_CTRL_2_INTR_CTRL_EN_RISING_BIT 0
#define GPIO_PER_PIN_INTR_CTRL_2_INTR_CTRL_EN_FALLING_BIT 1
#define GPIO_PER_PIN_INTR_CTRL_2_INTR_CTRL_EN_LVLHIGH_BIT 2
#define GPIO_PER_PIN_INTR_CTRL_2_INTR_CTRL_EN_LVLLOW_BIT 3
#define GPIO_PER_PIN_INTR_CTRL_2_CTRL_EN_INPUT_FILTER_BIT 4
 
// Per-pin view of the output enable of GPIO[3].
#define GPIO_PER_PIN_OE_3_REG_OFFSET 0x218
#define GPIO_PER_PIN_OE_3_REG_RESVAL 0x0u
#define GPIO_PER_PIN_OE_3_OE_BIT 0
 
// Per-pin view of the interrupt control and input filter configuration of
// GPIO[3].
#define GPIO_PER_PIN_INTR_CTRL_3_REG_OFFSET 0x21c
#define GPIO_PER_PIN_INTR_CTRL_3_REG_RESVAL 0x0u
#define GPIO_PER_PIN_INTR_CTRL_3_INTR_CTRL_EN_RISING_BIT 0
#define GPIO_PER_PIN_INTR_CTRL_3_INTR_CTRL_EN_FALLING_BIT 1
#define GPIO_PER_PIN_INTR_CTRL_3_INTR_CTRL_EN_LVLHIGH_BIT 2
#define GPIO_PER_PIN_INTR_CTRL_3_INTR_CTRL_EN_LVLLOW_BIT 3
#define GPIO_PER_PIN_INTR_CTRL_3_CTRL_EN_INPUT_FILTER_BIT 4
 
// Per-pin view of the output enable of GPIO[4].
#define GPIO_PER_PIN_OE_4_REG_OFFSET 0x220
#define GPIO_PER_PIN_OE_4_REG_RESVAL 0x0u
#define GPIO_PER_PIN_OE_4_OE_BIT 0
 
// Per-pin view of the interrupt control and input filter configuration of
// GPIO[4].
#define GPIO_PER_PIN_INTR_CTRL_4_REG_OFFSET 0x224
#define GPIO_PER_PIN_INTR_CTRL_4_REG_RESVAL 0x0u
#define GPIO_PER_PIN_INTR_CTRL_4_INTR_CTRL_EN_RISING_BIT 0
#define GPIO_PER_PIN_INTR_CTRL_4_INTR_CTRL_EN_FALLING_BIT 1
#define GPIO_PER_PIN_INTR_CTRL_4_INTR_CTRL_EN_LVLHIGH_BIT 2
#define GPIO_PER_PIN_INTR_CTRL_4_INTR_CTRL_EN_LVLLOW_BIT 3
#define GPIO_PER_PIN_INTR_CTRL_4_CTRL_EN_INPUT_FILTER_BIT 4
 
// Per-pin view of the output enable of GPIO[5].
#define GPIO_PER_PIN_OE_5_REG_OFFSET 0x228
#define GPIO_PER_PIN_OE_5_REG_RESVAL 0x0u
#define GPIO_PER_PIN_OE_5_OE_BIT 0
 
// Per-pin view of the interrupt control and input filter configuration of
// GPIO[5].
#define GPIO_PER_PIN_INTR_CTRL_5_REG_OFFSET 0x22c
#define GPIO_PER_PIN_INTR_CTRL_5_REG_RESVAL 0x0u
#define GPIO_PER_PIN_INTR_CTRL_5_INTR_CTRL_EN_RISING_BIT 0
#define GPIO_PER_PIN_INTR_CTRL_5_INTR_CTRL_EN_FALLING_BIT 1
#define GPIO_PER_PIN_INTR_CTRL_5_INTR_CTRL_EN_LVLHIGH_BIT 2
#define GPIO_PER_PIN_INTR_CTRL_5_INTR_CTRL_EN_LVLLOW_BIT 3
#define GPIO_PER_PIN_INTR_CTRL_5_CTRL_EN_INPUT_FILTER_BIT 4
 
// Per-pin view of the output enable of GPIO[6].
#define GPIO_PER_PIN_OE_6_REG_OFFSET 0x230
#define GPIO_PER_PIN_OE_6_REG_RESVAL 0x0u
#define GPIO_PER_PIN_OE_6_OE_BIT 0
 
// Per-pin view of the interrupt control and input filter configuration of
// GPIO[6].
#define GPIO_PER_PIN_INTR_CTRL_6_REG_OFFSET 0x234
#define GPIO_PER_PIN_INTR_CTRL_6_REG_RESVAL 0x0u
#define GPIO_PER_PIN_INTR_CTRL_6_INTR_CTRL_EN_RISING_BIT 0
#define GPIO_PER_PIN_INTR_CTRL_6_INTR_CTRL_EN_FALLING_BIT 1
#define GPIO_PER_PIN_INTR_CTRL_6_INTR_CTRL_EN_LVLHIGH_BIT 2
#define GPIO_PER_PIN_INTR_CTRL_6_INTR_CTRL_EN_LVLLOW_BIT 3
#define GPIO_PER_PIN_INTR_CTRL_6_CTRL_EN_INPUT_FILTER_BIT 4
 
// Per-pin view of the output enable of GPIO[7].
#define GPIO_PER_PIN_OE_7_REG_OFFSET 0x238
#define GPIO_PER_PIN_OE_7_REG_RESVAL 0x0u
#define GPIO_PER_PIN_OE_7_OE_BIT 0
 
// Per-pin view of the interrupt control and input filter configuration of
// GPIO[7].
#define GPIO_PER_PIN_INTR_CTRL_7_REG_OFFSET 0x23c
#define GPIO_PER_PIN_INTR_CTRL_7_REG_RESVAL 0x0u
#define GPIO_PER_PIN_INTR_CTRL_7_INTR_CTRL_EN_RISING_BIT 0
#define GPIO_PER_PIN_INTR_CTRL_7_INTR_CTRL_EN_FALLING_BIT 1
#define GPIO_PER_PIN_INTR_CTRL_7_INTR_CTRL_EN_LVLHIGH_BIT 2
#define GPIO_PER_PIN_INTR_CTRL_7_INTR_CTRL_EN_LVLLOW_BIT 3
#define GPIO_PER_PIN_INTR_CTRL_7_CTRL_EN_INPUT_FILTER_BIT 4
 
// Per-pin view of the output enable of GPIO[8].
#define GPIO_PER_PIN_OE_8_REG_OFFSET 0x240
#define GPIO_PER_PIN_OE_8_REG_RESVAL 0x0u
#define GPIO_PER_PIN_OE_8_OE_BIT 0
 
// Per-pin view of the interrupt control and input filter configuration of
// GPIO[8].
#define GPIO_PER_PIN_INTR_CTRL_8_REG_OFFSET 0x244
#define GPIO_PER_PIN_INTR_CTRL_8_REG_RESVAL 0x0u
#define GPIO_PER_PIN_INTR_CTRL_8_INTR_CTRL_EN_RISING_BIT 0
#define GPIO_PER_PIN_INTR_CTRL_8_INTR_CTRL_EN_FALLING_BIT 1
#define GPIO_PER_PIN_INTR_CTRL_8_INTR_CTRL_EN_LVLHIGH_BIT 2
#define GPIO_PER_PIN_INTR_CTRL_8_INTR_CTRL_EN_LVLLOW_BIT 3
#define GPIO_PER_PIN_INTR_CTRL_8_CTRL_EN_INPUT_FILTER_BIT 4
 
// Per-pin view of the output enable of GPIO[9].
#define GPIO_PER_PIN_OE_9_REG_OFFSET 0x248
#define GPIO_PER_PIN_OE_9_REG_RESVAL 0x0u
#define GPIO_PER_PIN_OE_9_OE_BIT 0
 
// Per-pin view of the interrupt control and input filter configuration of
// GPIO[9].
#define GPIO_PER_PIN_INTR_CTRL_9_REG_OFFSET 0x24c
#define GPIO_PER_PIN_INTR_CTRL_9_REG_RESVAL 0x0u
#define GPIO_PER_PIN_INTR_CTRL_9_INTR_CTRL_EN_RISING_BIT 0
#define GPIO_PER_PIN_INTR_CTRL_9_INTR_CTRL_EN_FALLING_BIT 1
#define GPIO_PER_PIN_INTR_CTRL_9_INTR_CTRL_EN_LVLHIGH_BIT 2
#define GPIO_PER_PIN_INTR_CTRL_9_INTR_CTRL_EN_LVLLOW_BIT 3
#define GPIO_PER_PIN_INTR_CTRL_9_CTRL_EN_INPUT_FILTER_BIT 4
 
// Per-pin view of the output enable of GPIO[10].
#define GPIO_PER_PIN_OE_10_REG_OFFSET 0x250
#define GPIO_PER_PIN_OE_10_REG_RESVAL 0x0u
#define GPIO_PER_PIN_OE_10_OE_BIT 0
 
// Per-pin view of the interrupt control and input filter configuration of
// GPIO[10].
#define GPIO_PER_PIN_INTR_CTRL_10_REG_OFFSET 0x254
#define GPIO_PER_PIN_INTR_CTRL_10_REG_RESVAL 0x0u
#define GPIO_PER_PIN_INTR_CTRL_10_INTR_CTRL_EN_RISING_BIT 0
#define GPIO_PER_PIN_INTR_CTRL_10_INTR_CTRL_EN_FALLING_BIT 1
#define GPIO_PER_PIN_INTR_CTRL_10_INTR_CTRL_EN_LVLHIGH_BIT 2
#define GPIO_PER_PIN_INTR_CTRL_10_INTR_CTRL_EN_LVLLOW_BIT 3
#define GPIO_PER_PIN_INTR_CTRL_10_CTRL_EN_INPUT_FILTER_BIT 4
 
// Per-pin view of the output enable of GPIO[11].
#define GPIO_PER_PIN_OE_11_REG_OFFSET 0x258
#define GPIO_PER_PIN_OE_11_REG_RESVAL 0x0u
#define GPIO_PER_PIN_OE_11_OE_BIT 0
 
// Per-pin view of the interrupt control and input filter configuration of
// GPIO[11].
#define GPIO_PER_PIN_INTR_CTRL_11_REG_OFFSET 0x25c
#define GPIO_PER_PIN_INTR_CTRL_11_REG_RESVAL 0x0u
#define GPIO_PER_PIN_INTR_CTRL_11_INTR_CTRL_EN_RISING_BIT 0
#define GPIO_PER_PIN_INTR_CTRL_11_INTR_CTRL_EN_FALLING_BIT 1
#define GPIO_PER_PIN_INTR_CTRL_11_INTR_CTRL_EN_LVLHIGH_BIT 2
#define GPIO_PER_PIN_INTR_CTRL_11_INTR_CTRL_EN_LVLLOW_BIT 3
#define GPIO_PER_PIN_INTR_CTRL_11_CTRL_EN_INPUT_FILTER_BIT 4
 
// Per-pin view of the output enable of GPIO[12].
#define GPIO_PER_PIN_OE_12_REG_OFFSET 0x260
#define GPIO_PER_PIN_OE_12_REG_RESVAL 0x0u
#define GPIO_PER_PIN_OE_12_OE_BIT 0
 
// Per-pin view of the interrupt control and input filter configuration of
// GPIO[12].
#define GPIO_PER_PIN_INTR_CTRL_12_REG_OFFSET 0x264
#define GPIO_PER_PIN_INTR_CTRL_12_REG_RESVAL 0x0u
#define GPIO_PER_PIN_INTR_CTRL_12_INTR_CTRL_EN_RISING_BIT 0
#define GPIO_PER_PIN_INTR_CTRL_12_INTR_CTRL_EN_FALLING_BIT 1
#define GPIO_PER_PIN_INTR_CTRL_12_INTR_CTRL_EN_LVLHIGH_BIT 2
#define GPIO_PER_PIN_INTR_CTRL_12_INTR_CTRL_EN_LVLLOW_BIT 3
#define GPIO_PER_PIN_INTR_CTRL_12_CTRL_EN_INPUT_FILTER_BIT 4
 
// Per-pin view of the output enable of GPIO[13].
#define GPIO_PER_PIN_OE_13_REG_OFFSET 0x268
#define GPIO_PER_PIN_OE_13_REG_RESVAL 0x0u
#define GPIO_PER_PIN_OE_13_OE_BIT 0
 
// Per-pin view of the interrupt control and input filter configuration of
// GPIO[13].
#define GPIO_PER_PIN_INTR_CTRL_13_REG_OFFSET 0x26c
#define GPIO_PER_PIN_INTR_CTRL_13_REG_RESVAL 0x0u
#define GPIO_PER_PIN_INTR_CTRL_13_INTR_CTRL_EN_RISING_BIT 0
#define GPIO_PER_PIN_INTR_CTRL_13_INTR_CTRL_EN_FALLING_BIT 1
#define GPIO_PER_PIN_INTR_CTRL_13_INTR_CTRL_EN_LVLHIGH_BIT 2
#define GPIO_PER_PIN_INTR_CTRL_13_INTR_CTRL_EN_LVLLOW_BIT 3
#define GPIO_PER_PIN_INTR_CTRL_13_CTRL_EN_INPUT_FILTER_BIT 4
 
// Per-pin view of the output enable of GPIO[14].
#define GPIO_PER_PIN_OE_14_REG_OFFSET 0x270
#define GPIO_PER_PIN_OE_14_REG_RESVAL 0x0u
#define GPIO_PER_PIN_OE_14_OE_BIT 0
 
// Per-pin view of the interrupt control and input filter configuration of
// GPIO[14].
#define GPIO_PER_PIN_INTR_CTRL_14_REG_OFFSET 0x274
#define GPIO_PER_PIN_INTR_CTRL_14_REG_RESVAL 0x0u
#define GPIO_PER_PIN_INTR_CTRL_14_INTR_CTRL_EN_RISING_BIT 0
#define GPIO_PER_PIN_INTR_CTRL_14_INTR_CTRL_EN_FALLING_BIT 1
#define GPIO_PER_PIN_INTR_CTRL_14_INTR_CTRL_EN_LVLHIGH_BIT 2
#define GPIO_PER_PIN_INTR_CTRL_14_INTR_CTRL_EN_LVLLOW_BIT 3
#define GPIO_PER_PIN_INTR_CTRL_14_CTRL_EN_INPUT_FILTER_BIT 4
 
// Per-pin view of the output enable of GPIO[15].
#define GPIO_PER_PIN_OE_15_REG_OFFSET 0x278
#define GPIO_PER_PIN_OE_15_REG_RESVAL 0x0u
#define GPIO_PER_PIN_OE_15_OE_BIT 0
 
// Per-pin view of the interrupt control and input filter configuration of
// GPIO[15].
#define GPIO_PER_PIN_INTR_CTRL_15_REG_OFFSET 0x27c
#define GPIO_PER_PIN_INTR_CTRL_15_REG_RESVAL 0x0u
#define GPIO_PER_PIN_INTR_CTRL_15_INTR_CTRL_EN_RISING_BIT 0
#define GPIO_PER_PIN_INTR_CTRL_15_INTR_CTRL_EN_FALLING_BIT 1
#define GPIO_PER_PIN_INTR_CTRL_15_INTR_CTRL_EN_LVLHIGH_BIT 2
#define GPIO_PER_PIN_INTR_CTRL_15_INTR_CTRL_EN_LVLLOW_BIT 3
#define GPIO_PER_PIN_INTR_CTRL_15_CTRL_EN_INPUT_FILTER_BIT 4
 
// Per-pin view of the output enable of GPIO[16].
#define GPIO_PER_PIN_OE_16_REG_OFFSET 0x280
#define GPIO_PER_PIN_OE_16_REG_RESVAL 0x0u
#define GPIO_PER_PIN_OE_16_OE_BIT 0
 
// Per-pin view of the interrupt control and input filter configuration of
// GPIO[16].
#define GPIO_PER_PIN_INTR_CTRL_16_REG_OFFSET 0x284
#define GPIO_PER_PIN_INTR_CTRL_16_REG_RESVAL 0x0u
#define GPIO_PER_PIN_INTR_CTRL_16_INTR_CTRL_EN_RISING_BIT 0
#define GPIO_PER_PIN_INTR_CTRL_16_INTR_CTRL_EN_FALLING_BIT 1
#define GPIO_PER_PIN_INTR_CTRL_16_INTR_CTRL_EN_LVLHIGH_BIT 2
#define GPIO_PER_PIN_INTR_CTRL_16_INTR_CTRL_EN_LVLLOW_BIT 3
#define GPIO_PER_PIN_INTR_CTRL_16_CTRL_EN_INPUT_FILTER_BIT 4
 
// Per-pin view of the output enable of GPIO[17].
#define GPIO_PER_PIN_OE_17_REG_OFFSET 0x288
#define GPIO_PER_PIN_OE_17_REG_RESVAL 0x0u
#define GPIO_PER_PIN_OE_17_OE_BIT 0
 
// Per-pin view of the interrupt control and input filter configuration of
// GPIO[17].
#define GPIO_PER_PIN_INTR_CTRL_17_REG_OFFSET 0x28c
#define GPIO_PER_PIN_INTR_CTRL_17_REG_RESVAL 0x0u
#define GPIO_PER_PIN_INTR_CTRL_17_INTR_CTRL_EN_RISING_BIT 0
#define GPIO_PER_PIN_INTR_CTRL_17_INTR_CTRL_EN_FALLING_BIT 1
#define GPIO_PER_PIN_INTR_CTRL_17_INTR_CTRL_EN_LVLHIGH_BIT 2
#define GPIO_PER_PIN_INTR_CTRL_17_INTR_CTRL_EN_LVLLOW_BIT 3
#define GPIO_PER_PIN_INTR_CTRL_17_CTRL_EN_INPUT_FILTER_BIT 4
 
// Per-pin view of the output enable of GPIO[18].
#define GPIO_PER_PIN_OE_18_REG_OFFSET 0x290
#define GPIO_PER_PIN_OE_18_REG_RESVAL 0x0u
#define GPIO_PER_PIN_OE_18_OE_BIT 0
 
// Per-pin view of the interrupt control and input filter configuration of
// GPIO[18].
#define GPIO_PER_PIN_INTR_CTRL_18_REG_OFFSET 0x294
#define GPIO_PER_PIN_INTR_CTRL_18_REG_RESVAL 0x0u
#define GPIO_PER_PIN_INTR_CTRL_18_INTR_CTRL_EN_RISING_BIT 0
#define GPIO_PER_PIN_INTR_CTRL_18_INTR_CTRL_EN_FALLING_BIT 1
#define GPIO_PER_PIN_INTR_CTRL_18_INTR_CTRL_EN_LVLHIGH_BIT 2
#define GPIO_PER_PIN_INTR_CTRL_18_INTR_CTRL_EN_LVLLOW_BIT 3
#define GPIO_PER_PIN_INTR_CTRL_18_CTRL_EN_INPUT_FILTER_BIT 4
 
// Per-pin view of the output enable of GPIO[19].
#define GPIO_PER_PIN_OE_19_REG_OFFSET 0x298
#define GPIO_PER_PIN_OE_19_REG_RESVAL 0x0u
#define GPIO_PER_PIN_OE_19_OE_BIT 0
 
// Per-pin view of the interrupt control and input filter configuration of
// GPIO[19].
#define GPIO_PER_PIN_INTR_CTRL_19_REG_OFFSET 0x29c
#define GPIO_PER_PIN_INTR_CTRL_19_REG_RESVAL 0x0u
#define GPIO_PER_PIN_INTR_CTRL_19_INTR_CTRL_EN_RISING_BIT 0
#define GPIO_PER_PIN_INTR_CTRL_19_INTR_CTRL_EN_FALLING_BIT 1
#define GPIO_PER_PIN_INTR_CTRL_19_INTR_CTRL_EN_LVLHIGH_BIT 2
#define GPIO_PER_PIN_INTR_CTRL_19_INTR_CTRL_EN_LVLLOW_BIT 3
#define GPIO_PER_PIN_INTR_CTRL_19_CTRL_EN_INPUT_FILTER_BIT 4
 
// Per-pin view of the output enable of GPIO[20].
#define GPIO_PER_PIN_OE_20_REG_OFFSET 0x2a0
#define GPIO_PER_PIN_OE_20_REG_RESVAL 0x0u
#define GPIO_PER_PIN_OE_20_OE_BIT 0
 
// Per-pin view of the interrupt control and input filter configuration of
// GPIO[20].
#define GPIO_PER_PIN_INTR_CTRL_20_REG_OFFSET 0x2a4
#define GPIO_PER_PIN_INTR_CTRL_20_REG_RESVAL 0x0u
#define GPIO_PER_PIN_INTR_CTRL_20_INTR_CTRL_EN_RISING_BIT 0
#define GPIO_PER_PIN_INTR_CTRL_20_INTR_CTRL_EN_FALLING_BIT 1
#define GPIO_PER_PIN_INTR_CTRL_20_INTR_CTRL_EN_LVLHIGH_BIT 2
#define GPIO_PER_PIN_INTR_CTRL_20_INTR_CTRL_EN_LVLLOW_BIT 3
#define GPIO_PER_PIN_INTR_CTRL_20_CTRL_EN_INPUT_FILTER_BIT 4
 
// Per-pin view of the output enable of GPIO[21].
#define GPIO_PER_PIN_OE_21_REG_OFFSET 0x2a8
#define GPIO_PER_PIN_OE_21_REG_RESVAL 0x0u
#define GPIO_PER_PIN_OE_21_OE_BIT 0
 
// Per-pin view of the interrupt control and input filter configuration of
// GPIO[21].
#define GPIO_PER_PIN_INTR_CTRL_21_REG_OFFSET 0x2ac
#define GPIO_PER_PIN_INTR_CTRL_21_REG_RESVAL 0x0u
#define GPIO_PER_PIN_INTR_CTRL_21_INTR_CTRL_EN_RISING_BIT 0
#define GPIO_PER_PIN_INTR_CTRL_21_INTR_CTRL_EN_FALLING_BIT 1
#define GPIO_PER_PIN_INTR_CTRL_21_INTR_CTRL_EN_LVLHIGH_BIT 2
#define GPIO_PER_PIN_INTR_CTRL_21_INTR_CTRL_EN_LVLLOW_BIT 3
#define GPIO_PER_PIN_INTR_CTRL_21_CTRL_EN_INPUT_FILTER_BIT 4
 
// Per-pin view of the output enable of GPIO[22].
#define GPIO_PER_PIN_OE_22_REG_OFFSET 0x2b0
#define GPIO_PER_PIN_OE_22_REG_RESVAL 0x0u
#define GPIO_PER_PIN_OE_22_OE_BIT 0
 
// Per-pin view of the interrupt control and input filter configuration of
// GPIO[22].
#define GPIO_PER_PIN_INTR_CTRL_22_REG_OFFSET 0x2b4
#define GPIO_PER_PIN_INTR_CTRL_22_REG_RESVAL 0x0u
#define GPIO_PER_PIN_INTR_CTRL_22_INTR_CTRL_EN_RISING_BIT 0
#define GPIO_PER_PIN_INTR_CTRL_22_INTR_CTRL_EN_FALLING_BIT 1
#define GPIO_PER_PIN_INTR_CTRL_22_INTR_CTRL_EN_LVLHIGH_BIT 2
#define GPIO_PER_PIN_INTR_CTRL_22_INTR_CTRL_EN_LVLLOW_BIT 3
#define GPIO_PER_PIN_INTR_CTRL_22_CTRL_EN_INPUT_FILTER_BIT 4
 
// Per-pin view of the output enable of GPIO[23].
#define GPIO_PER_PIN_OE_23_REG_OFFSET 0x2b8
#define GPIO_PER_PIN_OE_23_REG_RESVAL 0x0u
#define GPIO_PER_PIN_OE_23_OE_BIT 0
 
// Per-pin view of the interrupt control and input filter configuration of
// GPIO[23].
#define GPIO_PER_PIN_INTR_CTRL_23_REG_OFFSET 0x2bc
#define GPIO_PER_PIN_INTR_CTRL_23_REG_RESVAL 0x0u
#define GPIO_PER_PIN_INTR_CTRL_23_INTR_CTRL_EN_RISING_BIT 0
#define GPIO_PER_PIN_INTR_CTRL_23_INTR_CTRL_EN_FALLING_BIT 1
#define GPIO_PER_PIN_INTR_CTRL_23_INTR_CTRL_EN_LVLHIGH_BIT 2
#define GPIO_PER_PIN_INTR_CTRL_23_INTR_CTRL_EN_LVLLOW_BIT 3
#define GPIO_PER_PIN_INTR_CTRL_23_CTRL_EN_INPUT_FILTER_BIT 4
 
// Per-pin view of the output enable of GPIO[24].
#define GPIO_PER_PIN_OE_24_REG_OFFSET 0x2c0
#define GPIO_PER_PIN_OE_24_REG_RESVAL 0x0u
#define GPIO_PER_PIN_OE_24_OE_BIT 0
 
// Per-pin view of the interrupt control and input filter configuration of
// GPIO[24].
#define GPIO_PER_PIN_INTR_CTRL_24_REG_OFFSET 0x2c4
#define GPIO_PER_PIN_INTR_CTRL_24_REG_RESVAL 0x0u
#define GPIO_PER_PIN_INTR_CTRL_24_INTR_CTRL_EN_RISING_BIT 0
#define GPIO_PER_PIN_INTR_CTRL_24_INTR_CTRL_EN_FALLING_BIT 1
#define GPIO_PER_PIN_INTR_CTRL_24_INTR_CTRL_EN_LVLHIGH_BIT 2
#define GPIO_PER_PIN_INTR_CTRL_24_INTR_CTRL_EN_LVLLOW_BIT 3
#define GPIO_PER_PIN_INTR_CTRL_24_CTRL_EN_INPUT_FILTER_BIT 4
 
// Per-pin view of the output enable of GPIO[25].
#define GPIO_PER_PIN_OE_25_REG_OFFSET 0x2c8
#define GPIO_PER_PIN_OE_25_REG_RESVAL 0x0u
#define GPIO_PER_PIN_OE_25_OE_BIT 0
 
// Per-pin view of the interrupt control and input filter configuration of
// GPIO[25].
#define GPIO_PER_PIN_INTR_CTRL_25_REG_OFFSET 0x2cc
#define GPIO_PER_PIN_INTR_CTRL_25_REG_RESVAL 0x0u
#define GPIO_PER_PIN_INTR_CTRL_25_INTR_CTRL_EN_RISING_BIT 0
#define GPIO_PER_PIN_INTR_CTRL_25_INTR_CTRL_EN_FALLING_BIT 1
#define GPIO_PER_PIN_INTR_CTRL_25_INTR_CTRL_EN_LVLHIGH_BIT 2
#define GPIO_PER_PIN_INTR_CTRL_25_INTR_CTRL_EN_LVLLOW_BIT 3
#define GPIO_PER_PIN_INTR_CTRL_25_CTRL_EN_INPUT_FILTER_BIT 4
 
// Per-pin view of the output enable of GPIO[26].
#define GPIO_PER_PIN_OE_26_REG_OFFSET 0x2d0
#define GPIO_PER_PIN_OE_26_REG_RESVAL 0x0u
#define GPIO_PER_PIN_OE_26_OE_BIT 0
 
// Per-pin view of the interrupt control and input filter configuration of
// GPIO[26].
#define GPIO_PER_PIN_INTR_CTRL_26_REG_OFFSET 0x2d4
#define GPIO_PER_PIN_INTR_CTRL_26_REG_RESVAL 0x0u
#define GPIO_PER_PIN_INTR_CTRL_26_INTR_CTRL_EN_RISING_BIT 0
#define GPIO_PER_PIN_INTR_CTRL_26_INTR_CTRL_EN_FALLING_BIT 1
#define GPIO_PER_PIN_INTR_CTRL_26_INTR_CTRL_EN_LVLHIGH_BIT 2
#define GPIO_PER_PIN_INTR_CTRL_26_INTR_CTRL_EN_LVLLOW_BIT 3
#define GPIO_PER_PIN_INTR_CTRL_26_CTRL_EN_INPUT_FILTER_BIT 4
 
// Per-pin view of the output enable of GPIO[27].
#define GPIO_PER_PIN_OE_27_REG_OFFSET 0x2d8
#define GPIO_PER_PIN_OE_27_REG_RESVAL 0x0u
#define GPIO_PER_PIN_OE_27_OE_BIT 0
 
// Per-pin view of the interrupt control and input filter configuration of
// GPIO[27].
#define GPIO_PER_PIN_INTR_CTRL_27_REG_OFFSET 0x2dc
#define GPIO_PER_PIN_INTR_CTRL_27_REG_RESVAL 0x0u
#define GPIO_PER_PIN_INTR_CTRL_27_INTR_CTRL_EN_RISING_BIT 0
#define GPIO_PER_PIN_INTR_CTRL_27_INTR_CTRL_EN_FALLING_BIT 1
#define GPIO_PER_PIN_INTR_CTRL_27_INTR_CTRL_EN_LVLHIGH_BIT 2
#define GPIO_PER_PIN_INTR_CTRL_27_INTR_CTRL_EN_LVLLOW_BIT 3
#define GPIO_PER_PIN_INTR_CTRL_27_CTRL_EN_INPUT_FILTER_BIT 4
 
// Per-pin view of the output enable of GPIO[28].
#define GPIO_PER_PIN_OE_28_REG_OFFSET 0x2e0
#define GPIO_PER_PIN_OE_28_REG_RESVAL 0x0u
#define GPIO_PER_PIN_OE_28_OE_BIT 0
 
// Per-pin view of the interrupt control and input filter configuration of
// GPIO[28].
#define GPIO_PER_PIN_INTR_CTRL_28_REG_OFFSET 0x2e4
#define GPIO_PER_PIN_INTR_CTRL_28_REG_RESVAL 0x0u
#define GPIO_PER_PIN_INTR_CTRL_28_INTR_CTRL_EN_RISING_BIT 0
#define GPIO_PER_PIN_INTR_CTRL_28_INTR_CTRL_EN_FALLING_BIT 1
#define GPIO_PER_PIN_INTR_CTRL_28_INTR_CTRL_EN_LVLHIGH_BIT 2
#define GPIO_PER_PIN_INTR_CTRL_28_INTR_CTRL_EN_LVLLOW_BIT 3
#define GPIO_PER_PIN_INTR_CTRL_28_CTRL_EN_INPUT_FILTER_BIT 4
 
// Per-pin view of the output enable of GPIO[29].
#define GPIO_PER_PIN_OE_29_REG_OFFSET 0x2e8
#define GPIO_PER_PIN_OE_29_REG_RESVAL 0x0u
#define GPIO_PER_PIN_OE_29_OE_BIT 0
 
// Per-pin view of the interrupt control and input filter configuration of
// GPIO[29].
#define GPIO_PER_PIN_INTR_CTRL_29_REG_OFFSET 0x2ec
#define GPIO_PER_PIN_INTR_CTRL_29_REG_RESVAL 0x0u
#define GPIO_PER_PIN_INTR_CTRL_29_INTR_CTRL_EN_RISING_BIT 0
#define GPIO_PER_PIN_INTR_CTRL_29_INTR_CTRL_EN_FALLING_BIT 1
#define GPIO_PER_PIN_INTR_CTRL_29_INTR_CTRL_EN_LVLHIGH_BIT 2
#define GPIO_PER_PIN_INTR_CTRL_29_INTR_CTRL_EN_LVLLOW_BIT 3
#define GPIO_PER_PIN_INTR_CTRL_29_CTRL_EN_INPUT_FILTER_BIT 4
 
// Per-pin view of the output enable of GPIO[30].
#define GPIO_PER_PIN_OE_30_REG_OFFSET 0x2f0
#define GPIO_PER_PIN_OE_30_REG_RESVAL 0x0u
#define GPIO_PER_PIN_OE_30_OE_BIT 0
 
// Per-pin view of the interrupt control and input filter configuration of
// GPIO[30].
#define GPIO_PER_PIN_INTR_CTRL_30_REG_OFFSET 0x2f4
#define GPIO_PER_PIN_INTR_CTRL_30_REG_RESVAL 0x0u
#define GPIO_PER_PIN_INTR_CTRL_30_INTR_CTRL_EN_RISING_BIT 0
#define GPIO_PER_PIN_INTR_CTRL_30_INTR_CTRL_EN_FALLING_BIT 1
#define GPIO_PER_PIN_INTR_CTRL_30_INTR_CTRL_EN_LVLHIGH_BIT 2
#define GPIO_PER_PIN_INTR_CTRL_30_INTR_CTRL_EN_LVLLOW_BIT 3
#define GPIO_PER_PIN_INTR_CTRL_30_CTRL_EN_INPUT_FILTER_BIT 4
 
// Per-pin view of the output enable of GPIO[31].
#define GPIO_PER_PIN_OE_31_REG_OFFSET 0x2f8
#define GPIO_PER_PIN_OE_31_REG_RESVAL 0x0u
#define GPIO_PER_PIN_OE_31_OE_BIT 0
 
// Per-pin view of the interrupt control and input filter configuration of
// GPIO[31].
#define GPIO_PER_PIN_INTR_CTRL_31_REG_OFFSET 0x2fc
#define GPIO_PER_PIN_INTR_CTRL_31_REG_RESVAL 0x0u
#define GPIO_PER_PIN_INTR_CTRL_31_INTR_CTRL_EN_RISING_BIT 0
#define GPIO_PER_PIN_INTR_CTRL_31_INTR_CTRL_EN_FALLING_BIT 1
#define GPIO_PER_PIN_INTR_CTRL_31_INTR_CTRL_EN_LVLHIGH_BIT 2
#define GPIO_PER_PIN_INTR_CTRL_31_INTR_CTRL_EN_LVLLOW_BIT 3
#define GPIO_PER_PIN_INTR_CTRL_31_CTRL_EN_INPUT_FILTER_BIT 4
 
#ifdef __cplusplus
}  // extern "C"
#endif
#endif  // _GPIO_REG_DEFS_
// End generated register defines for gpio