entropy_src_regs.h

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/**
 * @file
 * @brief Generated register defines for entropy_src
 */
 
// Copyright information found in source file:
// Copyright lowRISC contributors (OpenTitan project).
 
// Licensing information found in source file:
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
 
#ifndef _ENTROPY_SRC_REG_DEFS_
#define _ENTROPY_SRC_REG_DEFS_
 
#ifdef __cplusplus
extern "C" {
#endif
//  Number of 32-bit entries in the observe FIFO.
#define ENTROPY_SRC_PARAM_OBSERVE_FIFO_DEPTH 32
 
// Number of alerts
#define ENTROPY_SRC_PARAM_NUM_ALERTS 2
 
// Register width
#define ENTROPY_SRC_PARAM_REG_WIDTH 32
 
// Common Interrupt Offsets
#define ENTROPY_SRC_INTR_COMMON_ES_ENTROPY_VALID_BIT 0
#define ENTROPY_SRC_INTR_COMMON_ES_HEALTH_TEST_FAILED_BIT 1
#define ENTROPY_SRC_INTR_COMMON_ES_OBSERVE_FIFO_READY_BIT 2
#define ENTROPY_SRC_INTR_COMMON_ES_FATAL_ERR_BIT 3
 
// Interrupt State Register
#define ENTROPY_SRC_INTR_STATE_REG_OFFSET 0x0
#define ENTROPY_SRC_INTR_STATE_REG_RESVAL 0x0u
#define ENTROPY_SRC_INTR_STATE_ES_ENTROPY_VALID_BIT 0
#define ENTROPY_SRC_INTR_STATE_ES_HEALTH_TEST_FAILED_BIT 1
#define ENTROPY_SRC_INTR_STATE_ES_OBSERVE_FIFO_READY_BIT 2
#define ENTROPY_SRC_INTR_STATE_ES_FATAL_ERR_BIT 3
 
// Interrupt Enable Register
#define ENTROPY_SRC_INTR_ENABLE_REG_OFFSET 0x4
#define ENTROPY_SRC_INTR_ENABLE_REG_RESVAL 0x0u
#define ENTROPY_SRC_INTR_ENABLE_ES_ENTROPY_VALID_BIT 0
#define ENTROPY_SRC_INTR_ENABLE_ES_HEALTH_TEST_FAILED_BIT 1
#define ENTROPY_SRC_INTR_ENABLE_ES_OBSERVE_FIFO_READY_BIT 2
#define ENTROPY_SRC_INTR_ENABLE_ES_FATAL_ERR_BIT 3
 
// Interrupt Test Register
#define ENTROPY_SRC_INTR_TEST_REG_OFFSET 0x8
#define ENTROPY_SRC_INTR_TEST_REG_RESVAL 0x0u
#define ENTROPY_SRC_INTR_TEST_ES_ENTROPY_VALID_BIT 0
#define ENTROPY_SRC_INTR_TEST_ES_HEALTH_TEST_FAILED_BIT 1
#define ENTROPY_SRC_INTR_TEST_ES_OBSERVE_FIFO_READY_BIT 2
#define ENTROPY_SRC_INTR_TEST_ES_FATAL_ERR_BIT 3
 
// Alert Test Register
#define ENTROPY_SRC_ALERT_TEST_REG_OFFSET 0xc
#define ENTROPY_SRC_ALERT_TEST_REG_RESVAL 0x0u
#define ENTROPY_SRC_ALERT_TEST_RECOV_ALERT_BIT 0
#define ENTROPY_SRC_ALERT_TEST_FATAL_ALERT_BIT 1
 
// Register write enable for module enable register
#define ENTROPY_SRC_ME_REGWEN_REG_OFFSET 0x10
#define ENTROPY_SRC_ME_REGWEN_REG_RESVAL 0x1u
#define ENTROPY_SRC_ME_REGWEN_ME_REGWEN_BIT 0
 
// Register write enable for control and threshold registers
#define ENTROPY_SRC_SW_REGUPD_REG_OFFSET 0x14
#define ENTROPY_SRC_SW_REGUPD_REG_RESVAL 0x1u
#define ENTROPY_SRC_SW_REGUPD_SW_REGUPD_BIT 0
 
// Register write enable for all control registers
#define ENTROPY_SRC_REGWEN_REG_OFFSET 0x18
#define ENTROPY_SRC_REGWEN_REG_RESVAL 0x1u
#define ENTROPY_SRC_REGWEN_REGWEN_BIT 0
 
// Module enable register
#define ENTROPY_SRC_MODULE_ENABLE_REG_OFFSET 0x1c
#define ENTROPY_SRC_MODULE_ENABLE_REG_RESVAL 0x9u
#define ENTROPY_SRC_MODULE_ENABLE_MODULE_ENABLE_MASK 0xfu
#define ENTROPY_SRC_MODULE_ENABLE_MODULE_ENABLE_OFFSET 0
#define ENTROPY_SRC_MODULE_ENABLE_MODULE_ENABLE_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_MODULE_ENABLE_MODULE_ENABLE_MASK, .index = ENTROPY_SRC_MODULE_ENABLE_MODULE_ENABLE_OFFSET })
 
// Configuration register
#define ENTROPY_SRC_CONF_REG_OFFSET 0x20
#define ENTROPY_SRC_CONF_REG_RESVAL 0x999999u
#define ENTROPY_SRC_CONF_FIPS_ENABLE_MASK 0xfu
#define ENTROPY_SRC_CONF_FIPS_ENABLE_OFFSET 0
#define ENTROPY_SRC_CONF_FIPS_ENABLE_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_CONF_FIPS_ENABLE_MASK, .index = ENTROPY_SRC_CONF_FIPS_ENABLE_OFFSET })
#define ENTROPY_SRC_CONF_FIPS_FLAG_MASK 0xfu
#define ENTROPY_SRC_CONF_FIPS_FLAG_OFFSET 4
#define ENTROPY_SRC_CONF_FIPS_FLAG_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_CONF_FIPS_FLAG_MASK, .index = ENTROPY_SRC_CONF_FIPS_FLAG_OFFSET })
#define ENTROPY_SRC_CONF_RNG_FIPS_MASK 0xfu
#define ENTROPY_SRC_CONF_RNG_FIPS_OFFSET 8
#define ENTROPY_SRC_CONF_RNG_FIPS_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_CONF_RNG_FIPS_MASK, .index = ENTROPY_SRC_CONF_RNG_FIPS_OFFSET })
#define ENTROPY_SRC_CONF_RNG_BIT_ENABLE_MASK 0xfu
#define ENTROPY_SRC_CONF_RNG_BIT_ENABLE_OFFSET 12
#define ENTROPY_SRC_CONF_RNG_BIT_ENABLE_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_CONF_RNG_BIT_ENABLE_MASK, .index = ENTROPY_SRC_CONF_RNG_BIT_ENABLE_OFFSET })
#define ENTROPY_SRC_CONF_THRESHOLD_SCOPE_MASK 0xfu
#define ENTROPY_SRC_CONF_THRESHOLD_SCOPE_OFFSET 16
#define ENTROPY_SRC_CONF_THRESHOLD_SCOPE_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_CONF_THRESHOLD_SCOPE_MASK, .index = ENTROPY_SRC_CONF_THRESHOLD_SCOPE_OFFSET })
#define ENTROPY_SRC_CONF_ENTROPY_DATA_REG_ENABLE_MASK 0xfu
#define ENTROPY_SRC_CONF_ENTROPY_DATA_REG_ENABLE_OFFSET 20
#define ENTROPY_SRC_CONF_ENTROPY_DATA_REG_ENABLE_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_CONF_ENTROPY_DATA_REG_ENABLE_MASK, .index = ENTROPY_SRC_CONF_ENTROPY_DATA_REG_ENABLE_OFFSET })
#define ENTROPY_SRC_CONF_RNG_BIT_SEL_MASK 0xffu
#define ENTROPY_SRC_CONF_RNG_BIT_SEL_OFFSET 24
#define ENTROPY_SRC_CONF_RNG_BIT_SEL_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_CONF_RNG_BIT_SEL_MASK, .index = ENTROPY_SRC_CONF_RNG_BIT_SEL_OFFSET })
 
// Entropy control register
#define ENTROPY_SRC_ENTROPY_CONTROL_REG_OFFSET 0x24
#define ENTROPY_SRC_ENTROPY_CONTROL_REG_RESVAL 0x99u
#define ENTROPY_SRC_ENTROPY_CONTROL_ES_ROUTE_MASK 0xfu
#define ENTROPY_SRC_ENTROPY_CONTROL_ES_ROUTE_OFFSET 0
#define ENTROPY_SRC_ENTROPY_CONTROL_ES_ROUTE_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_ENTROPY_CONTROL_ES_ROUTE_MASK, .index = ENTROPY_SRC_ENTROPY_CONTROL_ES_ROUTE_OFFSET })
#define ENTROPY_SRC_ENTROPY_CONTROL_ES_TYPE_MASK 0xfu
#define ENTROPY_SRC_ENTROPY_CONTROL_ES_TYPE_OFFSET 4
#define ENTROPY_SRC_ENTROPY_CONTROL_ES_TYPE_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_ENTROPY_CONTROL_ES_TYPE_MASK, .index = ENTROPY_SRC_ENTROPY_CONTROL_ES_TYPE_OFFSET })
 
// Entropy data bits
#define ENTROPY_SRC_ENTROPY_DATA_REG_OFFSET 0x28
#define ENTROPY_SRC_ENTROPY_DATA_REG_RESVAL 0x0u
 
// Health test windows register
#define ENTROPY_SRC_HEALTH_TEST_WINDOWS_REG_OFFSET 0x2c
#define ENTROPY_SRC_HEALTH_TEST_WINDOWS_REG_RESVAL 0x1800200u
#define ENTROPY_SRC_HEALTH_TEST_WINDOWS_FIPS_WINDOW_MASK 0xffffu
#define ENTROPY_SRC_HEALTH_TEST_WINDOWS_FIPS_WINDOW_OFFSET 0
#define ENTROPY_SRC_HEALTH_TEST_WINDOWS_FIPS_WINDOW_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_HEALTH_TEST_WINDOWS_FIPS_WINDOW_MASK, .index = ENTROPY_SRC_HEALTH_TEST_WINDOWS_FIPS_WINDOW_OFFSET })
#define ENTROPY_SRC_HEALTH_TEST_WINDOWS_BYPASS_WINDOW_MASK 0xffffu
#define ENTROPY_SRC_HEALTH_TEST_WINDOWS_BYPASS_WINDOW_OFFSET 16
#define ENTROPY_SRC_HEALTH_TEST_WINDOWS_BYPASS_WINDOW_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_HEALTH_TEST_WINDOWS_BYPASS_WINDOW_MASK, .index = ENTROPY_SRC_HEALTH_TEST_WINDOWS_BYPASS_WINDOW_OFFSET })
 
// Threshold one way control register
#define ENTROPY_SRC_THRESHOLD_ONEWAY_REG_OFFSET 0x30
#define ENTROPY_SRC_THRESHOLD_ONEWAY_REG_RESVAL 0x9u
#define ENTROPY_SRC_THRESHOLD_ONEWAY_THRESHOLD_ONEWAY_MASK 0xfu
#define ENTROPY_SRC_THRESHOLD_ONEWAY_THRESHOLD_ONEWAY_OFFSET 0
#define ENTROPY_SRC_THRESHOLD_ONEWAY_THRESHOLD_ONEWAY_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_THRESHOLD_ONEWAY_THRESHOLD_ONEWAY_MASK, .index = ENTROPY_SRC_THRESHOLD_ONEWAY_THRESHOLD_ONEWAY_OFFSET })
 
// Repetition Count Test threshold register
#define ENTROPY_SRC_REPCNT_THRESHOLD_REG_OFFSET 0x34
#define ENTROPY_SRC_REPCNT_THRESHOLD_REG_RESVAL 0xffffu
#define ENTROPY_SRC_REPCNT_THRESHOLD_REPCNT_THRESHOLD_MASK 0xffffu
#define ENTROPY_SRC_REPCNT_THRESHOLD_REPCNT_THRESHOLD_OFFSET 0
#define ENTROPY_SRC_REPCNT_THRESHOLD_REPCNT_THRESHOLD_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_REPCNT_THRESHOLD_REPCNT_THRESHOLD_MASK, .index = ENTROPY_SRC_REPCNT_THRESHOLD_REPCNT_THRESHOLD_OFFSET })
 
// Repetition Count Symbol Test threshold register
#define ENTROPY_SRC_REPCNTS_THRESHOLD_REG_OFFSET 0x38
#define ENTROPY_SRC_REPCNTS_THRESHOLD_REG_RESVAL 0xffffu
#define ENTROPY_SRC_REPCNTS_THRESHOLD_REPCNTS_THRESHOLD_MASK 0xffffu
#define ENTROPY_SRC_REPCNTS_THRESHOLD_REPCNTS_THRESHOLD_OFFSET 0
#define ENTROPY_SRC_REPCNTS_THRESHOLD_REPCNTS_THRESHOLD_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_REPCNTS_THRESHOLD_REPCNTS_THRESHOLD_MASK, .index = ENTROPY_SRC_REPCNTS_THRESHOLD_REPCNTS_THRESHOLD_OFFSET })
 
// Adaptive proportion test high threshold register
#define ENTROPY_SRC_ADAPTP_HI_THRESHOLD_REG_OFFSET 0x3c
#define ENTROPY_SRC_ADAPTP_HI_THRESHOLD_REG_RESVAL 0xffffu
#define ENTROPY_SRC_ADAPTP_HI_THRESHOLD_ADAPTP_HI_THRESHOLD_MASK 0xffffu
#define ENTROPY_SRC_ADAPTP_HI_THRESHOLD_ADAPTP_HI_THRESHOLD_OFFSET 0
#define ENTROPY_SRC_ADAPTP_HI_THRESHOLD_ADAPTP_HI_THRESHOLD_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_ADAPTP_HI_THRESHOLD_ADAPTP_HI_THRESHOLD_MASK, .index = ENTROPY_SRC_ADAPTP_HI_THRESHOLD_ADAPTP_HI_THRESHOLD_OFFSET })
 
// Adaptive proportion test low threshold register
#define ENTROPY_SRC_ADAPTP_LO_THRESHOLD_REG_OFFSET 0x40
#define ENTROPY_SRC_ADAPTP_LO_THRESHOLD_REG_RESVAL 0x0u
#define ENTROPY_SRC_ADAPTP_LO_THRESHOLD_ADAPTP_LO_THRESHOLD_MASK 0xffffu
#define ENTROPY_SRC_ADAPTP_LO_THRESHOLD_ADAPTP_LO_THRESHOLD_OFFSET 0
#define ENTROPY_SRC_ADAPTP_LO_THRESHOLD_ADAPTP_LO_THRESHOLD_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_ADAPTP_LO_THRESHOLD_ADAPTP_LO_THRESHOLD_MASK, .index = ENTROPY_SRC_ADAPTP_LO_THRESHOLD_ADAPTP_LO_THRESHOLD_OFFSET })
 
// Bucket test threshold register
#define ENTROPY_SRC_BUCKET_THRESHOLD_REG_OFFSET 0x44
#define ENTROPY_SRC_BUCKET_THRESHOLD_REG_RESVAL 0xffffu
#define ENTROPY_SRC_BUCKET_THRESHOLD_BUCKET_THRESHOLD_MASK 0xffffu
#define ENTROPY_SRC_BUCKET_THRESHOLD_BUCKET_THRESHOLD_OFFSET 0
#define ENTROPY_SRC_BUCKET_THRESHOLD_BUCKET_THRESHOLD_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_BUCKET_THRESHOLD_BUCKET_THRESHOLD_MASK, .index = ENTROPY_SRC_BUCKET_THRESHOLD_BUCKET_THRESHOLD_OFFSET })
 
// Markov test high threshold register
#define ENTROPY_SRC_MARKOV_HI_THRESHOLD_REG_OFFSET 0x48
#define ENTROPY_SRC_MARKOV_HI_THRESHOLD_REG_RESVAL 0xffffu
#define ENTROPY_SRC_MARKOV_HI_THRESHOLD_MARKOV_HI_THRESHOLD_MASK 0xffffu
#define ENTROPY_SRC_MARKOV_HI_THRESHOLD_MARKOV_HI_THRESHOLD_OFFSET 0
#define ENTROPY_SRC_MARKOV_HI_THRESHOLD_MARKOV_HI_THRESHOLD_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_MARKOV_HI_THRESHOLD_MARKOV_HI_THRESHOLD_MASK, .index = ENTROPY_SRC_MARKOV_HI_THRESHOLD_MARKOV_HI_THRESHOLD_OFFSET })
 
// Markov test low threshold register
#define ENTROPY_SRC_MARKOV_LO_THRESHOLD_REG_OFFSET 0x4c
#define ENTROPY_SRC_MARKOV_LO_THRESHOLD_REG_RESVAL 0x0u
#define ENTROPY_SRC_MARKOV_LO_THRESHOLD_MARKOV_LO_THRESHOLD_MASK 0xffffu
#define ENTROPY_SRC_MARKOV_LO_THRESHOLD_MARKOV_LO_THRESHOLD_OFFSET 0
#define ENTROPY_SRC_MARKOV_LO_THRESHOLD_MARKOV_LO_THRESHOLD_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_MARKOV_LO_THRESHOLD_MARKOV_LO_THRESHOLD_MASK, .index = ENTROPY_SRC_MARKOV_LO_THRESHOLD_MARKOV_LO_THRESHOLD_OFFSET })
 
// External health test high threshold register
#define ENTROPY_SRC_EXTHT_HI_THRESHOLD_REG_OFFSET 0x50
#define ENTROPY_SRC_EXTHT_HI_THRESHOLD_REG_RESVAL 0xffffu
#define ENTROPY_SRC_EXTHT_HI_THRESHOLD_EXTHT_HI_THRESHOLD_MASK 0xffffu
#define ENTROPY_SRC_EXTHT_HI_THRESHOLD_EXTHT_HI_THRESHOLD_OFFSET 0
#define ENTROPY_SRC_EXTHT_HI_THRESHOLD_EXTHT_HI_THRESHOLD_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_EXTHT_HI_THRESHOLD_EXTHT_HI_THRESHOLD_MASK, .index = ENTROPY_SRC_EXTHT_HI_THRESHOLD_EXTHT_HI_THRESHOLD_OFFSET })
 
// External health test low threshold register
#define ENTROPY_SRC_EXTHT_LO_THRESHOLD_REG_OFFSET 0x54
#define ENTROPY_SRC_EXTHT_LO_THRESHOLD_REG_RESVAL 0x0u
#define ENTROPY_SRC_EXTHT_LO_THRESHOLD_EXTHT_LO_THRESHOLD_MASK 0xffffu
#define ENTROPY_SRC_EXTHT_LO_THRESHOLD_EXTHT_LO_THRESHOLD_OFFSET 0
#define ENTROPY_SRC_EXTHT_LO_THRESHOLD_EXTHT_LO_THRESHOLD_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_EXTHT_LO_THRESHOLD_EXTHT_LO_THRESHOLD_MASK, .index = ENTROPY_SRC_EXTHT_LO_THRESHOLD_EXTHT_LO_THRESHOLD_OFFSET })
 
// Health test watermark number register
#define ENTROPY_SRC_HT_WATERMARK_NUM_REG_OFFSET 0x58
#define ENTROPY_SRC_HT_WATERMARK_NUM_REG_RESVAL 0x0u
#define ENTROPY_SRC_HT_WATERMARK_NUM_HT_WATERMARK_NUM_MASK 0xfu
#define ENTROPY_SRC_HT_WATERMARK_NUM_HT_WATERMARK_NUM_OFFSET 0
#define ENTROPY_SRC_HT_WATERMARK_NUM_HT_WATERMARK_NUM_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_HT_WATERMARK_NUM_HT_WATERMARK_NUM_MASK, .index = ENTROPY_SRC_HT_WATERMARK_NUM_HT_WATERMARK_NUM_OFFSET })
#define ENTROPY_SRC_HT_WATERMARK_NUM_HT_WATERMARK_NUM_VALUE_REPCNT_HI 0x0
#define ENTROPY_SRC_HT_WATERMARK_NUM_HT_WATERMARK_NUM_VALUE_REPCNTS_HI 0x1
#define ENTROPY_SRC_HT_WATERMARK_NUM_HT_WATERMARK_NUM_VALUE_ADAPTP_HI 0x2
#define ENTROPY_SRC_HT_WATERMARK_NUM_HT_WATERMARK_NUM_VALUE_ADAPTP_LO 0x3
#define ENTROPY_SRC_HT_WATERMARK_NUM_HT_WATERMARK_NUM_VALUE_BUCKET_HI 0x4
#define ENTROPY_SRC_HT_WATERMARK_NUM_HT_WATERMARK_NUM_VALUE_MARKOV_HI 0x5
#define ENTROPY_SRC_HT_WATERMARK_NUM_HT_WATERMARK_NUM_VALUE_MARKOV_LO 0x6
#define ENTROPY_SRC_HT_WATERMARK_NUM_HT_WATERMARK_NUM_VALUE_EXTHT_HI 0x7
#define ENTROPY_SRC_HT_WATERMARK_NUM_HT_WATERMARK_NUM_VALUE_EXTHT_LO 0x8
 
// Health test watermark register
#define ENTROPY_SRC_HT_WATERMARK_REG_OFFSET 0x5c
#define ENTROPY_SRC_HT_WATERMARK_REG_RESVAL 0x0u
#define ENTROPY_SRC_HT_WATERMARK_HT_WATERMARK_MASK 0xffffu
#define ENTROPY_SRC_HT_WATERMARK_HT_WATERMARK_OFFSET 0
#define ENTROPY_SRC_HT_WATERMARK_HT_WATERMARK_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_HT_WATERMARK_HT_WATERMARK_MASK, .index = ENTROPY_SRC_HT_WATERMARK_HT_WATERMARK_OFFSET })
 
// Repetition Count Test failure counter register
#define ENTROPY_SRC_REPCNT_TOTAL_FAILS_REG_OFFSET 0x60
#define ENTROPY_SRC_REPCNT_TOTAL_FAILS_REG_RESVAL 0x0u
 
// Repetition Count Symbol Test failure counter register
#define ENTROPY_SRC_REPCNTS_TOTAL_FAILS_REG_OFFSET 0x64
#define ENTROPY_SRC_REPCNTS_TOTAL_FAILS_REG_RESVAL 0x0u
 
// Adaptive proportion high test failure counter register
#define ENTROPY_SRC_ADAPTP_HI_TOTAL_FAILS_REG_OFFSET 0x68
#define ENTROPY_SRC_ADAPTP_HI_TOTAL_FAILS_REG_RESVAL 0x0u
 
// Adaptive proportion low test failure counter register
#define ENTROPY_SRC_ADAPTP_LO_TOTAL_FAILS_REG_OFFSET 0x6c
#define ENTROPY_SRC_ADAPTP_LO_TOTAL_FAILS_REG_RESVAL 0x0u
 
// Bucket test failure counter register
#define ENTROPY_SRC_BUCKET_TOTAL_FAILS_REG_OFFSET 0x70
#define ENTROPY_SRC_BUCKET_TOTAL_FAILS_REG_RESVAL 0x0u
 
// Markov high test failure counter register
#define ENTROPY_SRC_MARKOV_HI_TOTAL_FAILS_REG_OFFSET 0x74
#define ENTROPY_SRC_MARKOV_HI_TOTAL_FAILS_REG_RESVAL 0x0u
 
// Markov low test failure counter register
#define ENTROPY_SRC_MARKOV_LO_TOTAL_FAILS_REG_OFFSET 0x78
#define ENTROPY_SRC_MARKOV_LO_TOTAL_FAILS_REG_RESVAL 0x0u
 
// External health test high threshold failure counter register
#define ENTROPY_SRC_EXTHT_HI_TOTAL_FAILS_REG_OFFSET 0x7c
#define ENTROPY_SRC_EXTHT_HI_TOTAL_FAILS_REG_RESVAL 0x0u
 
// External health test low threshold failure counter register
#define ENTROPY_SRC_EXTHT_LO_TOTAL_FAILS_REG_OFFSET 0x80
#define ENTROPY_SRC_EXTHT_LO_TOTAL_FAILS_REG_RESVAL 0x0u
 
// Alert threshold register
#define ENTROPY_SRC_ALERT_THRESHOLD_REG_OFFSET 0x84
#define ENTROPY_SRC_ALERT_THRESHOLD_REG_RESVAL 0xfffd0002u
#define ENTROPY_SRC_ALERT_THRESHOLD_ALERT_THRESHOLD_MASK 0xffffu
#define ENTROPY_SRC_ALERT_THRESHOLD_ALERT_THRESHOLD_OFFSET 0
#define ENTROPY_SRC_ALERT_THRESHOLD_ALERT_THRESHOLD_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_ALERT_THRESHOLD_ALERT_THRESHOLD_MASK, .index = ENTROPY_SRC_ALERT_THRESHOLD_ALERT_THRESHOLD_OFFSET })
#define ENTROPY_SRC_ALERT_THRESHOLD_ALERT_THRESHOLD_INV_MASK 0xffffu
#define ENTROPY_SRC_ALERT_THRESHOLD_ALERT_THRESHOLD_INV_OFFSET 16
#define ENTROPY_SRC_ALERT_THRESHOLD_ALERT_THRESHOLD_INV_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_ALERT_THRESHOLD_ALERT_THRESHOLD_INV_MASK, .index = ENTROPY_SRC_ALERT_THRESHOLD_ALERT_THRESHOLD_INV_OFFSET })
 
// Alert summary failure counts register
#define ENTROPY_SRC_ALERT_SUMMARY_FAIL_COUNTS_REG_OFFSET 0x88
#define ENTROPY_SRC_ALERT_SUMMARY_FAIL_COUNTS_REG_RESVAL 0x0u
#define ENTROPY_SRC_ALERT_SUMMARY_FAIL_COUNTS_ANY_FAIL_COUNT_MASK 0xffffu
#define ENTROPY_SRC_ALERT_SUMMARY_FAIL_COUNTS_ANY_FAIL_COUNT_OFFSET 0
#define ENTROPY_SRC_ALERT_SUMMARY_FAIL_COUNTS_ANY_FAIL_COUNT_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_ALERT_SUMMARY_FAIL_COUNTS_ANY_FAIL_COUNT_MASK, .index = ENTROPY_SRC_ALERT_SUMMARY_FAIL_COUNTS_ANY_FAIL_COUNT_OFFSET })
 
// Alert failure counts register
#define ENTROPY_SRC_ALERT_FAIL_COUNTS_REG_OFFSET 0x8c
#define ENTROPY_SRC_ALERT_FAIL_COUNTS_REG_RESVAL 0x0u
#define ENTROPY_SRC_ALERT_FAIL_COUNTS_REPCNT_FAIL_COUNT_MASK 0xfu
#define ENTROPY_SRC_ALERT_FAIL_COUNTS_REPCNT_FAIL_COUNT_OFFSET 4
#define ENTROPY_SRC_ALERT_FAIL_COUNTS_REPCNT_FAIL_COUNT_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_ALERT_FAIL_COUNTS_REPCNT_FAIL_COUNT_MASK, .index = ENTROPY_SRC_ALERT_FAIL_COUNTS_REPCNT_FAIL_COUNT_OFFSET })
#define ENTROPY_SRC_ALERT_FAIL_COUNTS_ADAPTP_HI_FAIL_COUNT_MASK 0xfu
#define ENTROPY_SRC_ALERT_FAIL_COUNTS_ADAPTP_HI_FAIL_COUNT_OFFSET 8
#define ENTROPY_SRC_ALERT_FAIL_COUNTS_ADAPTP_HI_FAIL_COUNT_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_ALERT_FAIL_COUNTS_ADAPTP_HI_FAIL_COUNT_MASK, .index = ENTROPY_SRC_ALERT_FAIL_COUNTS_ADAPTP_HI_FAIL_COUNT_OFFSET })
#define ENTROPY_SRC_ALERT_FAIL_COUNTS_ADAPTP_LO_FAIL_COUNT_MASK 0xfu
#define ENTROPY_SRC_ALERT_FAIL_COUNTS_ADAPTP_LO_FAIL_COUNT_OFFSET 12
#define ENTROPY_SRC_ALERT_FAIL_COUNTS_ADAPTP_LO_FAIL_COUNT_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_ALERT_FAIL_COUNTS_ADAPTP_LO_FAIL_COUNT_MASK, .index = ENTROPY_SRC_ALERT_FAIL_COUNTS_ADAPTP_LO_FAIL_COUNT_OFFSET })
#define ENTROPY_SRC_ALERT_FAIL_COUNTS_BUCKET_FAIL_COUNT_MASK 0xfu
#define ENTROPY_SRC_ALERT_FAIL_COUNTS_BUCKET_FAIL_COUNT_OFFSET 16
#define ENTROPY_SRC_ALERT_FAIL_COUNTS_BUCKET_FAIL_COUNT_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_ALERT_FAIL_COUNTS_BUCKET_FAIL_COUNT_MASK, .index = ENTROPY_SRC_ALERT_FAIL_COUNTS_BUCKET_FAIL_COUNT_OFFSET })
#define ENTROPY_SRC_ALERT_FAIL_COUNTS_MARKOV_HI_FAIL_COUNT_MASK 0xfu
#define ENTROPY_SRC_ALERT_FAIL_COUNTS_MARKOV_HI_FAIL_COUNT_OFFSET 20
#define ENTROPY_SRC_ALERT_FAIL_COUNTS_MARKOV_HI_FAIL_COUNT_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_ALERT_FAIL_COUNTS_MARKOV_HI_FAIL_COUNT_MASK, .index = ENTROPY_SRC_ALERT_FAIL_COUNTS_MARKOV_HI_FAIL_COUNT_OFFSET })
#define ENTROPY_SRC_ALERT_FAIL_COUNTS_MARKOV_LO_FAIL_COUNT_MASK 0xfu
#define ENTROPY_SRC_ALERT_FAIL_COUNTS_MARKOV_LO_FAIL_COUNT_OFFSET 24
#define ENTROPY_SRC_ALERT_FAIL_COUNTS_MARKOV_LO_FAIL_COUNT_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_ALERT_FAIL_COUNTS_MARKOV_LO_FAIL_COUNT_MASK, .index = ENTROPY_SRC_ALERT_FAIL_COUNTS_MARKOV_LO_FAIL_COUNT_OFFSET })
#define ENTROPY_SRC_ALERT_FAIL_COUNTS_REPCNTS_FAIL_COUNT_MASK 0xfu
#define ENTROPY_SRC_ALERT_FAIL_COUNTS_REPCNTS_FAIL_COUNT_OFFSET 28
#define ENTROPY_SRC_ALERT_FAIL_COUNTS_REPCNTS_FAIL_COUNT_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_ALERT_FAIL_COUNTS_REPCNTS_FAIL_COUNT_MASK, .index = ENTROPY_SRC_ALERT_FAIL_COUNTS_REPCNTS_FAIL_COUNT_OFFSET })
 
// External health test alert failure counts register
#define ENTROPY_SRC_EXTHT_FAIL_COUNTS_REG_OFFSET 0x90
#define ENTROPY_SRC_EXTHT_FAIL_COUNTS_REG_RESVAL 0x0u
#define ENTROPY_SRC_EXTHT_FAIL_COUNTS_EXTHT_HI_FAIL_COUNT_MASK 0xfu
#define ENTROPY_SRC_EXTHT_FAIL_COUNTS_EXTHT_HI_FAIL_COUNT_OFFSET 0
#define ENTROPY_SRC_EXTHT_FAIL_COUNTS_EXTHT_HI_FAIL_COUNT_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_EXTHT_FAIL_COUNTS_EXTHT_HI_FAIL_COUNT_MASK, .index = ENTROPY_SRC_EXTHT_FAIL_COUNTS_EXTHT_HI_FAIL_COUNT_OFFSET })
#define ENTROPY_SRC_EXTHT_FAIL_COUNTS_EXTHT_LO_FAIL_COUNT_MASK 0xfu
#define ENTROPY_SRC_EXTHT_FAIL_COUNTS_EXTHT_LO_FAIL_COUNT_OFFSET 4
#define ENTROPY_SRC_EXTHT_FAIL_COUNTS_EXTHT_LO_FAIL_COUNT_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_EXTHT_FAIL_COUNTS_EXTHT_LO_FAIL_COUNT_MASK, .index = ENTROPY_SRC_EXTHT_FAIL_COUNTS_EXTHT_LO_FAIL_COUNT_OFFSET })
 
// Firmware override control register
#define ENTROPY_SRC_FW_OV_CONTROL_REG_OFFSET 0x94
#define ENTROPY_SRC_FW_OV_CONTROL_REG_RESVAL 0x99u
#define ENTROPY_SRC_FW_OV_CONTROL_FW_OV_MODE_MASK 0xfu
#define ENTROPY_SRC_FW_OV_CONTROL_FW_OV_MODE_OFFSET 0
#define ENTROPY_SRC_FW_OV_CONTROL_FW_OV_MODE_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_FW_OV_CONTROL_FW_OV_MODE_MASK, .index = ENTROPY_SRC_FW_OV_CONTROL_FW_OV_MODE_OFFSET })
#define ENTROPY_SRC_FW_OV_CONTROL_FW_OV_ENTROPY_INSERT_MASK 0xfu
#define ENTROPY_SRC_FW_OV_CONTROL_FW_OV_ENTROPY_INSERT_OFFSET 4
#define ENTROPY_SRC_FW_OV_CONTROL_FW_OV_ENTROPY_INSERT_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_FW_OV_CONTROL_FW_OV_ENTROPY_INSERT_MASK, .index = ENTROPY_SRC_FW_OV_CONTROL_FW_OV_ENTROPY_INSERT_OFFSET })
 
// Firmware override sha3 block start control register
#define ENTROPY_SRC_FW_OV_SHA3_START_REG_OFFSET 0x98
#define ENTROPY_SRC_FW_OV_SHA3_START_REG_RESVAL 0x9u
#define ENTROPY_SRC_FW_OV_SHA3_START_FW_OV_INSERT_START_MASK 0xfu
#define ENTROPY_SRC_FW_OV_SHA3_START_FW_OV_INSERT_START_OFFSET 0
#define ENTROPY_SRC_FW_OV_SHA3_START_FW_OV_INSERT_START_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_FW_OV_SHA3_START_FW_OV_INSERT_START_MASK, .index = ENTROPY_SRC_FW_OV_SHA3_START_FW_OV_INSERT_START_OFFSET })
 
// Firmware override FIFO write full status register
#define ENTROPY_SRC_FW_OV_WR_FIFO_FULL_REG_OFFSET 0x9c
#define ENTROPY_SRC_FW_OV_WR_FIFO_FULL_REG_RESVAL 0x0u
#define ENTROPY_SRC_FW_OV_WR_FIFO_FULL_FW_OV_WR_FIFO_FULL_BIT 0
 
// Firmware override observe FIFO overflow status
#define ENTROPY_SRC_FW_OV_RD_FIFO_OVERFLOW_REG_OFFSET 0xa0
#define ENTROPY_SRC_FW_OV_RD_FIFO_OVERFLOW_REG_RESVAL 0x0u
#define ENTROPY_SRC_FW_OV_RD_FIFO_OVERFLOW_FW_OV_RD_FIFO_OVERFLOW_BIT 0
 
// Firmware override observe FIFO read register
#define ENTROPY_SRC_FW_OV_RD_DATA_REG_OFFSET 0xa4
#define ENTROPY_SRC_FW_OV_RD_DATA_REG_RESVAL 0x0u
 
// Firmware override FIFO write register
#define ENTROPY_SRC_FW_OV_WR_DATA_REG_OFFSET 0xa8
#define ENTROPY_SRC_FW_OV_WR_DATA_REG_RESVAL 0x0u
 
// Observe FIFO threshold register
#define ENTROPY_SRC_OBSERVE_FIFO_THRESH_REG_OFFSET 0xac
#define ENTROPY_SRC_OBSERVE_FIFO_THRESH_REG_RESVAL 0x10u
#define ENTROPY_SRC_OBSERVE_FIFO_THRESH_OBSERVE_FIFO_THRESH_MASK 0x3fu
#define ENTROPY_SRC_OBSERVE_FIFO_THRESH_OBSERVE_FIFO_THRESH_OFFSET 0
#define ENTROPY_SRC_OBSERVE_FIFO_THRESH_OBSERVE_FIFO_THRESH_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_OBSERVE_FIFO_THRESH_OBSERVE_FIFO_THRESH_MASK, .index = ENTROPY_SRC_OBSERVE_FIFO_THRESH_OBSERVE_FIFO_THRESH_OFFSET })
 
// Observe FIFO depth register
#define ENTROPY_SRC_OBSERVE_FIFO_DEPTH_REG_OFFSET 0xb0
#define ENTROPY_SRC_OBSERVE_FIFO_DEPTH_REG_RESVAL 0x0u
#define ENTROPY_SRC_OBSERVE_FIFO_DEPTH_OBSERVE_FIFO_DEPTH_MASK 0x3fu
#define ENTROPY_SRC_OBSERVE_FIFO_DEPTH_OBSERVE_FIFO_DEPTH_OFFSET 0
#define ENTROPY_SRC_OBSERVE_FIFO_DEPTH_OBSERVE_FIFO_DEPTH_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_OBSERVE_FIFO_DEPTH_OBSERVE_FIFO_DEPTH_MASK, .index = ENTROPY_SRC_OBSERVE_FIFO_DEPTH_OBSERVE_FIFO_DEPTH_OFFSET })
 
// Debug status register
#define ENTROPY_SRC_DEBUG_STATUS_REG_OFFSET 0xb4
#define ENTROPY_SRC_DEBUG_STATUS_REG_RESVAL 0x10000u
#define ENTROPY_SRC_DEBUG_STATUS_ENTROPY_FIFO_DEPTH_MASK 0x3u
#define ENTROPY_SRC_DEBUG_STATUS_ENTROPY_FIFO_DEPTH_OFFSET 0
#define ENTROPY_SRC_DEBUG_STATUS_ENTROPY_FIFO_DEPTH_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_DEBUG_STATUS_ENTROPY_FIFO_DEPTH_MASK, .index = ENTROPY_SRC_DEBUG_STATUS_ENTROPY_FIFO_DEPTH_OFFSET })
#define ENTROPY_SRC_DEBUG_STATUS_SHA3_FSM_MASK 0x7u
#define ENTROPY_SRC_DEBUG_STATUS_SHA3_FSM_OFFSET 3
#define ENTROPY_SRC_DEBUG_STATUS_SHA3_FSM_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_DEBUG_STATUS_SHA3_FSM_MASK, .index = ENTROPY_SRC_DEBUG_STATUS_SHA3_FSM_OFFSET })
#define ENTROPY_SRC_DEBUG_STATUS_SHA3_BLOCK_PR_BIT 6
#define ENTROPY_SRC_DEBUG_STATUS_SHA3_SQUEEZING_BIT 7
#define ENTROPY_SRC_DEBUG_STATUS_SHA3_ABSORBED_BIT 8
#define ENTROPY_SRC_DEBUG_STATUS_SHA3_ERR_BIT 9
#define ENTROPY_SRC_DEBUG_STATUS_MAIN_SM_IDLE_BIT 16
#define ENTROPY_SRC_DEBUG_STATUS_MAIN_SM_BOOT_DONE_BIT 17
 
// Recoverable alert status register
#define ENTROPY_SRC_RECOV_ALERT_STS_REG_OFFSET 0xb8
#define ENTROPY_SRC_RECOV_ALERT_STS_REG_RESVAL 0x0u
#define ENTROPY_SRC_RECOV_ALERT_STS_FIPS_ENABLE_FIELD_ALERT_BIT 0
#define ENTROPY_SRC_RECOV_ALERT_STS_ENTROPY_DATA_REG_EN_FIELD_ALERT_BIT 1
#define ENTROPY_SRC_RECOV_ALERT_STS_MODULE_ENABLE_FIELD_ALERT_BIT 2
#define ENTROPY_SRC_RECOV_ALERT_STS_THRESHOLD_SCOPE_FIELD_ALERT_BIT 3
#define ENTROPY_SRC_RECOV_ALERT_STS_THRESHOLD_ONEWAY_FIELD_ALERT_BIT 4
#define ENTROPY_SRC_RECOV_ALERT_STS_RNG_BIT_ENABLE_FIELD_ALERT_BIT 5
#define ENTROPY_SRC_RECOV_ALERT_STS_FW_OV_SHA3_START_FIELD_ALERT_BIT 7
#define ENTROPY_SRC_RECOV_ALERT_STS_FW_OV_MODE_FIELD_ALERT_BIT 8
#define ENTROPY_SRC_RECOV_ALERT_STS_FW_OV_ENTROPY_INSERT_FIELD_ALERT_BIT 9
#define ENTROPY_SRC_RECOV_ALERT_STS_ES_ROUTE_FIELD_ALERT_BIT 10
#define ENTROPY_SRC_RECOV_ALERT_STS_ES_TYPE_FIELD_ALERT_BIT 11
#define ENTROPY_SRC_RECOV_ALERT_STS_ES_MAIN_SM_ALERT_BIT 12
#define ENTROPY_SRC_RECOV_ALERT_STS_ES_BUS_CMP_ALERT_BIT 13
#define ENTROPY_SRC_RECOV_ALERT_STS_ES_THRESH_CFG_ALERT_BIT 14
#define ENTROPY_SRC_RECOV_ALERT_STS_ES_FW_OV_WR_ALERT_BIT 15
#define ENTROPY_SRC_RECOV_ALERT_STS_ES_FW_OV_DISABLE_ALERT_BIT 16
#define ENTROPY_SRC_RECOV_ALERT_STS_FIPS_FLAG_FIELD_ALERT_BIT 17
#define ENTROPY_SRC_RECOV_ALERT_STS_RNG_FIPS_FIELD_ALERT_BIT 18
#define ENTROPY_SRC_RECOV_ALERT_STS_POSTHT_ENTROPY_DROP_ALERT_BIT 31
 
// Hardware detection of error conditions status register
#define ENTROPY_SRC_ERR_CODE_REG_OFFSET 0xbc
#define ENTROPY_SRC_ERR_CODE_REG_RESVAL 0x0u
#define ENTROPY_SRC_ERR_CODE_SFIFO_ESRNG_ERR_BIT 0
#define ENTROPY_SRC_ERR_CODE_SFIFO_DISTR_ERR_BIT 1
#define ENTROPY_SRC_ERR_CODE_SFIFO_OBSERVE_ERR_BIT 2
#define ENTROPY_SRC_ERR_CODE_SFIFO_ESFINAL_ERR_BIT 3
#define ENTROPY_SRC_ERR_CODE_ES_ACK_SM_ERR_BIT 20
#define ENTROPY_SRC_ERR_CODE_ES_MAIN_SM_ERR_BIT 21
#define ENTROPY_SRC_ERR_CODE_ES_CNTR_ERR_BIT 22
#define ENTROPY_SRC_ERR_CODE_SHA3_STATE_ERR_BIT 23
#define ENTROPY_SRC_ERR_CODE_SHA3_RST_STORAGE_ERR_BIT 24
#define ENTROPY_SRC_ERR_CODE_FIFO_WRITE_ERR_BIT 28
#define ENTROPY_SRC_ERR_CODE_FIFO_READ_ERR_BIT 29
#define ENTROPY_SRC_ERR_CODE_FIFO_STATE_ERR_BIT 30
 
// Test error conditions register
#define ENTROPY_SRC_ERR_CODE_TEST_REG_OFFSET 0xc0
#define ENTROPY_SRC_ERR_CODE_TEST_REG_RESVAL 0x0u
#define ENTROPY_SRC_ERR_CODE_TEST_ERR_CODE_TEST_MASK 0x1fu
#define ENTROPY_SRC_ERR_CODE_TEST_ERR_CODE_TEST_OFFSET 0
#define ENTROPY_SRC_ERR_CODE_TEST_ERR_CODE_TEST_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_ERR_CODE_TEST_ERR_CODE_TEST_MASK, .index = ENTROPY_SRC_ERR_CODE_TEST_ERR_CODE_TEST_OFFSET })
 
// Main state machine state debug register
#define ENTROPY_SRC_MAIN_SM_STATE_REG_OFFSET 0xc4
#define ENTROPY_SRC_MAIN_SM_STATE_REG_RESVAL 0xf5u
#define ENTROPY_SRC_MAIN_SM_STATE_MAIN_SM_STATE_MASK 0x1ffu
#define ENTROPY_SRC_MAIN_SM_STATE_MAIN_SM_STATE_OFFSET 0
#define ENTROPY_SRC_MAIN_SM_STATE_MAIN_SM_STATE_FIELD \
  ((bitfield_field32_t) { .mask = ENTROPY_SRC_MAIN_SM_STATE_MAIN_SM_STATE_MASK, .index = ENTROPY_SRC_MAIN_SM_STATE_MAIN_SM_STATE_OFFSET })
 
#ifdef __cplusplus
}  // extern "C"
#endif
#endif  // _ENTROPY_SRC_REG_DEFS_
// End generated register defines for entropy_src