Software APIs
spi_device.h
Go to the documentation of this file.
1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Device table API auto-generated by `dtgen`
6
7#ifndef OPENTITAN_DT_SPI_DEVICE_H_
8#define OPENTITAN_DT_SPI_DEVICE_H_
9
10#ifdef __cplusplus
11extern "C" {
12#endif // __cplusplus
13
14/**
15 * @file
16 * @brief Device Tables (DT) for IP spi_device and top earlgrey.
17 *
18 * This file contains the type definitions and global functions of the spi_device.
19 */
20
21#include "hw/top/dt/api.h"
22#include <stdint.h>
23
24
25
26/**
27 * List of instances.
28 */
29typedef enum dt_spi_device {
30 kDtSpiDeviceFirst = 0, /**< First instance */
31 kDtSpiDevice = 0, /**< spi_device */
33
34enum {
35 kDtSpiDeviceCount = 1, /**< Number of instances */
36};
37
38
39/**
40 * List of register blocks.
41 *
42 * Register blocks are guaranteed to start at 0 and to be consecutively numbered.
43 */
45 kDtSpiDeviceRegBlockCore = 0, /**< */
47
48enum {
49 kDtSpiDeviceRegBlockCount = 1, /**< Number of register blocks */
50};
51
52
53/** Primary register block (associated with the "primary" set of registers that control the IP). */
54static const dt_spi_device_reg_block_t kDtSpiDeviceRegBlockPrimary = kDtSpiDeviceRegBlockCore;
55
56/**
57 * List of IRQs.
58 *
59 * IRQs are guaranteed to be numbered consecutively from 0.
60 */
61typedef enum dt_spi_device_irq {
62 kDtSpiDeviceIrqUploadCmdfifoNotEmpty = 0, /**< Upload Command FIFO is not empty */
63 kDtSpiDeviceIrqUploadPayloadNotEmpty = 1, /**< Upload payload is not empty.
64
65 The event occurs after SPI transaction completed */
66 kDtSpiDeviceIrqUploadPayloadOverflow = 2, /**< Upload payload overflow event.
67
68 When a SPI Host system issues a command with payload more than 256B,
69 this event is reported. When it happens, SW should read the last
70 written payload index CSR to figure out the starting address of the
71 last 256B. */
72 kDtSpiDeviceIrqReadbufWatermark = 3, /**< Read Buffer Threshold event.
73
74 The host system accesses greater than or equal to the threshold of a
75 buffer. */
76 kDtSpiDeviceIrqReadbufFlip = 4, /**< Read buffer flipped event.
77
78 The host system accesses other side of buffer. */
79 kDtSpiDeviceIrqTpmHeaderNotEmpty = 5, /**< TPM Header(Command/Address) buffer available */
80 kDtSpiDeviceIrqTpmRdfifoCmdEnd = 6, /**< TPM RdFIFO command ended.
81
82 The TPM Read command targeting the RdFIFO ended.
83 Check TPM_STATUS.rdfifo_aborted to see if the transaction completed. */
84 kDtSpiDeviceIrqTpmRdfifoDrop = 7, /**< TPM RdFIFO data dropped.
85
86 Data was dropped from the RdFIFO.
87 Data was written while a read command was not active, and it was not accepted.
88 This can occur when the host aborts a read command. */
90
91enum {
92 kDtSpiDeviceIrqCount = 8, /**< Number of IRQs */
93};
94
95
96/**
97 * List of Alerts.
98 *
99 * Alerts are guaranteed to be numbered consecutively from 0.
100 */
102 kDtSpiDeviceAlertFatalFault = 0, /**< This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. */
104
105enum {
106 kDtSpiDeviceAlertCount = 1, /**< Number of Alerts */
107};
108
109
110/**
111 * List of clock ports.
112 *
113 * Clock ports are guaranteed to be numbered consecutively from 0.
114 */
116 kDtSpiDeviceClockClk = 0, /**< Clock port clk_i */
118
119enum {
120 kDtSpiDeviceClockCount = 1, /**< Number of clock ports */
121};
122
123
124/**
125 * List of reset ports.
126 *
127 * Reset ports are guaranteed to be numbered consecutively from 0.
128 */
130 kDtSpiDeviceResetRst = 0, /**< Reset port rst_ni */
132
133enum {
134 kDtSpiDeviceResetCount = 1, /**< Number of reset ports */
135};
136
137
138/**
139 * List of peripheral I/O.
140 *
141 * Peripheral I/O are guaranteed to be numbered consecutively from 0.
142 */
144 kDtSpiDevicePeriphIoSck = 0, /**< */
145 kDtSpiDevicePeriphIoCsb = 1, /**< */
146 kDtSpiDevicePeriphIoTpmCsb = 2, /**< */
147 kDtSpiDevicePeriphIoSd0 = 3, /**< */
148 kDtSpiDevicePeriphIoSd1 = 4, /**< */
149 kDtSpiDevicePeriphIoSd2 = 5, /**< */
150 kDtSpiDevicePeriphIoSd3 = 6, /**< */
152
153enum {
154 kDtSpiDevicePeriphIoCount = 7, /**< Number of peripheral I/O */
155};
156
157
158/**
159 * List of supported hardware features.
160 */
161#define OPENTITAN_SPI_DEVICE_HAS_MODE_FLASH_EMULATION 1
162#define OPENTITAN_SPI_DEVICE_HAS_MODE_PASSTHROUGH 1
163#define OPENTITAN_SPI_DEVICE_HAS_MODE_TPM 1
164#define OPENTITAN_SPI_DEVICE_HAS_HW_LANES 1
165#define OPENTITAN_SPI_DEVICE_HAS_HW_SERDES_ORDERING 1
166#define OPENTITAN_SPI_DEVICE_HAS_HW_CSB_STATUS 1
167#define OPENTITAN_SPI_DEVICE_HAS_MODE_FLASH_EMULATION_COMMANDS 1
168#define OPENTITAN_SPI_DEVICE_HAS_HW_FLASH_EMULATION_BLOCKS 1
169#define OPENTITAN_SPI_DEVICE_HAS_MODE_FLASH_EMULATION_READ_COMMAND_PROCESSOR 1
170#define OPENTITAN_SPI_DEVICE_HAS_MODE_FLASH_EMULATION_DUMMY_CYCLE 1
171#define OPENTITAN_SPI_DEVICE_HAS_MODE_FLASH_EMULATION_WRITE_ENABLE_DISABLE 1
172#define OPENTITAN_SPI_DEVICE_HAS_HW_LAST_READ_ADDR 1
173#define OPENTITAN_SPI_DEVICE_HAS_HW_CMDINFOS 1
174#define OPENTITAN_SPI_DEVICE_HAS_HW_COMMAND_UPLOAD 1
175#define OPENTITAN_SPI_DEVICE_HAS_HW_3B4B_ADDRESSING 1
176#define OPENTITAN_SPI_DEVICE_HAS_MODE_PASSTHROUGH_CMD_FILTER 1
177#define OPENTITAN_SPI_DEVICE_HAS_MODE_PASSTHROUGH_ADDRESS_MANIPULATION 1
178#define OPENTITAN_SPI_DEVICE_HAS_MODE_PASSTHROUGH_STATUS_MANIPULATION 1
179#define OPENTITAN_SPI_DEVICE_HAS_MODE_PASSTHROUGH_OUTPUT_ENABLE_CONTROL 1
180#define OPENTITAN_SPI_DEVICE_HAS_MODE_PASSTHROUGH_INTERCEPT_EN 1
181#define OPENTITAN_SPI_DEVICE_HAS_MODE_PASSTHROUGH_MAILBOX 1
182#define OPENTITAN_SPI_DEVICE_HAS_MODE_TPM_RETURN_BY_HW_REGS 1
183#define OPENTITAN_SPI_DEVICE_HAS_MODE_TPM_AUTO_WAIT 1
184#define OPENTITAN_SPI_DEVICE_HAS_MODE_TPM_READ_FIFO_MODE 1
185#define OPENTITAN_SPI_DEVICE_HAS_MODE_TPM_CAPABILITY 1
186
187
188
189/**
190 * Get the spi_device instance from an instance ID
191 *
192 * For example, `dt_uart_from_instance_id(kDtInstanceIdUart3) == kDtUart3`.
193 *
194 * @param inst_id Instance ID.
195 * @return A spi_device instance.
196 *
197 * **Note:** This function only makes sense if the instance ID has device type spi_device,
198 * otherwise the returned value is unspecified.
199 */
201
202/**
203 * Get the instance ID of an instance.
204 *
205 * @param dt Instance of spi_device.
206 * @return The instance ID of that instance.
207 */
209
210/**
211 * Get the register base address of an instance.
212 *
213 * @param dt Instance of spi_device.
214 * @param reg_block The register block requested.
215 * @return The register base address of the requested block.
216 */
219 dt_spi_device_reg_block_t reg_block);
220
221/**
222 * Get the primary register base address of an instance.
223 *
224 * This is just a convenience function, equivalent to
225 * `dt_spi_device_reg_block(dt, kDtSpiDeviceRegBlockCore)`
226 *
227 * @param dt Instance of spi_device.
228 * @return The register base address of the primary register block.
229 */
230static inline uint32_t dt_spi_device_primary_reg_block(
231 dt_spi_device_t dt) {
232 return dt_spi_device_reg_block(dt, kDtSpiDeviceRegBlockCore);
233}
234
235/**
236 * Get the PLIC ID of a spi_device IRQ for a given instance.
237 *
238 * If the instance is not connected to the PLIC, this function
239 * will return `kDtPlicIrqIdNone`.
240 *
241 * @param dt Instance of spi_device.
242 * @param irq A spi_device IRQ.
243 * @return The PLIC ID of the IRQ of this instance.
244 */
248
249/**
250 * Convert a global IRQ ID to a local spi_device IRQ type.
251 *
252 * @param dt Instance of spi_device.
253 * @param irq A PLIC ID that belongs to this instance.
254 * @return The spi_device IRQ, or `kDtSpiDeviceIrqCount`.
255 *
256 * **Note:** This function assumes that the PLIC ID belongs to the instance
257 * of spi_device passed in parameter. In other words, it must be the case that
258 * `dt_spi_device_instance_id(dt) == dt_plic_id_to_instance_id(irq)`. Otherwise, this function
259 * will return `kDtSpiDeviceIrqCount`.
260 */
263 dt_plic_irq_id_t irq);
264
265
266/**
267 * Get the alert ID of a spi_device alert for a given instance.
268 *
269 * **Note:** This function only makes sense if the instance is connected to the Alert Handler. For any
270 * instances where the instance is not connected, the return value is unspecified.
271 *
272 * @param dt Instance of spi_device.
273 * @param alert A spi_device alert.
274 * @return The Alert Handler alert ID of the alert of this instance.
275 */
279
280/**
281 * Convert a global alert ID to a local spi_device alert type.
282 *
283 * @param dt Instance of spi_device.
284 * @param alert A global alert ID that belongs to this instance.
285 * @return The spi_device alert, or `kDtSpiDeviceAlertCount`.
286 *
287 * **Note:** This function assumes that the global alert ID belongs to the
288 * instance of spi_device passed in parameter. In other words, it must be the case
289 * that `dt_spi_device_instance_id(dt) == dt_alert_id_to_instance_id(alert)`. Otherwise,
290 * this function will return `kDtSpiDeviceAlertCount`.
291 */
294 dt_alert_id_t alert);
295
296
297/**
298 * Get the peripheral I/O description of an instance.
299 *
300 * @param dt Instance of spi_device.
301 * @param sig Requested peripheral I/O.
302 * @return Description of the requested peripheral I/O for this instance.
303 */
307
308/**
309 * Get the clock signal connected to a clock port of an instance.
310 *
311 * @param dt Instance of spi_device.
312 * @param clk Clock port.
313 * @return Clock signal.
314 */
318
319/**
320 * Get the reset signal connected to a reset port of an instance.
321 *
322 * @param dt Instance of spi_device.
323 * @param rst Reset port.
324 * @return Reset signal.
325 */
329
330
331
332#ifdef __cplusplus
333} // extern "C"
334#endif // __cplusplus
335
336#endif // OPENTITAN_DT_SPI_DEVICE_H_