Software APIs
rom_ctrl.h
Go to the documentation of this file.
1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Device table API auto-generated by `dtgen`
6
7#ifndef OPENTITAN_DT_ROM_CTRL_H_
8#define OPENTITAN_DT_ROM_CTRL_H_
9
10#ifdef __cplusplus
11extern "C" {
12#endif // __cplusplus
13
14/**
15 * @file
16 * @brief Device Tables (DT) for IP rom_ctrl and top earlgrey.
17 *
18 * This file contains the type definitions and global functions of the rom_ctrl.
19 */
20
21#include "hw/top/dt/api.h"
22#include <stdint.h>
23
24
25
26/**
27 * List of instances.
28 */
29typedef enum dt_rom_ctrl {
30 kDtRomCtrlFirst = 0, /**< First instance */
31 kDtRomCtrl = 0, /**< rom_ctrl */
33
34enum {
35 kDtRomCtrlCount = 1, /**< Number of instances */
36};
37
38
39/**
40 * List of register blocks.
41 *
42 * Register blocks are guaranteed to start at 0 and to be consecutively numbered.
43 */
45 kDtRomCtrlRegBlockRegs = 0, /**< */
47
48enum {
49 kDtRomCtrlRegBlockCount = 1, /**< Number of register blocks */
50};
51
52
53/** Primary register block (associated with the "primary" set of registers that control the IP). */
54static const dt_rom_ctrl_reg_block_t kDtRomCtrlRegBlockPrimary = kDtRomCtrlRegBlockRegs;
55
56/**
57 * List of memories.
58 *
59 * Memories are guaranteed to start at 0 and to be consecutively numbered.
60 */
61typedef enum dt_rom_ctrl_memory {
62 kDtRomCtrlMemoryRom = 0, /**< */
64
65enum {
66 kDtRomCtrlMemoryCount = 1, /**< Number of memories */
67};
68
69
70/**
71 * List of Alerts.
72 *
73 * Alerts are guaranteed to be numbered consecutively from 0.
74 */
75typedef enum dt_rom_ctrl_alert {
76 kDtRomCtrlAlertFatal = 0, /**< A fatal error. Fatal alerts are non-recoverable and will be asserted until a hard reset. */
78
79enum {
80 kDtRomCtrlAlertCount = 1, /**< Number of Alerts */
81};
82
83
84/**
85 * List of clock ports.
86 *
87 * Clock ports are guaranteed to be numbered consecutively from 0.
88 */
89typedef enum dt_rom_ctrl_clock {
90 kDtRomCtrlClockClk = 0, /**< Clock port clk_i */
92
93enum {
94 kDtRomCtrlClockCount = 1, /**< Number of clock ports */
95};
96
97
98/**
99 * List of reset ports.
100 *
101 * Reset ports are guaranteed to be numbered consecutively from 0.
102 */
103typedef enum dt_rom_ctrl_reset {
104 kDtRomCtrlResetRst = 0, /**< Reset port rst_ni */
106
107enum {
108 kDtRomCtrlResetCount = 1, /**< Number of reset ports */
109};
110
111
112/**
113 * List of supported hardware features.
114 */
115#define OPENTITAN_ROM_CTRL_HAS_SCRAMBLED 1
116#define OPENTITAN_ROM_CTRL_HAS_DIGESTS 1
117#define OPENTITAN_ROM_CTRL_HAS_EXP_DIGESTS 1
118
119
120
121/**
122 * Get the rom_ctrl instance from an instance ID
123 *
124 * For example, `dt_uart_from_instance_id(kDtInstanceIdUart3) == kDtUart3`.
125 *
126 * @param inst_id Instance ID.
127 * @return A rom_ctrl instance.
128 *
129 * **Note:** This function only makes sense if the instance ID has device type rom_ctrl,
130 * otherwise the returned value is unspecified.
131 */
133
134/**
135 * Get the instance ID of an instance.
136 *
137 * @param dt Instance of rom_ctrl.
138 * @return The instance ID of that instance.
139 */
141
142/**
143 * Get the register base address of an instance.
144 *
145 * @param dt Instance of rom_ctrl.
146 * @param reg_block The register block requested.
147 * @return The register base address of the requested block.
148 */
149uint32_t dt_rom_ctrl_reg_block(
150 dt_rom_ctrl_t dt,
151 dt_rom_ctrl_reg_block_t reg_block);
152
153/**
154 * Get the primary register base address of an instance.
155 *
156 * This is just a convenience function, equivalent to
157 * `dt_rom_ctrl_reg_block(dt, kDtRomCtrlRegBlockRegs)`
158 *
159 * @param dt Instance of rom_ctrl.
160 * @return The register base address of the primary register block.
161 */
162static inline uint32_t dt_rom_ctrl_primary_reg_block(
163 dt_rom_ctrl_t dt) {
164 return dt_rom_ctrl_reg_block(dt, kDtRomCtrlRegBlockRegs);
165}
166
167/**
168 * Get the base address of a memory.
169 *
170 * @param dt Instance of rom_ctrl.
171 * @param mem The memory requested.
172 * @return The base address of the requested memory.
173 */
175 dt_rom_ctrl_t dt,
177
178/**
179 * Get the size of a memory.
180 *
181 * @param dt Instance of rom_ctrl.
182 * @param mem The memory requested.
183 * @return The size of the requested memory.
184 */
186 dt_rom_ctrl_t dt,
188
189
190/**
191 * Get the alert ID of a rom_ctrl alert for a given instance.
192 *
193 * **Note:** This function only makes sense if the instance is connected to the Alert Handler. For any
194 * instances where the instance is not connected, the return value is unspecified.
195 *
196 * @param dt Instance of rom_ctrl.
197 * @param alert A rom_ctrl alert.
198 * @return The Alert Handler alert ID of the alert of this instance.
199 */
201 dt_rom_ctrl_t dt,
202 dt_rom_ctrl_alert_t alert);
203
204/**
205 * Convert a global alert ID to a local rom_ctrl alert type.
206 *
207 * @param dt Instance of rom_ctrl.
208 * @param alert A global alert ID that belongs to this instance.
209 * @return The rom_ctrl alert, or `kDtRomCtrlAlertCount`.
210 *
211 * **Note:** This function assumes that the global alert ID belongs to the
212 * instance of rom_ctrl passed in parameter. In other words, it must be the case
213 * that `dt_rom_ctrl_instance_id(dt) == dt_alert_id_to_instance_id(alert)`. Otherwise,
214 * this function will return `kDtRomCtrlAlertCount`.
215 */
217 dt_rom_ctrl_t dt,
218 dt_alert_id_t alert);
219
220
221
222/**
223 * Get the clock signal connected to a clock port of an instance.
224 *
225 * @param dt Instance of rom_ctrl.
226 * @param clk Clock port.
227 * @return Clock signal.
228 */
230 dt_rom_ctrl_t dt,
232
233/**
234 * Get the reset signal connected to a reset port of an instance.
235 *
236 * @param dt Instance of rom_ctrl.
237 * @param rst Reset port.
238 * @return Reset signal.
239 */
241 dt_rom_ctrl_t dt,
243
244
245
246#ifdef __cplusplus
247} // extern "C"
248#endif // __cplusplus
249
250#endif // OPENTITAN_DT_ROM_CTRL_H_