Software APIs
dt_uart.h
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Device table API auto-generated by `dtgen`
6
7#ifndef OPENTITAN_DT_UART_H_
8#define OPENTITAN_DT_UART_H_
9
10#ifdef __cplusplus
11extern "C" {
12#endif // __cplusplus
13
14/**
15 * @file
16 * @brief Device Tables (DT) for IP uart and top earlgrey.
17 *
18 * This file contains the type definitions and global functions of the uart.
19 */
20
21#include "hw/top/dt/dt_api.h"
22#include <stdint.h>
23
24
25
26/**
27 * List of instances.
28 */
29typedef enum dt_uart {
30 kDtUart0 = 0, /**< uart0 */
31 kDtUart1 = 1, /**< uart1 */
32 kDtUart2 = 2, /**< uart2 */
33 kDtUart3 = 3, /**< uart3 */
34 kDtUartFirst = 0, /**< \internal First instance */
35 kDtUartCount = 4, /**< \internal Number of instances */
37
38/**
39 * List of register blocks.
40 *
41 * Register blocks are guaranteed to start at 0 and to be consecutively numbered.
42 */
43typedef enum dt_uart_reg_block {
44 kDtUartRegBlockCore = 0, /**< */
45 kDtUartRegBlockCount = 1, /**< \internal Number of register blocks */
47
48/** Primary register block (associated with the "primary" set of registers that control the IP). */
49static const dt_uart_reg_block_t kDtUartRegBlockPrimary = kDtUartRegBlockCore;
50
51/**
52 * List of memories.
53 *
54 * Memories are guaranteed to start at 0 and to be consecutively numbered.
55 */
56typedef enum dt_uart_memory {
57 kDtUartMemoryCount = 0, /**< \internal Number of memories */
59
60/**
61 * List of IRQs.
62 *
63 * IRQs are guaranteed to be numbered consecutively from 0.
64 */
65typedef enum dt_uart_irq {
66 kDtUartIrqTxWatermark = 0, /**< raised if the transmit FIFO is past the high-water mark. */
67 kDtUartIrqRxWatermark = 1, /**< raised if the receive FIFO is past the high-water mark. */
68 kDtUartIrqTxDone = 2, /**< raised if the transmit FIFO has emptied and no transmit is ongoing. */
69 kDtUartIrqRxOverflow = 3, /**< raised if the receive FIFO has overflowed. */
70 kDtUartIrqRxFrameErr = 4, /**< raised if a framing error has been detected on receive. */
71 kDtUartIrqRxBreakErr = 5, /**< raised if break condition has been detected on receive. */
72 kDtUartIrqRxTimeout = 6, /**< raised if RX FIFO has characters remaining in the FIFO without being
73retrieved for the programmed time period. */
74 kDtUartIrqRxParityErr = 7, /**< raised if the receiver has detected a parity error. */
75 kDtUartIrqTxEmpty = 8, /**< raised if the transmit FIFO is empty. */
76 kDtUartIrqCount = 9, /**< \internal Number of IRQs */
78
79/**
80 * List of Alerts.
81 *
82 * Alerts are guaranteed to be numbered consecutively from 0.
83 */
84typedef enum dt_uart_alert {
85 kDtUartAlertFatalFault = 0, /**< This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. */
86 kDtUartAlertCount = 1, /**< \internal Number of Alerts */
88
89/**
90 * List of clock ports.
91 *
92 * Clock ports are guaranteed to be numbered consecutively from 0.
93 */
94typedef enum dt_uart_clock {
95 kDtUartClockClk = 0, /**< Clock port clk_i */
96 kDtUartClockCount = 1, /**< \internal Number of clock ports */
98
99/**
100 * List of reset ports.
101 *
102 * Reset ports are guaranteed to be numbered consecutively from 0.
103 */
104typedef enum dt_uart_reset {
105 kDtUartResetRst = 0, /**< Reset port rst_ni */
106 kDtUartResetCount = 1, /**< \internal Number of reset ports */
108
109/**
110 * List of peripheral I/O.
111 *
112 * Peripheral I/O are guaranteed to be numbered consecutively from 0.
113 */
114typedef enum dt_uart_periph_io {
115 kDtUartPeriphIoRx = 0, /**< */
116 kDtUartPeriphIoTx = 1, /**< */
117 kDtUartPeriphIoCount = 2, /**< \internal Number of peripheral I/O */
119
120/**
121 * List of supported hardware features.
122 */
123#define OPENTITAN_UART_HAS_PARITY 1
124#define OPENTITAN_UART_HAS_LINE_LOOPBACK 1
125#define OPENTITAN_UART_HAS_SYSTEM_LOOPBACK 1
126#define OPENTITAN_UART_HAS_BAUD_RATE_CONTROL 1
127#define OPENTITAN_UART_HAS_LINE_BREAK 1
128#define OPENTITAN_UART_HAS_FIFO_INTERRUPTS 1
129
130
131
132/**
133 * Get the uart instance from an instance ID
134 *
135 * For example, `dt_uart_from_instance_id(kDtInstanceIdUart3) == kDtUart3`.
136 *
137 * @param inst_id Instance ID.
138 * @return A uart instance.
139 *
140 * **Note:** This function only makes sense if the instance ID has device type uart,
141 * otherwise the returned value is unspecified.
142 */
144
145/**
146 * Get the instance ID of an instance.
147 *
148 * @param dt Instance of uart.
149 * @return The instance ID of that instance.
150 */
152
153/**
154 * Get the register base address of an instance.
155 *
156 * @param dt Instance of uart.
157 * @param reg_block The register block requested.
158 * @return The register base address of the requested block.
159 */
160uint32_t dt_uart_reg_block(
161 dt_uart_t dt,
162 dt_uart_reg_block_t reg_block);
163
164/**
165 * Get the primary register base address of an instance.
166 *
167 * This is just a convenience function, equivalent to
168 * `dt_uart_reg_block(dt, kDtUartRegBlockCore)`
169 *
170 * @param dt Instance of uart.
171 * @return The register base address of the primary register block.
172 */
173static inline uint32_t dt_uart_primary_reg_block(
174 dt_uart_t dt) {
175 return dt_uart_reg_block(dt, kDtUartRegBlockCore);
176}
177
178/**
179 * Get the base address of a memory.
180 *
181 * @param dt Instance of uart.
182 * @param mem The memory requested.
183 * @return The base address of the requested memory.
184 */
185uint32_t dt_uart_memory_base(
186 dt_uart_t dt,
187 dt_uart_memory_t mem);
188
189/**
190 * Get the size of a memory.
191 *
192 * @param dt Instance of uart.
193 * @param mem The memory requested.
194 * @return The size of the requested memory.
195 */
196uint32_t dt_uart_memory_size(
197 dt_uart_t dt,
198 dt_uart_memory_t mem);
199
200/**
201 * Get the PLIC ID of a uart IRQ for a given instance.
202 *
203 * If the instance is not connected to the PLIC, this function
204 * will return `kDtPlicIrqIdNone`.
205 *
206 * @param dt Instance of uart.
207 * @param irq A uart IRQ.
208 * @return The PLIC ID of the IRQ of this instance.
209 */
211 dt_uart_t dt,
212 dt_uart_irq_t irq);
213
214/**
215 * Convert a global IRQ ID to a local uart IRQ type.
216 *
217 * @param dt Instance of uart.
218 * @param irq A PLIC ID that belongs to this instance.
219 * @return The uart IRQ, or `kDtUartIrqCount`.
220 *
221 * **Note:** This function assumes that the PLIC ID belongs to the instance
222 * of uart passed in parameter. In other words, it must be the case that
223 * `dt_uart_instance_id(dt) == dt_plic_id_to_instance_id(irq)`. Otherwise, this function
224 * will return `kDtUartIrqCount`.
225 */
227 dt_uart_t dt,
228 dt_plic_irq_id_t irq);
229
230
231/**
232 * Get the alert ID of a uart alert for a given instance.
233 *
234 * **Note:** This function only makes sense if the instance is connected to the Alert Handler. For any
235 * instances where the instance is not connected, the return value is unspecified.
236 *
237 * @param dt Instance of uart.
238 * @param alert A uart alert.
239 * @return The Alert Handler alert ID of the alert of this instance.
240 */
242 dt_uart_t dt,
243 dt_uart_alert_t alert);
244
245/**
246 * Convert a global alert ID to a local uart alert type.
247 *
248 * @param dt Instance of uart.
249 * @param alert A global alert ID that belongs to this instance.
250 * @return The uart alert, or `kDtUartAlertCount`.
251 *
252 * **Note:** This function assumes that the global alert ID belongs to the
253 * instance of uart passed in parameter. In other words, it must be the case
254 * that `dt_uart_instance_id(dt) == dt_alert_id_to_instance_id(alert)`. Otherwise,
255 * this function will return `kDtUartAlertCount`.
256 */
258 dt_uart_t dt,
259 dt_alert_id_t alert);
260
261
262/**
263 * Get the peripheral I/O description of an instance.
264 *
265 * @param dt Instance of uart.
266 * @param sig Requested peripheral I/O.
267 * @return Description of the requested peripheral I/O for this instance.
268 */
270 dt_uart_t dt,
272
273/**
274 * Get the clock signal connected to a clock port of an instance.
275 *
276 * @param dt Instance of uart.
277 * @param clk Clock port.
278 * @return Clock signal.
279 */
281 dt_uart_t dt,
282 dt_uart_clock_t clk);
283
284/**
285 * Get the reset signal connected to a reset port of an instance.
286 *
287 * @param dt Instance of uart.
288 * @param rst Reset port.
289 * @return Reset signal.
290 */
292 dt_uart_t dt,
293 dt_uart_reset_t rst);
294
295
296
297#ifdef __cplusplus
298} // extern "C"
299#endif // __cplusplus
300
301#endif // OPENTITAN_DT_UART_H_