Software APIs
dt_sram_ctrl.h
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Device table API auto-generated by `dtgen`
6
7#ifndef OPENTITAN_DT_SRAM_CTRL_H_
8#define OPENTITAN_DT_SRAM_CTRL_H_
9
10/**
11 * @file
12 * @brief Device Tables (DT) for IP sram_ctrl and top earlgrey.
13 *
14 * This file contains the type definitions and global functions of the sram_ctrl.
15 */
16
17#include "dt_api.h"
18#include <stdint.h>
19
20
21
22/**
23 * List of instances.
24 */
25typedef enum dt_sram_ctrl {
26 kDtSramCtrlRetAon = 0, /**< sram_ctrl_ret_aon */
27 kDtSramCtrlMain = 1, /**< sram_ctrl_main */
28 kDtSramCtrlFirst = 0, /**< \internal First instance */
29 kDtSramCtrlCount = 2, /**< \internal Number of instances */
31
32/**
33 * List of register blocks.
34 *
35 * Register blocks are guaranteed to start at 0 and to be consecutively numbered.
36 */
38 kDtSramCtrlRegBlockRegs = 0, /**< */
39 kDtSramCtrlRegBlockRam = 1, /**< */
40 kDtSramCtrlRegBlockCount = 2, /**< \internal Number of register blocks */
42
43/** Primary register block (associated with the "primary" set of registers that control the IP). */
44static const dt_sram_ctrl_reg_block_t kDtSramCtrlRegBlockPrimary = kDtSramCtrlRegBlockRegs;
45
46/**
47 * List of Alerts.
48 *
49 * Alerts are guaranteed to be numbered consecutively from 0.
50 */
51typedef enum dt_sram_ctrl_alert {
52 kDtSramCtrlAlertFatalError = 0, /**< This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected,
53or if the initialization mechanism has reached an invalid state. */
54 kDtSramCtrlAlertCount = 1, /**< \internal Number of Alerts */
56
57/**
58 * List of clock ports.
59 *
60 * Clock ports are guaranteed to be numbered consecutively from 0.
61 */
62typedef enum dt_sram_ctrl_clock {
63 kDtSramCtrlClockClk = 0, /**< Clock port clk_i */
64 kDtSramCtrlClockOtp = 1, /**< Clock port clk_otp_i */
65 kDtSramCtrlClockCount = 2, /**< \internal Number of clock ports */
67
68/**
69 * List of reset ports.
70 *
71 * Reset ports are guaranteed to be numbered consecutively from 0.
72 */
73typedef enum dt_sram_ctrl_reset {
74 kDtSramCtrlResetRst = 0, /**< Reset port rst_ni */
75 kDtSramCtrlResetOtp = 1, /**< Reset port rst_otp_ni */
76 kDtSramCtrlResetCount = 2, /**< \internal Number of reset ports */
78
79/**
80 * List of supported hardware features.
81 */
82#define OPENTITAN_SRAM_CTRL_HAS_INTEGRITY 1
83#define OPENTITAN_SRAM_CTRL_HAS_SCRAMBLED 1
84#define OPENTITAN_SRAM_CTRL_HAS_LOCK_ON_ERROR 1
85#define OPENTITAN_SRAM_CTRL_HAS_MEMSET 1
86#define OPENTITAN_SRAM_CTRL_HAS_FETCH_ALLOW 1
87#define OPENTITAN_SRAM_CTRL_HAS_SUBWORD_ACCESS 1
88#define OPENTITAN_SRAM_CTRL_HAS_REGWEN 1
89
90
91
92/**
93 * Get the sram_ctrl instance from an instance ID
94 *
95 * For example, `dt_uart_from_instance_id(kDtInstanceIdUart3) == kDtUart3`.
96 *
97 * @param inst_id Instance ID.
98 * @return A sram_ctrl instance.
99 *
100 * **Note:** This function only makes sense if the instance ID has device type sram_ctrl,
101 * otherwise the returned value is unspecified.
102 */
104
105/**
106 * Get the instance ID of an instance.
107 *
108 * @param dt Instance of sram_ctrl.
109 * @return The instance ID of that instance.
110 */
112
113/**
114 * Get the register base address of an instance.
115 *
116 * @param dt Instance of sram_ctrl.
117 * @param reg_block The register block requested.
118 * @return The register base address of the requested block.
119 */
122 dt_sram_ctrl_reg_block_t reg_block);
123
124/**
125 * Get the primary register base address of an instance.
126 *
127 * This is just a convenience function, equivalent to
128 * `dt_sram_ctrl_reg_block(dt, kDtSramCtrlRegBlockRegs)`
129 *
130 * @param dt Instance of sram_ctrl.
131 * @return The register base address of the primary register block.
132 */
133static inline uint32_t dt_sram_ctrl_primary_reg_block(
134 dt_sram_ctrl_t dt) {
135 return dt_sram_ctrl_reg_block(dt, kDtSramCtrlRegBlockRegs);
136}
137
138
139/**
140 * Get the alert ID of a sram_ctrl alert for a given instance.
141 *
142 * **Note:** This function only makes sense if the instance is connected to the Alert Handler. For any
143 * instances where the instance is not connected, the return value is unspecified.
144 *
145 * @param dt Instance of sram_ctrl.
146 * @param alert A sram_ctrl alert.
147 * @return The Alert Handler alert ID of the alert of this instance.
148 */
152
153/**
154 * Convert a global alert ID to a local sram_ctrl alert type.
155 *
156 * @param dt Instance of sram_ctrl.
157 * @param alert A global alert ID that belongs to this instance.
158 * @return The sram_ctrl alert, or `kDtSramCtrlAlertCount`.
159 *
160 * **Note:** This function assumes that the global alert ID belongs to the
161 * instance of sram_ctrl passed in parameter. In other words, it must be the case
162 * that `dt_sram_ctrl_instance_id(dt) == dt_alert_id_to_instance_id(alert)`. Otherwise,
163 * this function will return `kDtSramCtrlAlertCount`.
164 */
167 dt_alert_id_t alert);
168
169
170
171/**
172 * Get the clock signal connected to a clock port of an instance.
173 *
174 * @param dt Instance of sram_ctrl.
175 * @param clk Clock port.
176 * @return Clock signal.
177 */
181
182/**
183 * Get the reset signal connected to a reset port of an instance.
184 *
185 * @param dt Instance of sram_ctrl.
186 * @param rst Reset port.
187 * @return Reset signal.
188 */
192
193
194
195#endif // OPENTITAN_DT_SRAM_CTRL_H_