dt_rstmgr.h

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// Copyright lowRISC contributors (OpenTitan project).
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Device table API auto-generated by `dtgen`
 
#ifndef OPENTITAN_DT_RSTMGR_H_
#define OPENTITAN_DT_RSTMGR_H_
 
#ifdef __cplusplus
extern "C" {
#endif  // __cplusplus
 
/**
 * @file
 * @brief Device Tables (DT) for IP rstmgr and top earlgrey.
 *
 * This file contains the type definitions and global functions of the rstmgr.
 */
 
#include "hw/top/dt/dt_api.h"
#include <stdint.h>
 
 
 
 
 
/**
 * List of instances.
 */
typedef enum dt_rstmgr {
  kDtRstmgrAon = 0, /**< rstmgr_aon */
  kDtRstmgrFirst = 0, /**< \internal First instance */
  kDtRstmgrCount = 1, /**< \internal Number of instances */
} dt_rstmgr_t;
 
/**
 * List of register blocks.
 *
 * Register blocks are guaranteed to start at 0 and to be consecutively numbered.
 */
typedef enum dt_rstmgr_reg_block {
  kDtRstmgrRegBlockCore = 0, /**<  */
  kDtRstmgrRegBlockCount = 1, /**< \internal Number of register blocks */
} dt_rstmgr_reg_block_t;
 
/**
 * List of memories.
 *
 * Memories are guaranteed to start at 0 and to be consecutively numbered.
 */
typedef enum dt_rstmgr_memory {
  kDtRstmgrMemoryCount = 0, /**< \internal Number of memories */
} dt_rstmgr_memory_t;
 
/** Primary register block (associated with the "primary" set of registers that control the IP). */
static const dt_rstmgr_reg_block_t kDtRstmgrRegBlockPrimary = kDtRstmgrRegBlockCore;
 
/**
 * List of Alerts.
 *
 * Alerts are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_rstmgr_alert {
  kDtRstmgrAlertFatalFault = 0, /**< This fatal alert is triggered when a fatal structural fault is detected.
Structural faults include errors such as sparse fsm errors and tlul integrity errors. */
  kDtRstmgrAlertFatalCnstyFault = 1, /**< This fatal alert is triggered when a reset consistency fault is detected.
It is separated from the category above for clearer error collection and debug. */
  kDtRstmgrAlertCount = 2, /**< \internal Number of Alerts */
} dt_rstmgr_alert_t;
 
/**
 * List of clock ports.
 *
 * Clock ports are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_rstmgr_clock {
  kDtRstmgrClockClk = 0, /**< Clock port clk_i */
  kDtRstmgrClockAon = 1, /**< Clock port clk_aon_i */
  kDtRstmgrClockIoDiv4 = 2, /**< Clock port clk_io_div4_i */
  kDtRstmgrClockMain = 3, /**< Clock port clk_main_i */
  kDtRstmgrClockIo = 4, /**< Clock port clk_io_i */
  kDtRstmgrClockIoDiv2 = 5, /**< Clock port clk_io_div2_i */
  kDtRstmgrClockUsb = 6, /**< Clock port clk_usb_i */
  kDtRstmgrClockPor = 7, /**< Clock port clk_por_i */
  kDtRstmgrClockCount = 8, /**< \internal Number of clock ports */
} dt_rstmgr_clock_t;
 
/**
 * List of reset ports.
 *
 * Reset ports are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_rstmgr_reset {
  kDtRstmgrResetRst = 0, /**< Reset port rst_ni */
  kDtRstmgrResetPor = 1, /**< Reset port rst_por_ni */
  kDtRstmgrResetCount = 2, /**< \internal Number of reset ports */
} dt_rstmgr_reset_t;
 
/**
 * List of supported hardware features.
 */
#define OPENTITAN_RSTMGR_HAS_SW_RST_CHIP_RESET 1
#define OPENTITAN_RSTMGR_HAS_SW_RST_SPI_DEVICE_REQUEST 1
#define OPENTITAN_RSTMGR_HAS_SW_RST_SPI_DEVICE_ENABLE 1
#define OPENTITAN_RSTMGR_HAS_SW_RST_SPI_HOST0_REQUEST 1
#define OPENTITAN_RSTMGR_HAS_SW_RST_SPI_HOST0_ENABLE 1
#define OPENTITAN_RSTMGR_HAS_SW_RST_SPI_HOST1_REQUEST 1
#define OPENTITAN_RSTMGR_HAS_SW_RST_SPI_HOST1_ENABLE 1
#define OPENTITAN_RSTMGR_HAS_SW_RST_USB_REQUEST 1
#define OPENTITAN_RSTMGR_HAS_SW_RST_USB_ENABLE 1
#define OPENTITAN_RSTMGR_HAS_SW_RST_USB_AON_REQUEST 1
#define OPENTITAN_RSTMGR_HAS_SW_RST_USB_AON_ENABLE 1
#define OPENTITAN_RSTMGR_HAS_SW_RST_I2C0_REQUEST 1
#define OPENTITAN_RSTMGR_HAS_SW_RST_I2C0_ENABLE 1
#define OPENTITAN_RSTMGR_HAS_SW_RST_I2C1_REQUEST 1
#define OPENTITAN_RSTMGR_HAS_SW_RST_I2C1_ENABLE 1
#define OPENTITAN_RSTMGR_HAS_SW_RST_I2C2_REQUEST 1
#define OPENTITAN_RSTMGR_HAS_SW_RST_I2C2_ENABLE 1
#define OPENTITAN_RSTMGR_HAS_RESET_INFO_CAPTURE 1
#define OPENTITAN_RSTMGR_HAS_RESET_INFO_CLEAR 1
#define OPENTITAN_RSTMGR_HAS_ALERT_INFO_CAPTURE 1
#define OPENTITAN_RSTMGR_HAS_ALERT_INFO_ENABLE 1
#define OPENTITAN_RSTMGR_HAS_CPU_INFO_CAPTURE 1
#define OPENTITAN_RSTMGR_HAS_CPU_INFO_ENABLE 1
#define OPENTITAN_RSTMGR_HAS_ALERT_HANDLER_RESET_STATUS 1
 
 
 
/**
 * Get the rstmgr instance from an instance ID
 *
 * For example, `dt_uart_from_instance_id(kDtInstanceIdUart3) == kDtUart3`.
 *
 * @param inst_id Instance ID.
 * @return A rstmgr instance.
 *
 * **Note:** This function only makes sense if the instance ID has device type rstmgr,
 * otherwise the returned value is unspecified.
 */
dt_rstmgr_t dt_rstmgr_from_instance_id(dt_instance_id_t inst_id);
 
/**
 * Get the instance ID of an instance.
 *
 * @param dt Instance of rstmgr.
 * @return The instance ID of that instance.
 */
dt_instance_id_t dt_rstmgr_instance_id(dt_rstmgr_t dt);
 
/**
 * Get the register base address of an instance.
 *
 * @param dt Instance of rstmgr.
 * @param reg_block The register block requested.
 * @return The register base address of the requested block.
 */
uint32_t dt_rstmgr_reg_block(
    dt_rstmgr_t dt,
    dt_rstmgr_reg_block_t reg_block);
 
/**
 * Get the primary register base address of an instance.
 *
 * This is just a convenience function, equivalent to
 * `dt_rstmgr_reg_block(dt, kDtRstmgrRegBlockCore)`
 *
 * @param dt Instance of rstmgr.
 * @return The register base address of the primary register block.
 */
static inline uint32_t dt_rstmgr_primary_reg_block(
    dt_rstmgr_t dt) {
  return dt_rstmgr_reg_block(dt, kDtRstmgrRegBlockCore);
}
 
/**
 * Get the base address of a memory.
 *
 * @param dt Instance of rstmgr.
 * @param mem The memory requested.
 * @return The base address of the requested memory.
 */
uint32_t dt_rstmgr_memory_base(
    dt_rstmgr_t dt,
    dt_rstmgr_memory_t mem);
 
/**
 * Get the size of a memory.
 *
 * @param dt Instance of rstmgr.
 * @param mem The memory requested.
 * @return The size of the requested memory.
 */
uint32_t dt_rstmgr_memory_size(
    dt_rstmgr_t dt,
    dt_rstmgr_memory_t mem);
 
 
/**
 * Get the alert ID of a rstmgr alert for a given instance.
 *
 * **Note:** This function only makes sense if the instance is connected to the Alert Handler. For any
 * instances where the instance is not connected, the return value is unspecified.
 *
 * @param dt Instance of rstmgr.
 * @param alert A rstmgr alert.
 * @return The Alert Handler alert ID of the alert of this instance.
 */
dt_alert_id_t dt_rstmgr_alert_to_alert_id(
    dt_rstmgr_t dt,
    dt_rstmgr_alert_t alert);
 
/**
 * Convert a global alert ID to a local rstmgr alert type.
 *
 * @param dt Instance of rstmgr.
 * @param alert A global alert ID that belongs to this instance.
 * @return The rstmgr alert, or `kDtRstmgrAlertCount`.
 *
 * **Note:** This function assumes that the global alert ID belongs to the
 * instance of rstmgr passed in parameter. In other words, it must be the case
 * that `dt_rstmgr_instance_id(dt) == dt_alert_id_to_instance_id(alert)`. Otherwise,
 * this function will return `kDtRstmgrAlertCount`.
 */
dt_rstmgr_alert_t dt_rstmgr_alert_from_alert_id(
    dt_rstmgr_t dt,
    dt_alert_id_t alert);
 
 
 
/**
 * Get the clock signal connected to a clock port of an instance.
 *
 * @param dt Instance of rstmgr.
 * @param clk Clock port.
 * @return Clock signal.
 */
dt_clock_t dt_rstmgr_clock(
    dt_rstmgr_t dt,
    dt_rstmgr_clock_t clk);
 
/**
 * Get the reset signal connected to a reset port of an instance.
 *
 * @param dt Instance of rstmgr.
 * @param rst Reset port.
 * @return Reset signal.
 */
dt_reset_t dt_rstmgr_reset(
    dt_rstmgr_t dt,
    dt_rstmgr_reset_t rst);
 
 
 
/**
 * Get the number of software resets.
 *
 * @param dt Instance of rstmgr.
 * @return Number of software resets.
 */
size_t dt_rstmgr_sw_reset_count(dt_rstmgr_t dt);
 
/**
 * Get the reset ID of a software reset.
 *
 * The resets are ordered in the same way as they appear in the registers.
 *
 * @param dt Instance of rstmgr.
 * @param idx Index of the software reset, between 0 and `dt_rstmgr_sw_reset_count(dt)-1`.
 * @return Reset ID, or `kDtResetUnknown` for invalid parameters.
 */
dt_reset_t dt_rstmgr_sw_reset(dt_rstmgr_t dt, size_t idx);
 
/**
 * Description of a reset request source.
 *
 * A reset request source is always identified by the instance ID of the module where it comes
 * from. In principle, some instances could have several reset requests. If this is the case,
 * the `rst_req` can be used to distinguish between those. It should be cast to the
 * `dt_<ip>_reset_req_t` type of the corresponding IP.
 *
 * WARNING At the moment, three hardcoded reset requests are treated specially and have their
 * `reset_req` field set to `0` because there is no corresponding reset request declared by those
 * IPs:
 * - the main power glitch reset request, coming from the `pwrmgr`,
 * - the escalation reset request, coming from the `alert_handler`,
 * - the non-debug-module reset request, coming from the `rv_dm`.
 */
typedef struct dt_rstmgr_reset_req_src {
  dt_instance_id_t inst_id; /**< Instance ID of the source of this reset request. */
  size_t reset_req; /**< Index of the reset request signal for that instance. */
} dt_rstmgr_reset_req_src_t;
 
 
/**
 * Get the number of hardware reset requests.
 *
 * @param dt Instance of rstmgr.
 * @return Number of reset requests.
 */
size_t dt_rstmgr_hw_reset_req_src_count(dt_rstmgr_t dt);
 
/**
 * Get the description of a reset request.
 *
 * The reset requests are ordered as they appear in the registers.
 *
 * @param dt Instance of rstmgr.
 * @param idx Index of the reset request source, between 0 and
 *            `dt_pwrmgr_hw_reset_req_src_count(dt)-1`.
 * @return Description of the reset.
 */
dt_rstmgr_reset_req_src_t dt_rstmgr_hw_reset_req_src(dt_rstmgr_t dt, size_t idx);
 
 
 
#ifdef __cplusplus
}  // extern "C"
#endif  // __cplusplus
 
#endif  // OPENTITAN_DT_RSTMGR_H_