Software APIs
dt_rom_ctrl.h
Go to the documentation of this file.
1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Device table API auto-generated by `dtgen`
6
7#ifndef OPENTITAN_DT_ROM_CTRL_H_
8#define OPENTITAN_DT_ROM_CTRL_H_
9
10#ifdef __cplusplus
11extern "C" {
12#endif // __cplusplus
13
14/**
15 * @file
16 * @brief Device Tables (DT) for IP rom_ctrl and top earlgrey.
17 *
18 * This file contains the type definitions and global functions of the rom_ctrl.
19 */
20
21#include "hw/top/dt/dt_api.h"
22#include <stdint.h>
23
24
25
26/**
27 * List of instances.
28 */
29typedef enum dt_rom_ctrl {
30 kDtRomCtrl = 0, /**< rom_ctrl */
31 kDtRomCtrlFirst = 0, /**< \internal First instance */
32 kDtRomCtrlCount = 1, /**< \internal Number of instances */
34
35/**
36 * List of register blocks.
37 *
38 * Register blocks are guaranteed to start at 0 and to be consecutively numbered.
39 */
41 kDtRomCtrlRegBlockRegs = 0, /**< */
42 kDtRomCtrlRegBlockCount = 1, /**< \internal Number of register blocks */
44
45/**
46 * List of memories.
47 *
48 * Memories are guaranteed to start at 0 and to be consecutively numbered.
49 */
50typedef enum dt_rom_ctrl_memory {
51 kDtRomCtrlMemoryRom = 0, /**< */
52 kDtRomCtrlMemoryCount = 1, /**< \internal Number of memories */
54
55/** Primary register block (associated with the "primary" set of registers that control the IP). */
56static const dt_rom_ctrl_reg_block_t kDtRomCtrlRegBlockPrimary = kDtRomCtrlRegBlockRegs;
57
58/**
59 * List of Alerts.
60 *
61 * Alerts are guaranteed to be numbered consecutively from 0.
62 */
63typedef enum dt_rom_ctrl_alert {
64 kDtRomCtrlAlertFatal = 0, /**< A fatal error. Fatal alerts are non-recoverable and will be asserted until a hard reset. */
65 kDtRomCtrlAlertCount = 1, /**< \internal Number of Alerts */
67
68/**
69 * List of clock ports.
70 *
71 * Clock ports are guaranteed to be numbered consecutively from 0.
72 */
73typedef enum dt_rom_ctrl_clock {
74 kDtRomCtrlClockClk = 0, /**< Clock port clk_i */
75 kDtRomCtrlClockCount = 1, /**< \internal Number of clock ports */
77
78/**
79 * List of reset ports.
80 *
81 * Reset ports are guaranteed to be numbered consecutively from 0.
82 */
83typedef enum dt_rom_ctrl_reset {
84 kDtRomCtrlResetRst = 0, /**< Reset port rst_ni */
85 kDtRomCtrlResetCount = 1, /**< \internal Number of reset ports */
87
88/**
89 * List of supported hardware features.
90 */
91#define OPENTITAN_ROM_CTRL_HAS_SCRAMBLED 1
92#define OPENTITAN_ROM_CTRL_HAS_DIGESTS 1
93#define OPENTITAN_ROM_CTRL_HAS_EXP_DIGESTS 1
94
95
96
97/**
98 * Get the rom_ctrl instance from an instance ID
99 *
100 * For example, `dt_uart_from_instance_id(kDtInstanceIdUart3) == kDtUart3`.
101 *
102 * @param inst_id Instance ID.
103 * @return A rom_ctrl instance.
104 *
105 * **Note:** This function only makes sense if the instance ID has device type rom_ctrl,
106 * otherwise the returned value is unspecified.
107 */
109
110/**
111 * Get the instance ID of an instance.
112 *
113 * @param dt Instance of rom_ctrl.
114 * @return The instance ID of that instance.
115 */
117
118/**
119 * Get the register base address of an instance.
120 *
121 * @param dt Instance of rom_ctrl.
122 * @param reg_block The register block requested.
123 * @return The register base address of the requested block.
124 */
125uint32_t dt_rom_ctrl_reg_block(
126 dt_rom_ctrl_t dt,
127 dt_rom_ctrl_reg_block_t reg_block);
128
129/**
130 * Get the primary register base address of an instance.
131 *
132 * This is just a convenience function, equivalent to
133 * `dt_rom_ctrl_reg_block(dt, kDtRomCtrlRegBlockRegs)`
134 *
135 * @param dt Instance of rom_ctrl.
136 * @return The register base address of the primary register block.
137 */
138static inline uint32_t dt_rom_ctrl_primary_reg_block(
139 dt_rom_ctrl_t dt) {
140 return dt_rom_ctrl_reg_block(dt, kDtRomCtrlRegBlockRegs);
141}
142
143/**
144 * Get the base address of a memory.
145 *
146 * @param dt Instance of rom_ctrl.
147 * @param mem The memory requested.
148 * @return The base address of the requested memory.
149 */
151 dt_rom_ctrl_t dt,
153
154/**
155 * Get the size of a memory.
156 *
157 * @param dt Instance of rom_ctrl.
158 * @param mem The memory requested.
159 * @return The size of the requested memory.
160 */
162 dt_rom_ctrl_t dt,
164
165
166/**
167 * Get the alert ID of a rom_ctrl alert for a given instance.
168 *
169 * **Note:** This function only makes sense if the instance is connected to the Alert Handler. For any
170 * instances where the instance is not connected, the return value is unspecified.
171 *
172 * @param dt Instance of rom_ctrl.
173 * @param alert A rom_ctrl alert.
174 * @return The Alert Handler alert ID of the alert of this instance.
175 */
177 dt_rom_ctrl_t dt,
178 dt_rom_ctrl_alert_t alert);
179
180/**
181 * Convert a global alert ID to a local rom_ctrl alert type.
182 *
183 * @param dt Instance of rom_ctrl.
184 * @param alert A global alert ID that belongs to this instance.
185 * @return The rom_ctrl alert, or `kDtRomCtrlAlertCount`.
186 *
187 * **Note:** This function assumes that the global alert ID belongs to the
188 * instance of rom_ctrl passed in parameter. In other words, it must be the case
189 * that `dt_rom_ctrl_instance_id(dt) == dt_alert_id_to_instance_id(alert)`. Otherwise,
190 * this function will return `kDtRomCtrlAlertCount`.
191 */
193 dt_rom_ctrl_t dt,
194 dt_alert_id_t alert);
195
196
197
198/**
199 * Get the clock signal connected to a clock port of an instance.
200 *
201 * @param dt Instance of rom_ctrl.
202 * @param clk Clock port.
203 * @return Clock signal.
204 */
206 dt_rom_ctrl_t dt,
208
209/**
210 * Get the reset signal connected to a reset port of an instance.
211 *
212 * @param dt Instance of rom_ctrl.
213 * @param rst Reset port.
214 * @return Reset signal.
215 */
217 dt_rom_ctrl_t dt,
219
220
221
222#ifdef __cplusplus
223} // extern "C"
224#endif // __cplusplus
225
226#endif // OPENTITAN_DT_ROM_CTRL_H_