Software APIs
dt_otp_ctrl.h
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Device table API auto-generated by `dtgen`
6
7#ifndef OPENTITAN_DT_OTP_CTRL_H_
8#define OPENTITAN_DT_OTP_CTRL_H_
9
10#ifdef __cplusplus
11extern "C" {
12#endif // __cplusplus
13
14/**
15 * @file
16 * @brief Device Tables (DT) for IP otp_ctrl and top earlgrey.
17 *
18 * This file contains the type definitions and global functions of the otp_ctrl.
19 */
20
21#include "dt_api.h"
22#include <stdint.h>
23
24
25
26
27
28/**
29 * List of instances.
30 */
31typedef enum dt_otp_ctrl {
32 kDtOtpCtrl = 0, /**< otp_ctrl */
33 kDtOtpCtrlFirst = 0, /**< \internal First instance */
34 kDtOtpCtrlCount = 1, /**< \internal Number of instances */
36
37/**
38 * List of register blocks.
39 *
40 * Register blocks are guaranteed to start at 0 and to be consecutively numbered.
41 */
43 kDtOtpCtrlRegBlockCore = 0, /**< */
44 kDtOtpCtrlRegBlockCount = 1, /**< \internal Number of register blocks */
46
47/** Primary register block (associated with the "primary" set of registers that control the IP). */
48static const dt_otp_ctrl_reg_block_t kDtOtpCtrlRegBlockPrimary = kDtOtpCtrlRegBlockCore;
49
50/**
51 * List of IRQs.
52 *
53 * IRQs are guaranteed to be numbered consecutively from 0.
54 */
55typedef enum dt_otp_ctrl_irq {
56 kDtOtpCtrlIrqOtpOperationDone = 0, /**< A direct access command or digest calculation operation has completed. */
57 kDtOtpCtrlIrqOtpError = 1, /**< An error has occurred in the OTP controller. Check the !!ERR_CODE register to get more information. */
58 kDtOtpCtrlIrqCount = 2, /**< \internal Number of IRQs */
60
61/**
62 * List of Alerts.
63 *
64 * Alerts are guaranteed to be numbered consecutively from 0.
65 */
66typedef enum dt_otp_ctrl_alert {
67 kDtOtpCtrlAlertFatalMacroError = 0, /**< This alert triggers if hardware detects an uncorrectable error during an OTP transaction, for example an uncorrectable ECC error in the OTP array. */
68 kDtOtpCtrlAlertFatalCheckError = 1, /**< This alert triggers if any of the background checks fails. This includes the digest checks and concurrent ECC checks in the buffer registers. */
69 kDtOtpCtrlAlertFatalBusIntegError = 2, /**< This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. */
70 kDtOtpCtrlAlertFatalPrimOtpAlert = 3, /**< Fatal alert triggered inside the OTP primitive, including fatal TL-UL bus integrity faults of the test interface. */
71 kDtOtpCtrlAlertRecovPrimOtpAlert = 4, /**< Recoverable alert triggered inside the OTP primitive. */
72 kDtOtpCtrlAlertCount = 5, /**< \internal Number of Alerts */
74
75/**
76 * List of clock ports.
77 *
78 * Clock ports are guaranteed to be numbered consecutively from 0.
79 */
80typedef enum dt_otp_ctrl_clock {
81 kDtOtpCtrlClockClk = 0, /**< Clock port clk_i */
82 kDtOtpCtrlClockEdn = 1, /**< Clock port clk_edn_i */
83 kDtOtpCtrlClockCount = 2, /**< \internal Number of clock ports */
85
86/**
87 * List of reset ports.
88 *
89 * Reset ports are guaranteed to be numbered consecutively from 0.
90 */
91typedef enum dt_otp_ctrl_reset {
92 kDtOtpCtrlResetRst = 0, /**< Reset port rst_ni */
93 kDtOtpCtrlResetEdn = 1, /**< Reset port rst_edn_ni */
94 kDtOtpCtrlResetCount = 2, /**< \internal Number of reset ports */
96
97/**
98 * List of supported hardware features.
99 */
100#define OPENTITAN_OTP_CTRL_HAS_PARTITION_VENDOR_TEST 1
101#define OPENTITAN_OTP_CTRL_HAS_PARTITION_CREATOR_SW_CFG 1
102#define OPENTITAN_OTP_CTRL_HAS_PARTITION_OWNER_SW_CFG 1
103#define OPENTITAN_OTP_CTRL_HAS_INIT 1
104#define OPENTITAN_OTP_CTRL_HAS_ENTROPY_READ 1
105#define OPENTITAN_OTP_CTRL_HAS_KEY_DERIVATION 1
106#define OPENTITAN_OTP_CTRL_HAS_PROGRAM 1
107#define OPENTITAN_OTP_CTRL_HAS_PARTITION_SECRET0 1
108#define OPENTITAN_OTP_CTRL_HAS_PARTITION_SECRET1 1
109#define OPENTITAN_OTP_CTRL_HAS_PARTITION_SECRET2 1
110#define OPENTITAN_OTP_CTRL_HAS_PARTITION_LIFE_CYCLE 1
111#define OPENTITAN_OTP_CTRL_HAS_PARTITIONS_FEATURE_READ_LOCK 1
112#define OPENTITAN_OTP_CTRL_HAS_PARTITIONS_FEATURE_WRITE_LOCK 1
113#define OPENTITAN_OTP_CTRL_HAS_ERROR_HANDLING_RECOVERABLE 1
114#define OPENTITAN_OTP_CTRL_HAS_ERROR_HANDLING_FATAL 1
115#define OPENTITAN_OTP_CTRL_HAS_BACKGROUND_CHECK_CHECK_TIMEOUT 1
116#define OPENTITAN_OTP_CTRL_HAS_BACKGROUND_CHECK_INTEGRITY_CHECK_PERIOD 1
117#define OPENTITAN_OTP_CTRL_HAS_BACKGROUND_CHECK_CONSISTENCY_CHECK_PERIOD 1
118
119
120
121/**
122 * Get the otp_ctrl instance from an instance ID
123 *
124 * For example, `dt_uart_from_instance_id(kDtInstanceIdUart3) == kDtUart3`.
125 *
126 * @param inst_id Instance ID.
127 * @return A otp_ctrl instance.
128 *
129 * **Note:** This function only makes sense if the instance ID has device type otp_ctrl,
130 * otherwise the returned value is unspecified.
131 */
133
134/**
135 * Get the instance ID of an instance.
136 *
137 * @param dt Instance of otp_ctrl.
138 * @return The instance ID of that instance.
139 */
141
142/**
143 * Get the register base address of an instance.
144 *
145 * @param dt Instance of otp_ctrl.
146 * @param reg_block The register block requested.
147 * @return The register base address of the requested block.
148 */
149uint32_t dt_otp_ctrl_reg_block(
150 dt_otp_ctrl_t dt,
151 dt_otp_ctrl_reg_block_t reg_block);
152
153/**
154 * Get the primary register base address of an instance.
155 *
156 * This is just a convenience function, equivalent to
157 * `dt_otp_ctrl_reg_block(dt, kDtOtpCtrlRegBlockCore)`
158 *
159 * @param dt Instance of otp_ctrl.
160 * @return The register base address of the primary register block.
161 */
162static inline uint32_t dt_otp_ctrl_primary_reg_block(
163 dt_otp_ctrl_t dt) {
164 return dt_otp_ctrl_reg_block(dt, kDtOtpCtrlRegBlockCore);
165}
166
167/**
168 * Get the PLIC ID of a otp_ctrl IRQ for a given instance.
169 *
170 * If the instance is not connected to the PLIC, this function
171 * will return `kDtPlicIrqIdNone`.
172 *
173 * @param dt Instance of otp_ctrl.
174 * @param irq A otp_ctrl IRQ.
175 * @return The PLIC ID of the IRQ of this instance.
176 */
178 dt_otp_ctrl_t dt,
180
181/**
182 * Convert a global IRQ ID to a local otp_ctrl IRQ type.
183 *
184 * @param dt Instance of otp_ctrl.
185 * @param irq A PLIC ID that belongs to this instance.
186 * @return The otp_ctrl IRQ, or `kDtOtpCtrlIrqCount`.
187 *
188 * **Note:** This function assumes that the PLIC ID belongs to the instance
189 * of otp_ctrl passed in parameter. In other words, it must be the case that
190 * `dt_otp_ctrl_instance_id(dt) == dt_plic_id_to_instance_id(irq)`. Otherwise, this function
191 * will return `kDtOtpCtrlIrqCount`.
192 */
194 dt_otp_ctrl_t dt,
195 dt_plic_irq_id_t irq);
196
197
198/**
199 * Get the alert ID of a otp_ctrl alert for a given instance.
200 *
201 * **Note:** This function only makes sense if the instance is connected to the Alert Handler. For any
202 * instances where the instance is not connected, the return value is unspecified.
203 *
204 * @param dt Instance of otp_ctrl.
205 * @param alert A otp_ctrl alert.
206 * @return The Alert Handler alert ID of the alert of this instance.
207 */
209 dt_otp_ctrl_t dt,
210 dt_otp_ctrl_alert_t alert);
211
212/**
213 * Convert a global alert ID to a local otp_ctrl alert type.
214 *
215 * @param dt Instance of otp_ctrl.
216 * @param alert A global alert ID that belongs to this instance.
217 * @return The otp_ctrl alert, or `kDtOtpCtrlAlertCount`.
218 *
219 * **Note:** This function assumes that the global alert ID belongs to the
220 * instance of otp_ctrl passed in parameter. In other words, it must be the case
221 * that `dt_otp_ctrl_instance_id(dt) == dt_alert_id_to_instance_id(alert)`. Otherwise,
222 * this function will return `kDtOtpCtrlAlertCount`.
223 */
225 dt_otp_ctrl_t dt,
226 dt_alert_id_t alert);
227
228
229
230/**
231 * Get the clock signal connected to a clock port of an instance.
232 *
233 * @param dt Instance of otp_ctrl.
234 * @param clk Clock port.
235 * @return Clock signal.
236 */
238 dt_otp_ctrl_t dt,
240
241/**
242 * Get the reset signal connected to a reset port of an instance.
243 *
244 * @param dt Instance of otp_ctrl.
245 * @param rst Reset port.
246 * @return Reset signal.
247 */
249 dt_otp_ctrl_t dt,
251
252
253
254/**
255 * Description of an OTP partition.
256 *
257 */
258typedef struct dt_otp_partition_info {
259 uint32_t start_addr; /**< The absolute OTP address at which this partition starts */
260 size_t size; /**< Size (in bytes) of the partition, excluding the digest field */
261 uint32_t digest_addr; /**< The absolute OTP address at which this partition's digest starts */
262 uint32_t align_mask; /**< The alignment mask for this partition */
264
265
266/**
267 * SW readable OTP partition identifier.
268 */
269typedef enum otp_partition {
270 kOtpPartitionVendorTest = 0, /**< */
271 kOtpPartitionCreatorSwCfg = 1, /**< */
272 kOtpPartitionOwnerSwCfg = 2, /**< */
273 kOtpPartitionRotCreatorAuthCodesign = 3, /**< */
274 kOtpPartitionRotCreatorAuthState = 4, /**< */
275 kOtpPartitionHwCfg0 = 5, /**< */
276 kOtpPartitionHwCfg1 = 6, /**< */
277 kOtpPartitionCount = 7, /**< \internal */
279
280/**
281 * Get a SW readable OTP partition information.
282 *
283 * @param dt Instance of otp_ctrl.
284 * @param partition OTP partition identifier.
285 * @return OTP partition information.
286 */
289
290
291
292#ifdef __cplusplus
293} // extern "C"
294#endif // __cplusplus
295
296#endif // OPENTITAN_DT_OTP_CTRL_H_