dt_i2c.h

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// Copyright lowRISC contributors (OpenTitan project).
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Device table API auto-generated by `dtgen`
 
#ifndef OPENTITAN_DT_I2C_H_
#define OPENTITAN_DT_I2C_H_
 
#ifdef __cplusplus
extern "C" {
#endif  // __cplusplus
 
/**
 * @file
 * @brief Device Tables (DT) for IP i2c and top earlgrey.
 *
 * This file contains the type definitions and global functions of the i2c.
 */
 
#include "dt_api.h"
#include <stdint.h>
 
 
 
/**
 * List of instances.
 */
typedef enum dt_i2c {
  kDtI2c0 = 0, /**< i2c0 */
  kDtI2c1 = 1, /**< i2c1 */
  kDtI2c2 = 2, /**< i2c2 */
  kDtI2cFirst = 0, /**< \internal First instance */
  kDtI2cCount = 3, /**< \internal Number of instances */
} dt_i2c_t;
 
/**
 * List of register blocks.
 *
 * Register blocks are guaranteed to start at 0 and to be consecutively numbered.
 */
typedef enum dt_i2c_reg_block {
  kDtI2cRegBlockCore = 0, /**<  */
  kDtI2cRegBlockCount = 1, /**< \internal Number of register blocks */
} dt_i2c_reg_block_t;
 
/** Primary register block (associated with the "primary" set of registers that control the IP). */
static const dt_i2c_reg_block_t kDtI2cRegBlockPrimary = kDtI2cRegBlockCore;
 
/**
 * List of IRQs.
 *
 * IRQs are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_i2c_irq {
  kDtI2cIrqFmtThreshold = 0, /**< host mode interrupt: asserted whilst the FMT FIFO level is below the low threshold. This is a level status interrupt. */
  kDtI2cIrqRxThreshold = 1, /**< host mode interrupt: asserted whilst the RX FIFO level is above the high threshold. This is a level status interrupt. */
  kDtI2cIrqAcqThreshold = 2, /**< target mode interrupt: asserted whilst the ACQ FIFO level is above the high threshold. This is a level status interrupt. */
  kDtI2cIrqRxOverflow = 3, /**< host mode interrupt: raised if the RX FIFO has overflowed. */
  kDtI2cIrqControllerHalt = 4, /**< host mode interrupt: raised if the controller FSM is halted, such as on an unexpected NACK or lost arbitration.
Check !!CONTROLLER_EVENTS for the reason.
The interrupt will be released when the bits in !!CONTROLLER_EVENTS are cleared. */
  kDtI2cIrqSclInterference = 5, /**< host mode interrupt: raised if the SCL line drops early (not supported without clock synchronization). */
  kDtI2cIrqSdaInterference = 6, /**< host mode interrupt: raised if the SDA line goes low when host is trying to assert high */
  kDtI2cIrqStretchTimeout = 7, /**< host mode interrupt: raised if target stretches the clock beyond the allowed timeout period */
  kDtI2cIrqSdaUnstable = 8, /**< host mode interrupt: raised if the target does not assert a constant value of SDA during transmission. */
  kDtI2cIrqCmdComplete = 9, /**< host and target mode interrupt.
In host mode, raised if the host issues a repeated START or terminates the transaction by issuing STOP.
In target mode, raised if the external host issues a STOP or repeated START. */
  kDtI2cIrqTxStretch = 10, /**< target mode interrupt: raised if the target is stretching clocks for a read command. This is a level status interrupt. */
  kDtI2cIrqTxThreshold = 11, /**< target mode interrupt: asserted whilst the TX FIFO level is below the low threshold. This is a level status interrupt. */
  kDtI2cIrqAcqStretch = 12, /**< target mode interrupt: raised if the target is stretching clocks due to full ACQ FIFO or zero count in !!TARGET_ACK_CTRL.NBYTES (if enabled). This is a level status interrupt. */
  kDtI2cIrqUnexpStop = 13, /**< target mode interrupt: raised if STOP is received without a preceding NACK during an external host read. */
  kDtI2cIrqHostTimeout = 14, /**< target mode interrupt: raised if the host stops sending the clock during an ongoing transaction. */
  kDtI2cIrqCount = 15, /**< \internal Number of IRQs */
} dt_i2c_irq_t;
 
/**
 * List of Alerts.
 *
 * Alerts are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_i2c_alert {
  kDtI2cAlertFatalFault = 0, /**< This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. */
  kDtI2cAlertCount = 1, /**< \internal Number of Alerts */
} dt_i2c_alert_t;
 
/**
 * List of clock ports.
 *
 * Clock ports are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_i2c_clock {
  kDtI2cClockClk = 0, /**< Clock port clk_i */
  kDtI2cClockCount = 1, /**< \internal Number of clock ports */
} dt_i2c_clock_t;
 
/**
 * List of reset ports.
 *
 * Reset ports are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_i2c_reset {
  kDtI2cResetRst = 0, /**< Reset port rst_ni */
  kDtI2cResetCount = 1, /**< \internal Number of reset ports */
} dt_i2c_reset_t;
 
/**
 * List of peripheral I/O.
 *
 * Peripheral I/O are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_i2c_periph_io {
  kDtI2cPeriphIoSda = 0, /**<  */
  kDtI2cPeriphIoScl = 1, /**<  */
  kDtI2cPeriphIoCount = 2, /**< \internal Number of peripheral I/O */
} dt_i2c_periph_io_t;
 
/**
 * List of supported hardware features.
 */
#define OPENTITAN_I2C_HAS_MODE_HOST 1
#define OPENTITAN_I2C_HAS_MODE_TARGET 1
#define OPENTITAN_I2C_HAS_MODE_ACKCONTROL 1
#define OPENTITAN_I2C_HAS_SPEED_STANDARD 1
#define OPENTITAN_I2C_HAS_SPEED_FAST 1
#define OPENTITAN_I2C_HAS_SPEED_FASTPLUS 1
#define OPENTITAN_I2C_HAS_OVERRIDE 1
#define OPENTITAN_I2C_HAS_OPERATION_READ 1
#define OPENTITAN_I2C_HAS_OPERATION_WRITE 1
#define OPENTITAN_I2C_HAS_PROTOCOL_CLOCKSTRETCHING 1
#define OPENTITAN_I2C_HAS_PROTOCOL_NACK 1
#define OPENTITAN_I2C_HAS_PROTOCOL_REPEATEDSTART 1
 
 
 
/**
 * Get the i2c instance from an instance ID
 *
 * For example, `dt_uart_from_instance_id(kDtInstanceIdUart3) == kDtUart3`.
 *
 * @param inst_id Instance ID.
 * @return A i2c instance.
 *
 * **Note:** This function only makes sense if the instance ID has device type i2c,
 * otherwise the returned value is unspecified.
 */
dt_i2c_t dt_i2c_from_instance_id(dt_instance_id_t inst_id);
 
/**
 * Get the instance ID of an instance.
 *
 * @param dt Instance of i2c.
 * @return The instance ID of that instance.
 */
dt_instance_id_t dt_i2c_instance_id(dt_i2c_t dt);
 
/**
 * Get the register base address of an instance.
 *
 * @param dt Instance of i2c.
 * @param reg_block The register block requested.
 * @return The register base address of the requested block.
 */
uint32_t dt_i2c_reg_block(
    dt_i2c_t dt,
    dt_i2c_reg_block_t reg_block);
 
/**
 * Get the primary register base address of an instance.
 *
 * This is just a convenience function, equivalent to
 * `dt_i2c_reg_block(dt, kDtI2cRegBlockCore)`
 *
 * @param dt Instance of i2c.
 * @return The register base address of the primary register block.
 */
static inline uint32_t dt_i2c_primary_reg_block(
    dt_i2c_t dt) {
  return dt_i2c_reg_block(dt, kDtI2cRegBlockCore);
}
 
/**
 * Get the PLIC ID of a i2c IRQ for a given instance.
 *
 * If the instance is not connected to the PLIC, this function
 * will return `kDtPlicIrqIdNone`.
 *
 * @param dt Instance of i2c.
 * @param irq A i2c IRQ.
 * @return The PLIC ID of the IRQ of this instance.
 */
dt_plic_irq_id_t dt_i2c_irq_to_plic_id(
    dt_i2c_t dt,
    dt_i2c_irq_t irq);
 
/**
 * Convert a global IRQ ID to a local i2c IRQ type.
 *
 * @param dt Instance of i2c.
 * @param irq A PLIC ID that belongs to this instance.
 * @return The i2c IRQ, or `kDtI2cIrqCount`.
 *
 * **Note:** This function assumes that the PLIC ID belongs to the instance
 * of i2c passed in parameter. In other words, it must be the case that
 * `dt_i2c_instance_id(dt) == dt_plic_id_to_instance_id(irq)`. Otherwise, this function
 * will return `kDtI2cIrqCount`.
 */
dt_i2c_irq_t dt_i2c_irq_from_plic_id(
    dt_i2c_t dt,
    dt_plic_irq_id_t irq);
 
 
/**
 * Get the alert ID of a i2c alert for a given instance.
 *
 * **Note:** This function only makes sense if the instance is connected to the Alert Handler. For any
 * instances where the instance is not connected, the return value is unspecified.
 *
 * @param dt Instance of i2c.
 * @param alert A i2c alert.
 * @return The Alert Handler alert ID of the alert of this instance.
 */
dt_alert_id_t dt_i2c_alert_to_alert_id(
    dt_i2c_t dt,
    dt_i2c_alert_t alert);
 
/**
 * Convert a global alert ID to a local i2c alert type.
 *
 * @param dt Instance of i2c.
 * @param alert A global alert ID that belongs to this instance.
 * @return The i2c alert, or `kDtI2cAlertCount`.
 *
 * **Note:** This function assumes that the global alert ID belongs to the
 * instance of i2c passed in parameter. In other words, it must be the case
 * that `dt_i2c_instance_id(dt) == dt_alert_id_to_instance_id(alert)`. Otherwise,
 * this function will return `kDtI2cAlertCount`.
 */
dt_i2c_alert_t dt_i2c_alert_from_alert_id(
    dt_i2c_t dt,
    dt_alert_id_t alert);
 
 
/**
 * Get the peripheral I/O description of an instance.
 *
 * @param dt Instance of i2c.
 * @param sig Requested peripheral I/O.
 * @return Description of the requested peripheral I/O for this instance.
 */
dt_periph_io_t dt_i2c_periph_io(
    dt_i2c_t dt,
    dt_i2c_periph_io_t sig);
 
/**
 * Get the clock signal connected to a clock port of an instance.
 *
 * @param dt Instance of i2c.
 * @param clk Clock port.
 * @return Clock signal.
 */
dt_clock_t dt_i2c_clock(
    dt_i2c_t dt,
    dt_i2c_clock_t clk);
 
/**
 * Get the reset signal connected to a reset port of an instance.
 *
 * @param dt Instance of i2c.
 * @param rst Reset port.
 * @return Reset signal.
 */
dt_reset_t dt_i2c_reset(
    dt_i2c_t dt,
    dt_i2c_reset_t rst);
 
 
 
#ifdef __cplusplus
}  // extern "C"
#endif  // __cplusplus
 
#endif  // OPENTITAN_DT_I2C_H_